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Searched refs:wm_with_clock_ranges (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dsmu_helper.c714 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges) in smu_set_watermarks_for_clocks_ranges() argument
719 if (!table || !wm_with_clock_ranges) in smu_set_watermarks_for_clocks_ranges()
722 if (wm_with_clock_ranges->num_wm_dmif_sets > 4 || wm_with_clock_ranges->num_wm_mcif_sets > 4) in smu_set_watermarks_for_clocks_ranges()
725 for (i = 0; i < wm_with_clock_ranges->num_wm_dmif_sets; i++) { in smu_set_watermarks_for_clocks_ranges()
728 (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz / in smu_set_watermarks_for_clocks_ranges()
732 (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz / in smu_set_watermarks_for_clocks_ranges()
736 (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz / in smu_set_watermarks_for_clocks_ranges()
740 (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz / in smu_set_watermarks_for_clocks_ranges()
743 wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id; in smu_set_watermarks_for_clocks_ranges()
746 for (i = 0; i < wm_with_clock_ranges->num_wm_mcif_sets; i++) { in smu_set_watermarks_for_clocks_ranges()
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H A Dsmu_helper.h135 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
H A Dsmu10_hwmgr.c1374 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges; in smu10_set_watermarks_for_clocks_ranges() local
1379 smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges); in smu10_set_watermarks_for_clocks_ranges()
H A Dvega12_hwmgr.c2012 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges; in vega12_set_watermarks_for_clocks_ranges() local
2017 smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges); in vega12_set_watermarks_for_clocks_ranges()
H A Dvega20_hwmgr.c2953 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges; in vega20_set_watermarks_for_clocks_ranges() local
2958 smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges); in vega20_set_watermarks_for_clocks_ranges()
H A Dvega10_hwmgr.c4551 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_range; in vega10_set_watermarks_for_clocks_ranges() local
4555 smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges); in vega10_set_watermarks_for_clocks_ranges()
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_pp_smu.c403 struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges) in dm_pp_notify_wm_clock_changes() argument
414 (void *)wm_with_clock_ranges)) in dm_pp_notify_wm_clock_changes()
471 struct dm_pp_wm_sets_with_clock_ranges_soc15 wm_with_clock_ranges; in pp_rv_set_wm_ranges() local
472 …struct dm_pp_clock_range_for_dmif_wm_set_soc15 *wm_dce_clocks = wm_with_clock_ranges.wm_dmif_clock… in pp_rv_set_wm_ranges()
473 …struct dm_pp_clock_range_for_mcif_wm_set_soc15 *wm_soc_clocks = wm_with_clock_ranges.wm_mcif_clock… in pp_rv_set_wm_ranges()
476 wm_with_clock_ranges.num_wm_dmif_sets = ranges->num_reader_wm_sets; in pp_rv_set_wm_ranges()
477 wm_with_clock_ranges.num_wm_mcif_sets = ranges->num_writer_wm_sets; in pp_rv_set_wm_ranges()
479 for (i = 0; i < wm_with_clock_ranges.num_wm_dmif_sets; i++) { in pp_rv_set_wm_ranges()
495 for (i = 0; i < wm_with_clock_ranges.num_wm_mcif_sets; i++) { in pp_rv_set_wm_ranges()
512 &wm_with_clock_ranges); in pp_rv_set_wm_ranges()
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddm_services.h207 struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges);