Searched refs:vu32 (Results 1 – 16 of 16) sorted by relevance
486 int group_num = val.vu32; in mlx5_devlink_large_group_num_validate()502 return (val.vu32 >= 64 && val.vu32 <= 4096) ? 0 : -EINVAL; in mlx5_devlink_eq_depth_validate()510 return val.vu32 ? 0 : -EINVAL; in mlx5_devlink_hairpin_num_queues_validate()519 u32 val32 = val.vu32; in mlx5_devlink_hairpin_queue_size_validate()541 u32 val32 = val.vu32; in mlx5_devlink_num_doorbells_validate()568 value.vu32 = link_speed64; in mlx5_devlink_hairpin_params_init_values()572 value.vu32 = in mlx5_devlink_hairpin_params_init_values()606 value.vu32 = ESW_OFFLOADS_DEFAULT_NUM_GROUPS; in mlx5_devlink_set_params_init_values()612 value.vu32 = MLX5_COMP_EQ_SIZE; in mlx5_devlink_set_params_init_values()617 value.vu32 = MLX5_NUM_ASYNC_EQE; in mlx5_devlink_set_params_init_values()[all …]
153 return err ? MLX5_DEFAULT_NUM_DOORBELLS : val.vu32; in mlx5e_get_devlink_param_num_doorbells()
639 return val.vu32; in async_eq_depth_devlink_param_get()979 return val.vu32; in comp_eq_depth_devlink_param_get()
531 return val.vu32; in max_uc_list_get_devlink_param()
1466 esw->params.large_group_num = val.vu32; in mlx5_eswitch_get_devlink_param()
1167 params.log_num_packets = ilog2(val.vu32); in mlx5e_hairpin_flow_add()1183 params.num_channels = val.vu32; in mlx5e_hairpin_flow_add()
21 pf->max_mac_per_vf = ctx->val.vu32; in i40e_max_mac_per_vf_set()32 ctx->val.vu32 = pf->max_mac_per_vf; in i40e_max_mac_per_vf_get()
654 ctx->val.vu32 = 0; in mlx5_devlink_total_vfs_get()664 ctx->val.vu32 = MLX5_GET(nv_global_pci_conf, data, total_vfs); in mlx5_devlink_total_vfs_get()674 ctx->val.vu32 = MLX5_GET(nv_pf_pci_conf, data, total_vf); in mlx5_devlink_total_vfs_get()725 MLX5_SET(nv_pf_pci_conf, data, total_vf, ctx->val.vu32); in mlx5_devlink_total_vfs_set()
1222 pf->msix.min = val.vu32; in ice_set_min_max_msix()1228 pf->msix.max = val.vu32; in ice_set_min_max_msix()1610 if (val.vu32 > pf->hw.func_caps.common_cap.num_msix_vectors) in ice_devlink_msix_max_pf_validate()1621 if (val.vu32 < ICE_MIN_MSIX) in ice_devlink_msix_min_pf_validate()1789 value.vu32 = pf->msix.max; in ice_devlink_register_params()1793 value.vu32 = pf->msix.min; in ice_devlink_register_params()
698 val32 = src->vu32; in bnxt_copy_to_nvm_data()718 dst->vu32 = val32; in bnxt_copy_from_nvm_data()771 *nvm_cfg_ver = ver.vu32; in bnxt_hwrm_get_nvm_cfg_ver()1163 if (val.vu32 > max_val) { in bnxt_dl_msix_validate()
537 ctx->val.vu32 = nsim_dev->test2; in nsim_devlink_param_test2_get()548 nsim_dev->test2 = ctx->val.vu32; in nsim_devlink_param_test2_set()559 ctx->val.vu32 = NSIM_DEV_TEST2_DEFAULT; in nsim_devlink_param_test2_get_default()597 value.vu32 = nsim_dev->max_macs; in nsim_devlink_set_params_init_values()617 nsim_dev->max_macs = saved_value.vu32; in nsim_devlink_param_load_driverinit_values()
232 if (nla_put_u32(msg, nla_type, val.vu32)) in devlink_nl_param_value_put()531 value->vu32 = nla_get_u32(param_data); in devlink_param_value_get_from_info()
1187 int dwrr_mtu = val.vu32; in rvu_af_dl_dwrr_mtu_validate()1228 dwrr_mtu = convert_bytes_to_dwrr_mtu(ctx->val.vu32); in rvu_af_dl_dwrr_mtu_set()1248 ctx->val.vu32 = convert_dwrr_mtu_to_bytes(dwrr_mtu); in rvu_af_dl_dwrr_mtu_get()
1501 ctx->val.vu32 = tcam->vregion_rehash_intrvl; in mlxsw_sp_acl_tcam_region_rehash_intrvl_get()1515 u32 val = ctx->val.vu32; in mlxsw_sp_acl_tcam_region_rehash_intrvl_set()
440 u32 vu32; member
219 u32 value = val.vu32; in mlx4_devlink_max_macs_validate()271 value.vu32 = 1UL << log_num_mac; in mlx4_devlink_set_params_init_values()3951 log_num_mac = order_base_2(saved_value.vu32); in mlx4_devlink_param_load_driverinit_values()