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Searched refs:vpu (Results 1 – 25 of 137) sorted by relevance

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/linux/drivers/media/platform/mediatek/mdp3/
H A Dmtk-mdp3-vpu.c14 static inline struct mdp_dev *vpu_to_mdp(struct mdp_vpu_dev *vpu) in vpu_to_mdp() argument
16 return container_of(vpu, struct mdp_dev, vpu); in vpu_to_mdp()
19 static int mdp_vpu_shared_mem_alloc(struct mdp_vpu_dev *vpu) in mdp_vpu_shared_mem_alloc() argument
23 if (IS_ERR_OR_NULL(vpu)) in mdp_vpu_shared_mem_alloc()
26 dev = scp_get_device(vpu->scp); in mdp_vpu_shared_mem_alloc()
28 if (!vpu->param) { in mdp_vpu_shared_mem_alloc()
29 vpu->param = dma_alloc_wc(dev, vpu->param_size, in mdp_vpu_shared_mem_alloc()
30 &vpu->param_addr, GFP_KERNEL); in mdp_vpu_shared_mem_alloc()
31 if (!vpu->param) in mdp_vpu_shared_mem_alloc()
35 if (!vpu->work) { in mdp_vpu_shared_mem_alloc()
[all …]
/linux/drivers/media/platform/mediatek/vpu/
H A Dmtk_vpu.c227 static inline void vpu_cfg_writel(struct mtk_vpu *vpu, u32 val, u32 offset) in vpu_cfg_writel() argument
229 writel(val, vpu->reg.cfg + offset); in vpu_cfg_writel()
232 static inline u32 vpu_cfg_readl(struct mtk_vpu *vpu, u32 offset) in vpu_cfg_readl() argument
234 return readl(vpu->reg.cfg + offset); in vpu_cfg_readl()
237 static inline bool vpu_running(struct mtk_vpu *vpu) in vpu_running() argument
239 return vpu_cfg_readl(vpu, VPU_RESET) & BIT(0); in vpu_running()
242 static void vpu_clock_disable(struct mtk_vpu *vpu) in vpu_clock_disable() argument
245 mutex_lock(&vpu->vpu_mutex); in vpu_clock_disable()
246 if (!--vpu->wdt_refcnt) in vpu_clock_disable()
247 vpu_cfg_writel(vpu, in vpu_clock_disable()
[all …]
/linux/drivers/media/platform/amphion/
H A Dvpu_drv.c32 void vpu_writel(struct vpu_dev *vpu, u32 reg, u32 val) in vpu_writel() argument
34 writel(val, vpu->base + reg); in vpu_writel()
37 u32 vpu_readl(struct vpu_dev *vpu, u32 reg) in vpu_readl() argument
39 return readl(vpu->base + reg); in vpu_readl()
42 static void vpu_dev_get(struct vpu_dev *vpu) in vpu_dev_get() argument
44 if (atomic_inc_return(&vpu->ref_vpu) == 1 && vpu->res->setup) in vpu_dev_get()
45 vpu->res->setup(vpu); in vpu_dev_get()
48 static void vpu_dev_put(struct vpu_dev *vpu) in vpu_dev_put() argument
50 atomic_dec(&vpu->ref_vpu); in vpu_dev_put()
53 static void vpu_enc_get(struct vpu_dev *vpu) in vpu_enc_get() argument
[all …]
H A Dvpu_imx8q.c42 int vpu_imx8q_setup_dec(struct vpu_dev *vpu) in vpu_imx8q_setup_dec() argument
46 vpu_writel(vpu, offset + MFD_BLK_CTRL_MFD_SYS_CLOCK_ENABLE_SET, 0x1f); in vpu_imx8q_setup_dec()
47 vpu_writel(vpu, offset + MFD_BLK_CTRL_MFD_SYS_RESET_SET, 0xffffffff); in vpu_imx8q_setup_dec()
52 int vpu_imx8q_setup_enc(struct vpu_dev *vpu) in vpu_imx8q_setup_enc() argument
57 int vpu_imx8q_setup(struct vpu_dev *vpu) in vpu_imx8q_setup() argument
61 vpu_readl(vpu, offset + 0x108); in vpu_imx8q_setup()
63 vpu_writel(vpu, offset + SCB_BLK_CTRL_SCB_CLK_ENABLE_SET, 0x1); in vpu_imx8q_setup()
64 vpu_writel(vpu, offset + 0x190, 0xffffffff); in vpu_imx8q_setup()
65 vpu_writel(vpu, offset + SCB_BLK_CTRL_XMEM_RESET_SET, 0xffffffff); in vpu_imx8q_setup()
66 vpu_writel(vpu, offset + SCB_BLK_CTRL_SCB_CLK_ENABLE_SET, 0xE); in vpu_imx8q_setup()
[all …]
/linux/drivers/remoteproc/
H A Dingenic_rproc.c61 struct vpu { struct
71 struct vpu *vpu = rproc->priv; in ingenic_rproc_prepare() local
75 ret = clk_bulk_prepare_enable(ARRAY_SIZE(vpu->clks), vpu->clks); in ingenic_rproc_prepare()
77 dev_err(vpu->dev, "Unable to start clocks: %d\n", ret); in ingenic_rproc_prepare()
84 struct vpu *vpu = rproc->priv; in ingenic_rproc_unprepare() local
86 clk_bulk_disable_unprepare(ARRAY_SIZE(vpu->clks), vpu->clks); in ingenic_rproc_unprepare()
93 struct vpu *vpu = rproc->priv; in ingenic_rproc_start() local
96 enable_irq(vpu->irq); in ingenic_rproc_start()
100 writel(ctrl, vpu->aux_base + REG_AUX_CTRL); in ingenic_rproc_start()
107 struct vpu *vpu = rproc->priv; in ingenic_rproc_stop() local
[all …]
/linux/drivers/media/platform/verisilicon/
H A Dhantro_g2_hevc_dec.c13 struct hantro_dev *vpu = ctx->dev; in prepare_tile_info_buffer() local
28 hantro_reg_write(vpu, &g2_tile_e, tiles_enabled); in prepare_tile_info_buffer()
46 hantro_reg_write(vpu, &g2_num_tile_rows, num_tile_rows); in prepare_tile_info_buffer()
47 hantro_reg_write(vpu, &g2_num_tile_cols, num_tile_cols); in prepare_tile_info_buffer()
94 hantro_reg_write(vpu, &g2_num_tile_rows, 1); in prepare_tile_info_buffer()
95 hantro_reg_write(vpu, &g2_num_tile_cols, 1); in prepare_tile_info_buffer()
147 struct hantro_dev *vpu = ctx->dev; in set_params() local
153 hantro_reg_write(vpu, &g2_bit_depth_y_minus8, sps->bit_depth_luma_minus8); in set_params()
154 hantro_reg_write(vpu, &g2_bit_depth_c_minus8, sps->bit_depth_chroma_minus8); in set_params()
156 hantro_reg_write(vpu, &g2_hdr_skip_length, compute_header_skip_length(ctx)); in set_params()
[all …]
H A Dhantro_drv.c62 static void hantro_job_finish_no_pm(struct hantro_dev *vpu, in hantro_job_finish_no_pm() argument
89 static void hantro_job_finish(struct hantro_dev *vpu, in hantro_job_finish() argument
93 pm_runtime_put_autosuspend(vpu->dev); in hantro_job_finish()
95 clk_bulk_disable(vpu->variant->num_clocks, vpu->clocks); in hantro_job_finish()
97 hantro_job_finish_no_pm(vpu, ctx, result); in hantro_job_finish()
100 void hantro_irq_done(struct hantro_dev *vpu, in hantro_irq_done() argument
104 v4l2_m2m_get_curr_priv(vpu->m2m_dev); in hantro_irq_done()
111 if (cancel_delayed_work(&vpu->watchdog_work)) { in hantro_irq_done()
114 hantro_job_finish(vpu, ctx, result); in hantro_irq_done()
120 struct hantro_dev *vpu; in hantro_watchdog() local
[all …]
H A Dhantro_postproc.c17 #define HANTRO_PP_REG_WRITE(vpu, reg_name, val) \ argument
19 hantro_reg_write(vpu, \
24 #define HANTRO_PP_REG_WRITE_RELAXED(vpu, reg_name, val) \ argument
26 hantro_reg_write_relaxed(vpu, \
71 struct hantro_dev *vpu = ctx->dev; in hantro_postproc_g1_enable() local
77 HANTRO_PP_REG_WRITE(vpu, pipeline_en, 0x1); in hantro_postproc_g1_enable()
95 HANTRO_PP_REG_WRITE(vpu, clk_gate, 0x1); in hantro_postproc_g1_enable()
96 HANTRO_PP_REG_WRITE(vpu, out_endian, 0x1); in hantro_postproc_g1_enable()
97 HANTRO_PP_REG_WRITE(vpu, out_swap32, 0x1); in hantro_postproc_g1_enable()
98 HANTRO_PP_REG_WRITE(vpu, max_burst, 16); in hantro_postproc_g1_enable()
[all …]
H A Drockchip_vpu2_hw_vp8_dec.c280 struct hantro_dev *vpu = ctx->dev; in cfg_lf() local
285 hantro_reg_write(vpu, &vp8_dec_lf_level[0], lf->level); in cfg_lf()
291 hantro_reg_write(vpu, &vp8_dec_lf_level[i], lf_level); in cfg_lf()
295 hantro_reg_write(vpu, &vp8_dec_lf_level[i], in cfg_lf()
302 vdpu_write_relaxed(vpu, reg, VDPU_REG_FILTER_MB_ADJ); in cfg_lf()
306 hantro_reg_write(vpu, &vp8_dec_mb_adj[i], in cfg_lf()
308 hantro_reg_write(vpu, &vp8_dec_ref_adj[i], in cfg_lf()
319 struct hantro_dev *vpu = ctx->dev; in cfg_qp() local
323 hantro_reg_write(vpu, &vp8_dec_quant[0], q->y_ac_qi); in cfg_qp()
329 hantro_reg_write(vpu, &vp8_dec_quant[i], quant); in cfg_qp()
[all …]
H A Drockchip_vpu2_hw_jpeg_enc.c35 static void rockchip_vpu2_set_src_img_ctrl(struct hantro_dev *vpu, in rockchip_vpu2_set_src_img_ctrl() argument
51 vepu_write_relaxed(vpu, reg, VEPU_REG_INPUT_LUMA_INFO); in rockchip_vpu2_set_src_img_ctrl()
61 vepu_write_relaxed(vpu, reg, VEPU_REG_ENC_OVER_FILL_STRM_OFFSET); in rockchip_vpu2_set_src_img_ctrl()
64 vepu_write_relaxed(vpu, reg, VEPU_REG_ENC_CTRL1); in rockchip_vpu2_set_src_img_ctrl()
67 static void rockchip_vpu2_jpeg_enc_set_buffers(struct hantro_dev *vpu, in rockchip_vpu2_jpeg_enc_set_buffers() argument
82 vepu_write_relaxed(vpu, vb2_dma_contig_plane_dma_addr(dst_buf, 0) + in rockchip_vpu2_jpeg_enc_set_buffers()
85 vepu_write_relaxed(vpu, size_left, VEPU_REG_STR_BUF_LIMIT); in rockchip_vpu2_jpeg_enc_set_buffers()
89 vepu_write_relaxed(vpu, src[0], VEPU_REG_ADDR_IN_PLANE_0); in rockchip_vpu2_jpeg_enc_set_buffers()
93 vepu_write_relaxed(vpu, src[0], VEPU_REG_ADDR_IN_PLANE_0); in rockchip_vpu2_jpeg_enc_set_buffers()
94 vepu_write_relaxed(vpu, src[1], VEPU_REG_ADDR_IN_PLANE_1); in rockchip_vpu2_jpeg_enc_set_buffers()
[all …]
H A Dhantro_g1_vp8_dec.c139 struct hantro_dev *vpu = ctx->dev; in cfg_lf() local
144 hantro_reg_write(vpu, &vp8_dec_lf_level[0], lf->level); in cfg_lf()
150 hantro_reg_write(vpu, &vp8_dec_lf_level[i], lf_level); in cfg_lf()
154 hantro_reg_write(vpu, &vp8_dec_lf_level[i], in cfg_lf()
161 vdpu_write_relaxed(vpu, reg, G1_REG_REF_PIC(0)); in cfg_lf()
165 hantro_reg_write(vpu, &vp8_dec_mb_adj[i], in cfg_lf()
167 hantro_reg_write(vpu, &vp8_dec_ref_adj[i], in cfg_lf()
181 struct hantro_dev *vpu = ctx->dev; in cfg_qp() local
185 hantro_reg_write(vpu, &vp8_dec_quant[0], q->y_ac_qi); in cfg_qp()
191 hantro_reg_write(vpu, &vp8_dec_quant[i], quant); in cfg_qp()
[all …]
H A Dhantro_h1_jpeg_enc.c18 static void hantro_h1_set_src_img_ctrl(struct hantro_dev *vpu, in hantro_h1_set_src_img_ctrl() argument
37 vepu_write_relaxed(vpu, reg, H1_REG_IN_IMG_CTRL); in hantro_h1_set_src_img_ctrl()
40 static void hantro_h1_jpeg_enc_set_buffers(struct hantro_dev *vpu, in hantro_h1_jpeg_enc_set_buffers() argument
55 vepu_write_relaxed(vpu, vb2_dma_contig_plane_dma_addr(dst_buf, 0) + in hantro_h1_jpeg_enc_set_buffers()
58 vepu_write_relaxed(vpu, size_left, H1_REG_STR_BUF_LIMIT); in hantro_h1_jpeg_enc_set_buffers()
63 vepu_write_relaxed(vpu, src[0], H1_REG_ADDR_IN_PLANE_0); in hantro_h1_jpeg_enc_set_buffers()
67 vepu_write_relaxed(vpu, src[0], H1_REG_ADDR_IN_PLANE_0); in hantro_h1_jpeg_enc_set_buffers()
68 vepu_write_relaxed(vpu, src[1], H1_REG_ADDR_IN_PLANE_1); in hantro_h1_jpeg_enc_set_buffers()
73 vepu_write_relaxed(vpu, src[0], H1_REG_ADDR_IN_PLANE_0); in hantro_h1_jpeg_enc_set_buffers()
74 vepu_write_relaxed(vpu, src[1], H1_REG_ADDR_IN_PLANE_1); in hantro_h1_jpeg_enc_set_buffers()
[all …]
H A Dhantro_g2.c16 struct hantro_dev *vpu = ctx->dev; in hantro_g2_active() local
19 status = vdpu_read(vpu, G2_REG_INTERRUPT); in hantro_g2_active()
35 struct hantro_dev *vpu = ctx->dev; in hantro_g2_reset() local
38 status = vdpu_read(vpu, G2_REG_INTERRUPT); in hantro_g2_reset()
40 dev_warn_ratelimited(vpu->dev, "device still running, aborting"); in hantro_g2_reset()
42 vdpu_write(vpu, status, G2_REG_INTERRUPT); in hantro_g2_reset()
52 struct hantro_dev *vpu = dev_id; in hantro_g2_irq() local
55 status = vdpu_read(vpu, G2_REG_INTERRUPT); in hantro_g2_irq()
60 hantro_reg_write(vpu, &g2_dec_irq, 0); in hantro_g2_irq()
61 hantro_reg_write(vpu, &g2_dec_int_stat, 0); in hantro_g2_irq()
[all …]
H A Dhantro_g1_h264_dec.c28 struct hantro_dev *vpu = ctx->dev; in set_params() local
49 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL0); in set_params()
55 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL1); in set_params()
65 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL2); in set_params()
71 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL3); in set_params()
85 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL4); in set_params()
100 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL5); in set_params()
107 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL6); in set_params()
110 vdpu_write_relaxed(vpu, 0, G1_REG_ERR_CONC); in set_params()
113 vdpu_write_relaxed(vpu, in set_params()
[all …]
H A Drockchip_vpu2_hw_mpeg2_dec.c83 rockchip_vpu2_mpeg2_dec_set_quantisation(struct hantro_dev *vpu, in rockchip_vpu2_mpeg2_dec_set_quantisation() argument
90 vdpu_write_relaxed(vpu, ctx->mpeg2_dec.qtable.dma, VDPU_REG_QTABLE_BASE); in rockchip_vpu2_mpeg2_dec_set_quantisation()
94 rockchip_vpu2_mpeg2_dec_set_buffers(struct hantro_dev *vpu, in rockchip_vpu2_mpeg2_dec_set_buffers() argument
114 vdpu_write_relaxed(vpu, addr, VDPU_REG_RLC_VLC_BASE); in rockchip_vpu2_mpeg2_dec_set_buffers()
122 vdpu_write_relaxed(vpu, addr, VDPU_REG_DEC_OUT_BASE); in rockchip_vpu2_mpeg2_dec_set_buffers()
136 vdpu_write_relaxed(vpu, forward_addr, VDPU_REG_REFER0_BASE); in rockchip_vpu2_mpeg2_dec_set_buffers()
137 vdpu_write_relaxed(vpu, forward_addr, VDPU_REG_REFER1_BASE); in rockchip_vpu2_mpeg2_dec_set_buffers()
139 vdpu_write_relaxed(vpu, forward_addr, VDPU_REG_REFER0_BASE); in rockchip_vpu2_mpeg2_dec_set_buffers()
140 vdpu_write_relaxed(vpu, current_addr, VDPU_REG_REFER1_BASE); in rockchip_vpu2_mpeg2_dec_set_buffers()
142 vdpu_write_relaxed(vpu, current_addr, VDPU_REG_REFER0_BASE); in rockchip_vpu2_mpeg2_dec_set_buffers()
[all …]
H A Drockchip_vpu_hw.c371 struct hantro_dev *vpu = dev_id; in rockchip_vpu1_vepu_irq() local
375 status = vepu_read(vpu, H1_REG_INTERRUPT); in rockchip_vpu1_vepu_irq()
379 vepu_write(vpu, 0, H1_REG_INTERRUPT); in rockchip_vpu1_vepu_irq()
380 vepu_write(vpu, 0, H1_REG_AXI_CTRL); in rockchip_vpu1_vepu_irq()
382 hantro_irq_done(vpu, state); in rockchip_vpu1_vepu_irq()
389 struct hantro_dev *vpu = dev_id; in rockchip_vpu2_vdpu_irq() local
393 status = vdpu_read(vpu, VDPU_REG_INTERRUPT); in rockchip_vpu2_vdpu_irq()
397 vdpu_write(vpu, 0, VDPU_REG_INTERRUPT); in rockchip_vpu2_vdpu_irq()
398 vdpu_write(vpu, 0, VDPU_REG_AXI_CTRL); in rockchip_vpu2_vdpu_irq()
400 hantro_irq_done(vpu, state); in rockchip_vpu2_vdpu_irq()
[all …]
H A Drockchip_vpu2_hw_h264_dec.c199 struct hantro_dev *vpu = ctx->dev; in set_params() local
207 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(50)); in set_params()
211 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(51)); in set_params()
216 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(52)); in set_params()
219 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(53)); in set_params()
227 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(54)); in set_params()
233 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(56)); in set_params()
248 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(57)); in set_params()
253 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(59)); in set_params()
256 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(65)); in set_params()
[all …]
H A Dhantro_g1_mpeg2_dec.c81 hantro_g1_mpeg2_dec_set_quantisation(struct hantro_dev *vpu, in hantro_g1_mpeg2_dec_set_quantisation() argument
88 vdpu_write_relaxed(vpu, ctx->mpeg2_dec.qtable.dma, G1_REG_QTABLE_BASE); in hantro_g1_mpeg2_dec_set_quantisation()
92 hantro_g1_mpeg2_dec_set_buffers(struct hantro_dev *vpu, struct hantro_ctx *ctx, in hantro_g1_mpeg2_dec_set_buffers() argument
111 vdpu_write_relaxed(vpu, addr, G1_REG_RLC_VLC_BASE); in hantro_g1_mpeg2_dec_set_buffers()
119 vdpu_write_relaxed(vpu, addr, G1_REG_DEC_OUT_BASE); in hantro_g1_mpeg2_dec_set_buffers()
133 vdpu_write_relaxed(vpu, forward_addr, G1_REG_REFER0_BASE); in hantro_g1_mpeg2_dec_set_buffers()
134 vdpu_write_relaxed(vpu, forward_addr, G1_REG_REFER1_BASE); in hantro_g1_mpeg2_dec_set_buffers()
136 vdpu_write_relaxed(vpu, forward_addr, G1_REG_REFER0_BASE); in hantro_g1_mpeg2_dec_set_buffers()
137 vdpu_write_relaxed(vpu, current_addr, G1_REG_REFER1_BASE); in hantro_g1_mpeg2_dec_set_buffers()
139 vdpu_write_relaxed(vpu, current_addr, G1_REG_REFER0_BASE); in hantro_g1_mpeg2_dec_set_buffers()
[all …]
H A Dimx8m_vpu_hw.c28 static void imx8m_soft_reset(struct hantro_dev *vpu, u32 reset_bits) in imx8m_soft_reset() argument
33 val = readl(vpu->ctrl_base + CTRL_SOFT_RESET); in imx8m_soft_reset()
35 writel(val, vpu->ctrl_base + CTRL_SOFT_RESET); in imx8m_soft_reset()
40 val = readl(vpu->ctrl_base + CTRL_SOFT_RESET); in imx8m_soft_reset()
42 writel(val, vpu->ctrl_base + CTRL_SOFT_RESET); in imx8m_soft_reset()
45 static void imx8m_clk_enable(struct hantro_dev *vpu, u32 clock_bits) in imx8m_clk_enable() argument
49 val = readl(vpu->ctrl_base + CTRL_CLOCK_ENABLE); in imx8m_clk_enable()
51 writel(val, vpu->ctrl_base + CTRL_CLOCK_ENABLE); in imx8m_clk_enable()
54 static int imx8mq_runtime_resume(struct hantro_dev *vpu) in imx8mq_runtime_resume() argument
58 ret = clk_bulk_prepare_enable(vpu->variant->num_clocks, vpu->clocks); in imx8mq_runtime_resume()
[all …]
H A Dhantro_g1.c16 struct hantro_dev *vpu = dev_id; in hantro_g1_irq() local
20 status = vdpu_read(vpu, G1_REG_INTERRUPT); in hantro_g1_irq()
24 vdpu_write(vpu, 0, G1_REG_INTERRUPT); in hantro_g1_irq()
25 vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG); in hantro_g1_irq()
27 hantro_irq_done(vpu, state); in hantro_g1_irq()
34 struct hantro_dev *vpu = ctx->dev; in hantro_g1_reset() local
36 vdpu_write(vpu, G1_REG_INTERRUPT_DEC_IRQ_DIS, G1_REG_INTERRUPT); in hantro_g1_reset()
37 vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG); in hantro_g1_reset()
38 vdpu_write(vpu, 1, G1_REG_SOFT_RESET); in hantro_g1_reset()
H A Dhantro_hevc.c77 struct hantro_dev *vpu = ctx->dev; in tile_buffer_reallocate() local
92 dma_free_coherent(vpu->dev, hevc_dec->tile_filter.size, in tile_buffer_reallocate()
99 dma_free_coherent(vpu->dev, hevc_dec->tile_sao.size, in tile_buffer_reallocate()
106 dma_free_coherent(vpu->dev, hevc_dec->tile_bsd.size, in tile_buffer_reallocate()
113 hevc_dec->tile_filter.cpu = dma_alloc_coherent(vpu->dev, size, in tile_buffer_reallocate()
121 hevc_dec->tile_sao.cpu = dma_alloc_coherent(vpu->dev, size, in tile_buffer_reallocate()
129 hevc_dec->tile_bsd.cpu = dma_alloc_coherent(vpu->dev, size, in tile_buffer_reallocate()
142 dma_free_coherent(vpu->dev, hevc_dec->tile_sao.size, in tile_buffer_reallocate()
149 dma_free_coherent(vpu->dev, hevc_dec->tile_filter.size, in tile_buffer_reallocate()
217 struct hantro_dev *vpu = ctx->dev; in hantro_hevc_dec_exit() local
[all …]
H A DMakefile3 obj-$(CONFIG_VIDEO_HANTRO) += hantro-vpu.o
5 hantro-vpu-y += \
24 hantro-vpu-$(CONFIG_VIDEO_HANTRO_IMX8M) += \
27 hantro-vpu-$(CONFIG_VIDEO_HANTRO_SAMA5D4) += \
30 hantro-vpu-$(CONFIG_VIDEO_HANTRO_ROCKCHIP) += \
40 hantro-vpu-$(CONFIG_VIDEO_HANTRO_SUNXI) += \
43 hantro-vpu-$(CONFIG_VIDEO_HANTRO_STM32MP25) += \
/linux/drivers/media/platform/mediatek/mdp/
H A Dmtk_mdp_vpu.c13 static inline struct mtk_mdp_ctx *vpu_to_ctx(struct mtk_mdp_vpu *vpu) in vpu_to_ctx() argument
15 return container_of(vpu, struct mtk_mdp_ctx, vpu); in vpu_to_ctx()
20 struct mtk_mdp_vpu *vpu = (struct mtk_mdp_vpu *) in mtk_mdp_vpu_handle_init_ack() local
24 vpu->vsi = (struct mdp_process_vsi *) in mtk_mdp_vpu_handle_init_ack()
25 vpu_mapping_dm_addr(vpu->pdev, msg->vpu_inst_addr); in mtk_mdp_vpu_handle_init_ack()
26 vpu->inst_addr = msg->vpu_inst_addr; in mtk_mdp_vpu_handle_init_ack()
34 struct mtk_mdp_vpu *vpu = (struct mtk_mdp_vpu *) in mtk_mdp_vpu_ipi_handler() local
38 vpu->failure = msg->status; in mtk_mdp_vpu_ipi_handler()
39 if (!vpu->failure) { in mtk_mdp_vpu_ipi_handler()
48 ctx = vpu_to_ctx(vpu); in mtk_mdp_vpu_ipi_handler()
[all …]
/linux/drivers/media/platform/mediatek/vcodec/decoder/
H A Dvdec_vpu_if.h53 int vpu_dec_init(struct vdec_vpu_inst *vpu);
63 int vpu_dec_start(struct vdec_vpu_inst *vpu, uint32_t *data, unsigned int len);
73 int vpu_dec_end(struct vdec_vpu_inst *vpu);
80 int vpu_dec_deinit(struct vdec_vpu_inst *vpu);
88 int vpu_dec_reset(struct vdec_vpu_inst *vpu);
96 int vpu_dec_core(struct vdec_vpu_inst *vpu);
106 int vpu_dec_core_end(struct vdec_vpu_inst *vpu);
116 int vpu_dec_get_param(struct vdec_vpu_inst *vpu, uint32_t *data,
/linux/drivers/media/platform/mediatek/vcodec/decoder/vdec/
H A Dvdec_vp8_req_if.c103 struct vdec_vpu_inst vpu; member
125 vpu_dec_get_param(&inst->vpu, data, 3, GET_PARAM_PIC_INFO); in vdec_vp8_slice_get_pic_info()
129 ctx->picinfo.fb_sz[0] = inst->vpu.fb_sz[0]; in vdec_vp8_slice_get_pic_info()
130 ctx->picinfo.fb_sz[1] = inst->vpu.fb_sz[1]; in vdec_vp8_slice_get_pic_info()
284 inst->vpu.id = SCP_IPI_VDEC_LAT; in vdec_vp8_slice_init()
285 inst->vpu.core_id = SCP_IPI_VDEC_CORE; in vdec_vp8_slice_init()
286 inst->vpu.ctx = ctx; in vdec_vp8_slice_init()
287 inst->vpu.codec_type = ctx->current_codec; in vdec_vp8_slice_init()
288 inst->vpu.capture_type = ctx->capture_fourcc; in vdec_vp8_slice_init()
290 err = vpu_dec_init(&inst->vpu); in vdec_vp8_slice_init()
[all …]

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