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Searched refs:vlv_dpio_write (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/gpu/drm/i915/display/
H A Dintel_dpio_phy.c734 vlv_dpio_write(display->drm, phy, VLV_PCS01_DW10(ch), val); in chv_set_phy_signal_level()
741 vlv_dpio_write(display->drm, phy, VLV_PCS23_DW10(ch), val); in chv_set_phy_signal_level()
747 vlv_dpio_write(display->drm, phy, VLV_PCS01_DW9(ch), val); in chv_set_phy_signal_level()
753 vlv_dpio_write(display->drm, phy, VLV_PCS23_DW9(ch), val); in chv_set_phy_signal_level()
761 vlv_dpio_write(display->drm, phy, CHV_TX_DW4(ch, i), val); in chv_set_phy_signal_level()
779 vlv_dpio_write(display->drm, phy, CHV_TX_DW2(ch, i), val); in chv_set_phy_signal_level()
794 vlv_dpio_write(display->drm, phy, CHV_TX_DW3(ch, i), val); in chv_set_phy_signal_level()
800 vlv_dpio_write(display->drm, phy, VLV_PCS01_DW10(ch), val); in chv_set_phy_signal_level()
805 vlv_dpio_write(display->drm, phy, VLV_PCS23_DW10(ch), val); in chv_set_phy_signal_level()
826 vlv_dpio_write(display->drm, phy, VLV_PCS01_DW0(ch), val); in __chv_data_lane_soft_reset()
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H A Dvlv_sideband.h83 void vlv_dpio_write(struct drm_device *drm,
90 static inline void vlv_dpio_write(struct drm_device *drm, in vlv_dpio_write() function
H A Dvlv_sideband.c43 void vlv_dpio_write(struct drm_device *drm, in vlv_dpio_write() function
H A Dintel_display_power_well.c1496 vlv_dpio_write(display->drm, phy, CHV_CMN_DW28, tmp); in chv_dpio_cmn_power_well_enable()
1501 vlv_dpio_write(display->drm, phy, CHV_CMN_DW6_CH1, tmp); in chv_dpio_cmn_power_well_enable()
1510 vlv_dpio_write(display->drm, phy, CHV_CMN_DW30, tmp); in chv_dpio_cmn_power_well_enable()