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Searched refs:vlv_dpio_read (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/gpu/drm/i915/display/
H A Dintel_dpio_phy.c730 val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW10(ch)); in chv_set_phy_signal_level()
737 val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW10(ch)); in chv_set_phy_signal_level()
744 val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW9(ch)); in chv_set_phy_signal_level()
750 val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW9(ch)); in chv_set_phy_signal_level()
758 val = vlv_dpio_read(display->drm, phy, CHV_TX_DW4(ch, i)); in chv_set_phy_signal_level()
766 val = vlv_dpio_read(display->drm, phy, CHV_TX_DW2(ch, i)); in chv_set_phy_signal_level()
789 val = vlv_dpio_read(display->drm, phy, CHV_TX_DW3(ch, i)); in chv_set_phy_signal_level()
798 val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW10(ch)); in chv_set_phy_signal_level()
803 val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW10(ch)); in chv_set_phy_signal_level()
821 val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW0(ch)); in __chv_data_lane_soft_reset()
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H A Dvlv_sideband.h82 u32 vlv_dpio_read(struct drm_device *drm, enum dpio_phy phy, int reg);
86 static inline u32 vlv_dpio_read(struct drm_device *drm, int phy, int reg) in vlv_dpio_read() function
H A Dvlv_sideband.c24 u32 vlv_dpio_read(struct drm_device *drm, enum dpio_phy phy, int reg) in vlv_dpio_read() function
H A Dintel_display_power_well.c1493 tmp = vlv_dpio_read(display->drm, phy, CHV_CMN_DW28); in chv_dpio_cmn_power_well_enable()
1499 tmp = vlv_dpio_read(display->drm, phy, CHV_CMN_DW6_CH1); in chv_dpio_cmn_power_well_enable()
1508 tmp = vlv_dpio_read(display->drm, phy, CHV_CMN_DW30); in chv_dpio_cmn_power_well_enable()
1582 val = vlv_dpio_read(display->drm, phy, reg); in assert_chv_phy_powergate()