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Searched refs:vlv_cck_read (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/gpu/drm/i915/display/
H A Dvlv_clock.c27 hpll_freq = vlv_cck_read(drm, CCK_FUSE_REG) & in vlv_clock_get_hpll_vco()
46 val = vlv_cck_read(drm, reg); in vlv_clock_get_cck()
H A Dvlv_dsi_pll.c236 ret = poll_timeout_us(val = vlv_cck_read(display->drm, CCK_REG_DSI_PLL_CONTROL), in vlv_dsi_pll_enable()
258 tmp = vlv_cck_read(display->drm, CCK_REG_DSI_PLL_CONTROL); in vlv_dsi_pll_disable()
337 pll_ctl = vlv_cck_read(display->drm, CCK_REG_DSI_PLL_CONTROL); in vlv_dsi_get_pclk()
338 pll_div = vlv_cck_read(display->drm, CCK_REG_DSI_PLL_DIVIDER); in vlv_dsi_get_pclk()
607 cur_state = vlv_cck_read(display->drm, CCK_REG_DSI_PLL_CONTROL) & DSI_PLL_VCO_EN; in assert_dsi_pll()
H A Dvlv_sideband.h41 static inline u32 vlv_cck_read(struct drm_device *drm, u32 reg) in vlv_cck_read() function
H A Dintel_cdclk.c717 val = vlv_cck_read(display->drm, CCK_DISPLAY_CLOCK_CONTROL); in vlv_set_cdclk()
722 ret = poll_timeout_us(val = vlv_cck_read(display->drm, CCK_DISPLAY_CLOCK_CONTROL), in vlv_set_cdclk()