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Searched refs:v_taps (Results 1 – 25 of 25) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_transform.c122 if (data->taps.h_taps + data->taps.v_taps <= 2) { in setup_scaling_configuration()
133 SCL_V_NUM_OF_TAPS, data->taps.v_taps - 1); in setup_scaling_configuration()
156 if (data->taps.h_taps + data->taps.v_taps <= 2) { in dce60_setup_scaling_configuration()
169 SCL_V_NUM_OF_TAPS, data->taps.v_taps - 1); in dce60_setup_scaling_configuration()
306 dc_fixpt_from_int(data->taps.v_taps + 1)), in calculate_inits()
335 dc_fixpt_from_int(data->taps.v_taps + 1)), in dce60_calculate_inits()
442 coeffs_v = get_filter_coeffs_16p(data->taps.v_taps, data->ratios.vert); in dce_transform_set_scaler()
452 data->taps.v_taps, in dce_transform_set_scaler()
457 data->taps.v_taps, in dce_transform_set_scaler()
529 coeffs_v = get_filter_coeffs_16p(data->taps.v_taps, data->ratios.vert); in dce60_transform_set_scaler()
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/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn201/
H A Ddcn201_dpp.c226 if (in_taps->v_taps == 0) { in dpp201_get_optimal_number_of_taps()
228 scl_data->taps.v_taps = 8; in dpp201_get_optimal_number_of_taps()
230 scl_data->taps.v_taps = 4; in dpp201_get_optimal_number_of_taps()
232 scl_data->taps.v_taps = in_taps->v_taps; in dpp201_get_optimal_number_of_taps()
255 scl_data->taps.v_taps = 1; in dpp201_get_optimal_number_of_taps()
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn10/
H A Ddcn10_dpp_dscl.c298 v_2tap_hardcode_coef_en = scl_data->taps.v_taps < 3 in dpp1_dscl_set_scl_filter()
300 && (scl_data->taps.v_taps > 1 && scl_data->taps.v_taps_c > 1); in dpp1_dscl_set_scl_filter()
319 scl_data->taps.v_taps, scl_data->ratios.vert); in dpp1_dscl_set_scl_filter()
344 dpp, scl_data->taps.v_taps, in dpp1_dscl_set_scl_filter()
463 int vtaps = scl_data->taps.v_taps; in dpp1_dscl_find_lb_memory_config()
689 SCL_V_NUM_TAPS, scl_data->taps.v_taps - 1, in dpp1_dscl_set_scaler_manual_scale()
H A Ddcn10_dpp.c158 if (in_taps->v_taps == 0) in dpp1_get_optimal_number_of_taps()
159 scl_data->taps.v_taps = 4; in dpp1_get_optimal_number_of_taps()
161 scl_data->taps.v_taps = in_taps->v_taps; in dpp1_get_optimal_number_of_taps()
178 scl_data->taps.v_taps = 1; in dpp1_get_optimal_number_of_taps()
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_spl_translate.c39 spl_scaling_quality->v_taps = scaling_quality->v_taps; in populate_spltaps_from_taps()
48 scaling_quality->v_taps = spl_scaling_quality->v_taps + 1; in populate_taps_from_spltaps()
H A Ddc_hw_types.h718 uint32_t v_taps; member
H A Ddc.h2996 uint32_t v_taps; /* SCL_TAP_CONTROL->SCL_V_NUM_TAPS from taps.v_taps */ member
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/
H A Ddml21_translation_helper.c421 plane->composition.scaler_info.plane0.v_taps = 1; in populate_dml21_dummy_plane_cfg()
423 plane->composition.scaler_info.plane1.v_taps = 0; in populate_dml21_dummy_plane_cfg()
561 if ((scaler_data->taps.h_taps > 1) || (scaler_data->taps.v_taps > 1) || in populate_dml21_plane_config_from_plane_state()
591 if (!scaler_data->taps.v_taps) { in populate_dml21_plane_config_from_plane_state()
592 plane->composition.scaler_info.plane0.v_taps = 1; in populate_dml21_plane_config_from_plane_state()
593 plane->composition.scaler_info.plane1.v_taps = 1; in populate_dml21_plane_config_from_plane_state()
595 plane->composition.scaler_info.plane0.v_taps = scaler_data->taps.v_taps; in populate_dml21_plane_config_from_plane_state()
596 plane->composition.scaler_info.plane1.v_taps = scaler_data->taps.v_taps_c; in populate_dml21_plane_config_from_plane_state()
/linux/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_transform_v.c167 set_reg_field_value(value, data->taps.v_taps - 1, in setup_scaling_configuration()
176 if (data->taps.h_taps + data->taps.v_taps > 2) { in setup_scaling_configuration()
559 coeffs_v = get_filter_coeffs_64p(data->taps.v_taps, data->ratios.vert); in dce110_xfmv_set_scaler()
571 data->taps.v_taps, in dce110_xfmv_set_scaler()
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn30/
H A Ddcn30_dpp.c460 if (in_taps->v_taps == 0) { in dpp3_get_optimal_number_of_taps()
462 scl_data->taps.v_taps = min(dc_fixpt_ceil(dc_fixpt_mul_int(scl_data->ratios.vert, 2)), 8); in dpp3_get_optimal_number_of_taps()
464 scl_data->taps.v_taps = 4; in dpp3_get_optimal_number_of_taps()
466 scl_data->taps.v_taps = in_taps->v_taps; in dpp3_get_optimal_number_of_taps()
520 if (scl_data->taps.v_taps > max_taps_y) in dpp3_get_optimal_number_of_taps()
521 scl_data->taps.v_taps = max_taps_y; in dpp3_get_optimal_number_of_taps()
530 scl_data->taps.v_taps = 1; in dpp3_get_optimal_number_of_taps()
/linux/drivers/gpu/drm/amd/display/dc/sspl/
H A Ddc_spl_isharp_filters.c553 SPL_NAMESPACE(spl_dscl_get_blur_scale_coeffs_64p(data->taps.v_taps)); in SPL_NAMESPACE()
H A Ddc_spl_types.h38 uint32_t v_taps; member
/linux/drivers/gpu/drm/amd/display/dc/basics/
H A Ddce_calcs.c382 data->v_taps[maximum_number_of_surfaces - 2] = bw_int_to_fixed(1); in calculate_bandwidth()
383 data->v_taps[maximum_number_of_surfaces - 1] = bw_int_to_fixed(1); in calculate_bandwidth()
435 data->v_taps[i] = bw_int_to_fixed(1); in calculate_bandwidth()
544 if (bw_mtn(data->vsr[i], data->v_taps[i])) { in calculate_bandwidth()
580 if (bw_mtn(bw_add(data->v_taps[i], bw_int_to_fixed(1)), data->lb_partitions[i])) { in calculate_bandwidth()
803 …data->v_filter_init[i] = bw_floor2(bw_div((bw_add(bw_add(bw_add(bw_int_to_fixed(1), data->v_taps[i… in calculate_bandwidth()
819 …e[i] == bw_def_graphics) && (bw_mtn(data->lb_partitions[i], bw_add(data->v_taps[i], bw_ceil2(data-… in calculate_bandwidth()
1253 …data->scaler_limits_factor = bw_max2(bw_div(data->v_taps[i], data->v_scaler_efficiency), bw_div(da… in calculate_bandwidth()
1256 …ixed(4)), bw_int_to_fixed(1)), bw_mul(data->hsr[i], bw_max2(bw_div(data->v_taps[i], data->v_scaler… in calculate_bandwidth()
1311 …xed(1)) || (bw_leq(data->vsr[i], bw_frc_to_fixed(8, 10)) && bw_leq(data->v_taps[i], bw_int_to_fixe… in calculate_bandwidth()
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H A Dcalcs_logger.h431 DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] v_taps[%d]:%d", i, bw_fixed_to_int(data->v_taps[i])); in print_bw_calcs_data()
/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_debug.c167 update->scaling_info->scaling_quality.v_taps, in update_surface_trace()
H A Ddc_resource.c1364 data->taps.v_taps, in calculate_inits_and_viewports()
1621 if (res && (pipe_ctx->plane_res.scl_data.taps.v_taps != temp.v_taps || in resource_build_scaling_params()
H A Ddc.c6798 …state->dpp[i].v_taps = dscl_data->taps.v_taps + 1; // dscl_prog_data.taps stores (taps - 1), so ad… in dc_capture_register_software_state()
/linux/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dwb_scl.c807 uint32_t v_taps_luma = num_taps.v_taps; in dwb_program_vert_scalar()
/linux/drivers/gpu/drm/amd/display/dc/inc/
H A Ddce_calcs.h397 struct bw_fixed v_taps[maximum_number_of_surfaces]; member
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/
H A Ddml2_translation_helper.c1115 if (!scaler_data->taps.v_taps) { in populate_dml_plane_cfg_from_plane_state()
1119 out->VTaps[location] = scaler_data->taps.v_taps; in populate_dml_plane_cfg_from_plane_state()
1252 out->WritebackVTaps[location] = wb_info->dwb_params.scaler_taps.v_taps > 0 ? in populate_dml_writeback_cfg_from_stream_state()
1253 wb_info->dwb_params.scaler_taps.v_taps : 1; in populate_dml_writeback_cfg_from_stream_state()
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/
H A Ddml2_core_dcn4_calcs.c6788 double v_taps = p->display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_taps; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport() local
6789 double v_taps_c = p->display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_taps; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
6794 …rSize / LBBitPerPixel / ((double)p->SwathWidthY[k] / math_max2(h_ratio, 1.0)), 1)) - (v_taps - 1)); in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
6802 DML_LOG_VERBOSE("DML::%s: k=%u, VTaps = %f\n", __func__, k, v_taps); in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
7443 myPipe->VTaps = display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_taps; in dml_core_ms_prefetch_check()
7444 myPipe->VTapsChroma = display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_taps; in dml_core_ms_prefetch_check()
8035 || display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_taps != 1.0)) { in dml_core_mode_support()
8037 …].composition.scaler_info.plane0.v_taps < 1.0 || display_cfg->plane_descriptors[k].composition.sca… in dml_core_mode_support()
8043 …caler_info.plane0.v_ratio > display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_taps in dml_core_mode_support()
8045 …k].composition.scaler_info.plane1.v_taps < 1 || display_cfg->plane_descriptors[k].composition.scal… in dml_core_mode_support()
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/linux/drivers/gpu/drm/amd/display/dc/dml/calcs/
H A Ddcn_calcs.c404 input->scale_taps.vtaps = pipe->plane_res.scl_data.taps.v_taps; in pipe_ctx_to_e2e_pipe_params()
1013 v->override_vta_ps[input_idx] = pipe->plane_res.scl_data.taps.v_taps; in dcn_validate_bandwidth()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddcn30_fpu.c220 dout_wb.wb_vtaps_luma = wb_info->dwb_params.scaler_taps.v_taps; in dcn30_fpu_populate_dml_writeback_from_context()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.c1682 pipes[pipe_cnt].pipe.scale_taps.vtaps = scl->taps.v_taps; in dcn20_populate_dml_pipes_from_context()
2511 dout_wb.wb_vtaps_luma = wb_info->dwb_params.scaler_taps.v_taps; in dcn201_populate_dml_writeback_from_context_fpu()
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm.c10681 wb_info->dwb_params.scaler_taps.v_taps = 1; in dm_set_writeback()