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Searched refs:ufshcd_writel (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/ufs/core/
H A Dufshcd-crypto.c29 ufshcd_writel(hba, 0, slot_offset + 16 * sizeof(cfg->reg_val[0])); in ufshcd_program_key()
31 ufshcd_writel(hba, le32_to_cpu(cfg->reg_val[i]), in ufshcd_program_key()
35 ufshcd_writel(hba, le32_to_cpu(cfg->reg_val[17]), in ufshcd_program_key()
38 ufshcd_writel(hba, le32_to_cpu(cfg->reg_val[16]), in ufshcd_program_key()
H A Dufs-mcq.c102 ufshcd_writel(hba, val, REG_UFS_MCQ_CFG); in ufshcd_mcq_config_mac()
440 ufshcd_writel(hba, msg->address_lo, REG_UFS_ESILBA); in ufshcd_mcq_config_esi()
441 ufshcd_writel(hba, msg->address_hi, REG_UFS_ESIUBA); in ufshcd_mcq_config_esi()
H A Dufshcd.c380 ufshcd_writel(hba, new_val, REG_INTERRUPT_ENABLE); in ufshcd_enable_intr()
394 ufshcd_writel(hba, new_val, REG_INTERRUPT_ENABLE); in ufshcd_disable_intr()
889 ufshcd_writel(hba, ~mask, REG_UTP_TRANSFER_REQ_LIST_CLEAR); in ufshcd_utrl_clear()
900 ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR); in ufshcd_utmrl_clear()
902 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR); in ufshcd_utmrl_clear()
976 ufshcd_writel(hba, INT_AGGR_ENABLE | in ufshcd_reset_intr_aggr()
990 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE | in ufshcd_config_intr_aggr()
1002 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); in ufshcd_disable_intr_aggr()
1013 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT, in ufshcd_enable_run_stop_reg()
1015 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT, in ufshcd_enable_run_stop_reg()
[all …]
/linux/drivers/ufs/host/
H A Dufs-mediatek.c268 ufshcd_writel(hba, 0, in ufs_mtk_hce_enable_notify()
278 ufshcd_writel(hba, in ufs_mtk_hce_enable_notify()
353 ufshcd_writel(hba, REFCLK_REQUEST, REG_UFS_REFCLK_CTRL); in ufs_mtk_setup_ref_clk()
356 ufshcd_writel(hba, REFCLK_RELEASE, REG_UFS_REFCLK_CTRL); in ufs_mtk_setup_ref_clk()
417 ufshcd_writel(hba, 0x820820, REG_UFS_DEBUG_SEL); in ufs_mtk_dbg_sel()
418 ufshcd_writel(hba, 0x0, REG_UFS_DEBUG_SEL_B0); in ufs_mtk_dbg_sel()
419 ufshcd_writel(hba, 0x55555555, REG_UFS_DEBUG_SEL_B1); in ufs_mtk_dbg_sel()
420 ufshcd_writel(hba, 0xaaaaaaaa, REG_UFS_DEBUG_SEL_B2); in ufs_mtk_dbg_sel()
421 ufshcd_writel(hba, 0xffffffff, REG_UFS_DEBUG_SEL_B3); in ufs_mtk_dbg_sel()
423 ufshcd_writel(hba, 0x20, REG_UFS_DEBUG_SEL); in ufs_mtk_dbg_sel()
[all …]
H A Dufs-sprd.c59 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE); in ufs_sprd_ctrl_uic_compl()
188 ufshcd_writel(hba, 0, REG_AUTO_HIBERNATE_IDLE_TIMER); in ufs_sprd_suspend()
232 ufshcd_writel(hba, val, REG_CONTROLLER_ENABLE); in ufs_sprd_n6_key_acc_enable()
H A Dcdns-pltfrm.c134 ufshcd_writel(hba, core_clk_div, CDNS_UFS_REG_HCLKDIV); in cdns_ufs_set_hclkdiv()
242 ufshcd_writel(hba, data, CDNS_UFS_REG_PHY_XCFGD1); in cdns_ufs_m31_16nm_phy_initialization()
H A Dufshcd-dwc.c44 ufshcd_writel(hba, divider_val, DWC_UFS_REG_HCLKDIV); in ufshcd_dwc_program_clk_div()
H A Dufs-hisi.c232 ufshcd_writel(hba, UFS_HCLKDIV_NORMAL_VALUE, UFS_REG_HCLKDIV); in ufs_hisi_link_startup_pre_change()
237 ufshcd_writel(hba, reg, REG_AUTO_HIBERNATE_IDLE_TIMER); in ufs_hisi_link_startup_pre_change()
H A Dufs-qcom.c156 ufshcd_writel(hba, ICE_ALLOCATOR_TYPE, REG_UFS_MEM_ICE_CONFIG); in ufs_qcom_config_ice_allocator()
157 ufshcd_writel(hba, config, REG_UFS_MEM_ICE_NUM_CORE); in ufs_qcom_config_ice_allocator()
697 ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US); in ufs_qcom_cfg_timers()
798 ufshcd_writel(hba, UFS_ICE_SYNC_RST_SEL | UFS_ICE_SYNC_RST_SW, UFS_MEM_ICE_CFG); in ufs_qcom_resume()
807 ufshcd_writel(hba, reg_val, UFS_MEM_ICE_CFG); in ufs_qcom_resume()
1970 ufshcd_writel(hba, reg, REG_UFS_CFG1); in ufs_qcom_dump_dbg_regs()
H A Dufs-amd-versal2.c388 ufshcd_writel(hba, host->host_clk / 1000000, DWC_UFS_REG_HCLKDIV); in ufs_versal2_link_startup_notify()
H A Dufs-renesas.c62 ufshcd_writel(hba, value, reg); in ufs_renesas_write()
H A Dufshcd-pci.c105 ufshcd_writel(hba, hce, REG_CONTROLLER_ENABLE); in ufs_intel_hce_enable_notify()
H A Dufs-exynos.c337 ufshcd_writel(hba, MH_MSG(enabled_vh, MH_MSG_PH_READY), PH2VH_MBOX); in exynosauto_ufs_post_pwr_change()
/linux/include/ufs/
H A Dufshcd.h1275 #define ufshcd_writel(hba, val, reg) \ macro
1294 ufshcd_writel(hba, tmp, reg); in ufshcd_rmwl()