Searched refs:ubwc_config (Results 1 – 6 of 6) sorted by relevance
139 payload = core->iris_platform_data->ubwc_config->max_channels; in iris_hfi_gen2_packet_sys_init()149 payload = core->iris_platform_data->ubwc_config->mal_length; in iris_hfi_gen2_packet_sys_init()159 payload = core->iris_platform_data->ubwc_config->highest_bank_bit; in iris_hfi_gen2_packet_sys_init()169 payload = core->iris_platform_data->ubwc_config->bank_swzl_level; in iris_hfi_gen2_packet_sys_init()179 payload = core->iris_platform_data->ubwc_config->bank_swz2_level; in iris_hfi_gen2_packet_sys_init()189 payload = core->iris_platform_data->ubwc_config->bank_swz3_level; in iris_hfi_gen2_packet_sys_init()199 payload = core->iris_platform_data->ubwc_config->bank_spreading; in iris_hfi_gen2_packet_sys_init()
42 obj-$(CONFIG_QCOM_UBWC_CONFIG) += ubwc_config.o
838 BUG_ON(adreno_gpu->ubwc_config->highest_bank_bit < 13); in a5xx_hw_init()839 hbb = adreno_gpu->ubwc_config->highest_bank_bit - 13; in a5xx_hw_init()1774 adreno_gpu->ubwc_config = &adreno_gpu->_ubwc_config; in a5xx_gpu_init()
244 const struct qcom_ubwc_cfg_data *ubwc_config; member
267 const struct qcom_ubwc_cfg_data *cfg = adreno_gpu->ubwc_config; in a8xx_set_ubwc_config()
803 gpu->ubwc_config = &gpu->_ubwc_config; in a6xx_calc_ubwc_config()811 const struct qcom_ubwc_cfg_data *cfg = adreno_gpu->ubwc_config; in a6xx_set_ubwc_config()