| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn20/ |
| H A D | dcn20_dccg.h | 122 #define DCCG_REG_FIELD_LIST(type) \ argument
123 type DPPCLK0_DTO_PHASE;\
124 type DPPCLK0_DTO_MODULO;\
125 type DPPCLK_DTO_ENABLE[6];\
126 type DPPCLK_DTO_DB_EN[6];\
127 type REFCLK_CLOCK_EN;\
128 type REFCLK_SRC_SEL;\
129 type DISPCLK_STEP_DELAY;\
130 type DISPCLK_STEP_SIZE;\
131 type DISPCLK_FREQ_RAMP_DONE;\
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| /linux/drivers/net/ethernet/microchip/vcap/ |
| H A D | vcap_model_kunit.c | 19 .type = VCAP_FIELD_U32,
24 .type = VCAP_FIELD_BIT,
29 .type = VCAP_FIELD_U32,
34 .type = VCAP_FIELD_U32,
39 .type = VCAP_FIELD_U32,
44 .type = VCAP_FIELD_U32,
49 .type = VCAP_FIELD_BIT,
54 .type = VCAP_FIELD_U32,
59 .type = VCAP_FIELD_U32,
64 .type = VCAP_FIELD_U32,
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| /linux/drivers/net/ethernet/microchip/sparx5/ |
| H A D | sparx5_vcap_ag_api.c | 19 .type = VCAP_FIELD_BIT,
24 .type = VCAP_FIELD_BIT,
29 .type = VCAP_FIELD_U32,
34 .type = VCAP_FIELD_U32,
39 .type = VCAP_FIELD_U32,
44 .type = VCAP_FIELD_U72,
49 .type = VCAP_FIELD_BIT,
54 .type = VCAP_FIELD_BIT,
59 .type = VCAP_FIELD_U32,
64 .type = VCAP_FIELD_U32,
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| /linux/drivers/net/ethernet/microchip/sparx5/lan969x/ |
| H A D | lan969x_vcap_ag_api.c | 18 .type = VCAP_FIELD_BIT,
23 .type = VCAP_FIELD_BIT,
28 .type = VCAP_FIELD_U32,
33 .type = VCAP_FIELD_U32,
38 .type = VCAP_FIELD_U32,
43 .type = VCAP_FIELD_U72,
48 .type = VCAP_FIELD_BIT,
53 .type = VCAP_FIELD_BIT,
58 .type = VCAP_FIELD_U32,
63 .type = VCAP_FIELD_U32,
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| /linux/drivers/net/ethernet/microchip/lan966x/ |
| H A D | lan966x_vcap_ag_api.c | 11 .type = VCAP_FIELD_BIT,
16 .type = VCAP_FIELD_U32,
21 .type = VCAP_FIELD_U32,
26 .type = VCAP_FIELD_BIT,
31 .type = VCAP_FIELD_BIT,
36 .type = VCAP_FIELD_BIT,
41 .type = VCAP_FIELD_BIT,
46 .type = VCAP_FIELD_BIT,
51 .type = VCAP_FIELD_BIT,
56 .type = VCAP_FIELD_BIT,
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| /linux/drivers/gpu/drm/amd/display/dc/optc/dcn10/ |
| H A D | dcn10_optc.h | 415 #define TG_REG_FIELD_LIST_DCN1_0(type) \ argument
416 type VSTARTUP_START;\
417 type VUPDATE_OFFSET;\
418 type VUPDATE_WIDTH;\
419 type VREADY_OFFSET;\
420 type OTG_BLANK_DATA_EN;\
421 type OTG_BLANK_DE_MODE;\
422 type OTG_CURRENT_BLANK_STATE;\
423 type OTG_MASTER_UPDATE_LOCK;\
424 type UPDATE_LOCK_STATUS;\
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| /linux/drivers/gpu/drm/amd/display/dc/dio/dcn10/ |
| H A D | dcn10_stream_encoder.h | 355 #define SE_REG_FIELD_LIST_DCN1_0(type) \ argument
356 type AFMT_GENERIC_INDEX;\
357 type AFMT_GENERIC_HB0;\
358 type AFMT_GENERIC_HB1;\
359 type AFMT_GENERIC_HB2;\
360 type AFMT_GENERIC_HB3;\
361 type AFMT_GENERIC_LOCK_STATUS;\
362 type AFMT_GENERIC_CONFLICT;\
363 type AFMT_GENERIC_CONFLICT_CLR;\
364 type AFMT_GENERIC0_FRAME_UPDATE_PENDING;\
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| /linux/drivers/gpu/drm/amd/display/dc/dwb/dcn30/ |
| H A D | dcn30_dwb.h | 409 #define DWBC_REG_FIELD_LIST_DCN3_0(type) \ argument
410 type DWB_ENABLE;\
411 type DISPCLK_R_DWB_GATE_DIS;\
412 type DISPCLK_G_DWB_GATE_DIS;\
413 type DWB_TEST_CLK_SEL;\
414 type DWBSCL_LUT_MEM_PWR_FORCE;\
415 type DWBSCL_LUT_MEM_PWR_DIS;\
416 type DWBSCL_LUT_MEM_PWR_STATE;\
417 type DWBSCL_LB_MEM_PWR_FORCE;\
418 type DWBSCL_LB_MEM_PWR_DIS;\
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| /linux/net/ieee802154/ |
| H A D | nl_policy.c | 15 [IEEE802154_ATTR_DEV_NAME] = { .type = NLA_STRING, },
16 [IEEE802154_ATTR_DEV_INDEX] = { .type = NLA_U32, },
17 [IEEE802154_ATTR_PHY_NAME] = { .type = NLA_STRING, },
19 [IEEE802154_ATTR_STATUS] = { .type = NLA_U8, },
20 [IEEE802154_ATTR_SHORT_ADDR] = { .type = NLA_U16, },
21 [IEEE802154_ATTR_HW_ADDR] = { .type = NLA_HW_ADDR, },
22 [IEEE802154_ATTR_PAN_ID] = { .type = NLA_U16, },
23 [IEEE802154_ATTR_CHANNEL] = { .type = NLA_U8, },
24 [IEEE802154_ATTR_BCN_ORD] = { .type = NLA_U8, },
25 [IEEE802154_ATTR_SF_ORD] = { .type = NLA_U8, },
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| /linux/drivers/gpu/drm/amd/display/dc/dsc/dcn20/ |
| H A D | dcn20_dsc.h | 269 #define DSC_FIELD_LIST_DCN20(type)\ argument
270 type DSC_CLOCK_EN; \
271 type DSC_DISPCLK_R_GATE_DIS; \
272 type DSC_DSCCLK_R_GATE_DIS; \
273 type DSC_DBG_EN; \
274 type DSC_TEST_CLOCK_MUX_SEL; \
275 type ICH_RESET_AT_END_OF_LINE; \
276 type NUMBER_OF_SLICES_PER_LINE; \
277 type ALTERNATE_ICH_ENCODING_EN; \
278 type NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION; \
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| /linux/net/devlink/ |
| H A D | netlink_gen.c | 43 [DEVLINK_PORT_FUNCTION_ATTR_HW_ADDR] = { .type = NLA_BINARY, },
51 [DEVLINK_RATE_TC_ATTR_BW] = { .type = NLA_U32, },
55 [DEVLINK_ATTR_SELFTEST_ID_FLASH] = { .type = NLA_FLAG, },
60 [DEVLINK_ATTR_BUS_NAME] = { .type = NLA_NUL_STRING, },
61 [DEVLINK_ATTR_DEV_NAME] = { .type = NLA_NUL_STRING, },
66 [DEVLINK_ATTR_BUS_NAME] = { .type = NLA_NUL_STRING, },
67 [DEVLINK_ATTR_DEV_NAME] = { .type = NLA_NUL_STRING, },
68 [DEVLINK_ATTR_PORT_INDEX] = { .type = NLA_U32, },
73 [DEVLINK_ATTR_BUS_NAME] = { .type = NLA_NUL_STRING, },
74 [DEVLINK_ATTR_DEV_NAME] = { .type = NLA_NUL_STRING, },
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| /linux/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/ |
| H A D | dcn20_mmhubbub.h | 252 #define MCIF_WB_REG_FIELD_LIST_DCN2_0(type) \ argument
253 type MCIF_WB_BUFMGR_ENABLE;\
254 type MCIF_WB_BUFMGR_SW_INT_EN;\
255 type MCIF_WB_BUFMGR_SW_INT_ACK;\
256 type MCIF_WB_BUFMGR_SW_SLICE_INT_EN;\
257 type MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN;\
258 type MCIF_WB_BUFMGR_SW_LOCK;\
259 type MCIF_WB_P_VMID;\
260 type MCIF_WB_BUF_ADDR_FENCE_EN;\
261 type MCIF_WB_BUFMGR_CUR_LINE_R;\
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| /linux/include/uapi/linux/ |
| H A D | v4l2-dv-timings.h | 26 .type = V4L2_DV_BT_656_1120, \
36 .type = V4L2_DV_BT_656_1120, \
46 .type = V4L2_DV_BT_656_1120, \
57 .type = V4L2_DV_BT_656_1120, \
67 .type = V4L2_DV_BT_656_1120, \
76 .type = V4L2_DV_BT_656_1120, \
85 .type = V4L2_DV_BT_656_1120, \
94 .type = V4L2_DV_BT_656_1120, \
104 .type = V4L2_DV_BT_656_1120, \
113 .type = V4L2_DV_BT_656_1120, \
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| /linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
| H A D | dcn20_dwb.h | 202 #define DWBC_REG_FIELD_LIST_DCN2_0(type) \ argument
203 type WB_ENABLE;\
204 type DISPCLK_R_WB_GATE_DIS;\
205 type DISPCLK_G_WB_GATE_DIS;\
206 type DISPCLK_G_WBSCL_GATE_DIS;\
207 type WB_TEST_CLK_SEL;\
208 type WB_LB_LS_DIS;\
209 type WB_LB_SD_DIS;\
210 type WB_LUT_LS_DIS;\
211 type WBSCL_LB_MEM_PWR_MODE_SEL;\
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| /linux/drivers/gpu/drm/amd/display/dc/hubp/dcn20/ |
| H A D | dcn20_hubp.h | 185 #define DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type) \ argument
186 DCN_HUBP_REG_FIELD_BASE_LIST(type); \
187 type DMDATA_ADDRESS_HIGH;\
188 type DMDATA_MODE;\
189 type DMDATA_UPDATED;\
190 type DMDATA_REPEAT;\
191 type DMDATA_SIZE;\
192 type DMDATA_SW_UPDATED;\
193 type DMDATA_SW_REPEAT;\
194 type DMDATA_SW_SIZE;\
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| /linux/drivers/media/pci/saa7134/ |
| H A D | saa7134-cards.c | 65 .type = SAA7134_INPUT_COMPOSITE,
80 .type = SAA7134_INPUT_COMPOSITE1,
84 .type = SAA7134_INPUT_TV,
88 .type = SAA7134_INPUT_TV_MONO,
93 .type = SAA7134_INPUT_RADIO,
108 .type = SAA7134_INPUT_TV,
113 .type = SAA7134_INPUT_TV_MONO,
118 .type = SAA7134_INPUT_COMPOSITE1,
123 .type = SAA7134_INPUT_COMPOSITE2,
128 .type = SAA7134_INPUT_SVIDEO,
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| /linux/drivers/gpu/drm/amd/display/dc/hubp/dcn10/ |
| H A D | dcn10_hubp.h | 473 #define DCN_HUBP_REG_FIELD_BASE_LIST(type) \ argument
474 type HUBP_BLANK_EN;\
475 type HUBP_DISABLE;\
476 type HUBP_TTU_DISABLE;\
477 type HUBP_NO_OUTSTANDING_REQ;\
478 type HUBP_VTG_SEL;\
479 type HUBP_UNDERFLOW_STATUS;\
480 type HUBP_UNDERFLOW_CLEAR;\
481 type HUBP_IN_BLANK;\
482 type NUM_PIPES;\
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| /linux/net/tipc/ |
| H A D | netlink.c | 48 [TIPC_NLA_UNSPEC] = { .type = NLA_UNSPEC, },
49 [TIPC_NLA_BEARER] = { .type = NLA_NESTED, },
50 [TIPC_NLA_SOCK] = { .type = NLA_NESTED, },
51 [TIPC_NLA_PUBL] = { .type = NLA_NESTED, },
52 [TIPC_NLA_LINK] = { .type = NLA_NESTED, },
53 [TIPC_NLA_MEDIA] = { .type = NLA_NESTED, },
54 [TIPC_NLA_NODE] = { .type = NLA_NESTED, },
55 [TIPC_NLA_NET] = { .type = NLA_NESTED, },
56 [TIPC_NLA_NAME_TABLE] = { .type = NLA_NESTED, },
57 [TIPC_NLA_MON] = { .type = NLA_NESTED, },
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| /linux/drivers/iommu/generic_pt/ |
| H A D | pt_log2.h | 14 #define log2_to_int_t(type, a_lg2) ((type)(((type)1) << (a_lg2))) argument
18 #define log2_to_max_int_t(type, a_lg2) ((type)(log2_to_int_t(type, a_lg2) - 1)) argument
21 #define log2_div_t(type, a, b_lg2) ((type)(((type)a) >> (b_lg2))) argument
29 #define log2_div_eq_t(type, a, b, c_lg2) \ argument
30 (log2_div_t(type, (a) ^ (b), c_lg2) == 0)
34 #define log2_mod_t(type, a, b_lg2) \ argument
35 ((type)(((type)a) & log2_to_max_int_t(type, b_lg2)))
43 #define log2_mod_eq_max_t(type, a, b_lg2) \ argument
44 (log2_mod_t(type, a, b_lg2) == log2_to_max_int_t(type, b_lg2))
53 #define log2_set_mod_t(type, a, val, b_lg2) \ argument
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| /linux/drivers/gpu/drm/amd/display/dc/dcn10/ |
| H A D | dcn10_dwb.h | 148 #define DWBC_REG_FIELD_LIST(type) \ argument
149 type WB_ENABLE;\
150 type DISPCLK_R_WB_GATE_DIS;\
151 type DISPCLK_G_WB_GATE_DIS;\
152 type DISPCLK_G_WBSCL_GATE_DIS;\
153 type WB_LB_LS_DIS;\
154 type WB_LB_SD_DIS;\
155 type WB_LUT_LS_DIS;\
156 type CNV_WINDOW_CROP_EN;\
157 type CNV_STEREO_TYPE;\
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| /linux/scripts/kconfig/ |
| H A D | expr.c | 33 static struct expr *expr_lookup(enum expr_type type, void *l, void *r) in expr_lookup() argument
38 hash = hash_32((unsigned int)type ^ hash_ptr(l) ^ hash_ptr(r)); in expr_lookup()
41 if (e->type == type && e->left._initdata == l && in expr_lookup()
47 e->type = type; in expr_lookup()
62 struct expr *expr_alloc_one(enum expr_type type, struct expr *ce) in expr_alloc_one() argument
64 return expr_lookup(type, ce, NULL); in expr_alloc_one()
67 struct expr *expr_alloc_two(enum expr_type type, struct expr *e1, struct expr *e2) in expr_alloc_two() argument
69 return expr_lookup(type, e1, e2); in expr_alloc_two()
72 struct expr *expr_alloc_comp(enum expr_type type, struct symbol *s1, struct symbol *s2) in expr_alloc_comp() argument
74 return expr_lookup(type, s1, s2); in expr_alloc_comp()
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| /linux/fs/orangefs/ |
| H A D | orangefs-cache.c | 49 __s32 type = new_op->upcall.type; in get_opname_string() local
51 if (type == ORANGEFS_VFS_OP_FILE_IO) in get_opname_string()
53 else if (type == ORANGEFS_VFS_OP_LOOKUP) in get_opname_string()
55 else if (type == ORANGEFS_VFS_OP_CREATE) in get_opname_string()
57 else if (type == ORANGEFS_VFS_OP_GETATTR) in get_opname_string()
59 else if (type == ORANGEFS_VFS_OP_REMOVE) in get_opname_string()
61 else if (type == ORANGEFS_VFS_OP_MKDIR) in get_opname_string()
63 else if (type == ORANGEFS_VFS_OP_READDIR) in get_opname_string()
65 else if (type == ORANGEFS_VFS_OP_READDIRPLUS) in get_opname_string()
67 else if (type == ORANGEFS_VFS_OP_SETATTR) in get_opname_string()
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| /linux/drivers/gpu/drm/amd/display/dc/mpc/dcn30/ |
| H A D | dcn30_mpc.h | 645 #define MPC_REG_FIELD_LIST_DCN3_0(type) \ argument
646 MPC_REG_FIELD_LIST_DCN2_0(type) \
647 type MPC_DWB0_MUX;\
648 type MPC_DWB0_MUX_STATUS;\
649 type MPC_OUT_RATE_CONTROL;\
650 type MPC_OUT_RATE_CONTROL_DISABLE;\
651 type MPC_OUT_FLOW_CONTROL_MODE;\
652 type MPC_OUT_FLOW_CONTROL_COUNT; \
653 type MPCC_GAMUT_REMAP_MODE; \
654 type MPCC_GAMUT_REMAP_MODE_CURRENT;\
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| /linux/arch/mips/include/asm/ |
| H A D | unaligned-emul.h | 8 #define _LoadHW(addr, value, res, type) \ argument
11 "1:\t"type##_lb("%0", "0(%2)")"\n" \
12 "2:\t"type##_lbu("$1", "1(%2)")"\n\t"\
31 #define _LoadW(addr, value, res, type) \ argument
34 "1:\t"type##_lwl("%0", "(%2)")"\n" \
35 "2:\t"type##_lwr("%0", "3(%2)")"\n\t"\
53 #define _LoadW(addr, value, res, type) \ argument
58 "1:"type##_lb("%0", "0(%2)")"\n\t" \
59 "2:"type##_lbu("$1", "1(%2)")"\n\t" \
62 "3:"type##_lbu("$1", "2(%2)")"\n\t" \
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| /linux/drivers/gpu/drm/amd/display/dc/dcn31/ |
| H A D | dcn31_vpg.h | 93 #define VPG_DCN31_REG_FIELD_LIST(type) \ argument
94 type VPG_GENERIC_CONFLICT_OCCURED;\
95 type VPG_GENERIC_CONFLICT_CLR;\
96 type VPG_GENERIC_DATA_INDEX;\
97 type VPG_GENERIC_DATA_BYTE0;\
98 type VPG_GENERIC_DATA_BYTE1;\
99 type VPG_GENERIC_DATA_BYTE2;\
100 type VPG_GENERIC_DATA_BYTE3;\
101 type VPG_GENERIC0_FRAME_UPDATE;\
102 type VPG_GENERIC1_FRAME_UPDATE;\
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