1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #ifndef __RTW89_FW_H__
6 #define __RTW89_FW_H__
7
8 #include "core.h"
9
10 enum rtw89_fw_dl_status {
11 RTW89_FWDL_INITIAL_STATE = 0,
12 RTW89_FWDL_FWDL_ONGOING = 1,
13 RTW89_FWDL_CHECKSUM_FAIL = 2,
14 RTW89_FWDL_SECURITY_FAIL = 3,
15 RTW89_FWDL_CV_NOT_MATCH = 4,
16 RTW89_FWDL_RSVD0 = 5,
17 RTW89_FWDL_WCPU_FWDL_RDY = 6,
18 RTW89_FWDL_WCPU_FW_INIT_RDY = 7
19 };
20
21 struct rtw89_c2hreg_hdr {
22 u32 w0;
23 };
24
25 #define RTW89_C2HREG_HDR_FUNC_MASK GENMASK(6, 0)
26 #define RTW89_C2HREG_HDR_ACK BIT(7)
27 #define RTW89_C2HREG_HDR_LEN_MASK GENMASK(11, 8)
28 #define RTW89_C2HREG_HDR_SEQ_MASK GENMASK(15, 12)
29
30 struct rtw89_c2hreg_phycap {
31 u32 w0;
32 u32 w1;
33 u32 w2;
34 u32 w3;
35 } __packed;
36
37 #define RTW89_C2HREG_PHYCAP_W0_FUNC GENMASK(6, 0)
38 #define RTW89_C2HREG_PHYCAP_W0_ACK BIT(7)
39 #define RTW89_C2HREG_PHYCAP_W0_LEN GENMASK(11, 8)
40 #define RTW89_C2HREG_PHYCAP_W0_SEQ GENMASK(15, 12)
41 #define RTW89_C2HREG_PHYCAP_W0_RX_NSS GENMASK(23, 16)
42 #define RTW89_C2HREG_PHYCAP_W0_BW GENMASK(31, 24)
43 #define RTW89_C2HREG_PHYCAP_W1_TX_NSS GENMASK(7, 0)
44 #define RTW89_C2HREG_PHYCAP_W1_PROT GENMASK(15, 8)
45 #define RTW89_C2HREG_PHYCAP_W1_PROT_11N 1
46 #define RTW89_C2HREG_PHYCAP_W1_PROT_11AC 2
47 #define RTW89_C2HREG_PHYCAP_W1_PROT_11AX 3
48 #define RTW89_C2HREG_PHYCAP_W1_PROT_11BE 4
49 #define RTW89_C2HREG_PHYCAP_W1_NIC GENMASK(23, 16)
50 #define RTW89_C2HREG_PHYCAP_W1_WL_FUNC GENMASK(31, 24)
51 #define RTW89_C2HREG_PHYCAP_W2_HW_TYPE GENMASK(7, 0)
52 #define RTW89_C2HREG_PHYCAP_W3_ANT_TX_NUM GENMASK(15, 8)
53 #define RTW89_C2HREG_PHYCAP_W3_ANT_RX_NUM GENMASK(23, 16)
54 #define RTW89_C2HREG_PHYCAP_W3_BAND_SEL GENMASK(31, 24)
55
56 #define RTW89_C2HREG_PHYCAP_P1_W0_B1_RX_NSS GENMASK(23, 16)
57 #define RTW89_C2HREG_PHYCAP_P1_W0_B1_BW GENMASK(31, 24)
58 #define RTW89_C2HREG_PHYCAP_P1_W1_B1_TX_NSS GENMASK(7, 0)
59 #define RTW89_C2HREG_PHYCAP_P1_W1_B1_ANT_TX_NUM GENMASK(15, 8)
60 #define RTW89_C2HREG_PHYCAP_P1_W1_B1_ANT_RX_NUM GENMASK(23, 16)
61 #define RTW89_C2HREG_PHYCAP_P1_W1_B1_BAND_SEL GENMASK(31, 24)
62 #define RTW89_C2HREG_PHYCAP_P1_W2_QAM GENMASK(7, 0)
63 #define RTW89_C2HREG_PHYCAP_P1_W2_QAM_256 0x1
64 #define RTW89_C2HREG_PHYCAP_P1_W2_QAM_1024 0x2
65 #define RTW89_C2HREG_PHYCAP_P1_W2_QAM_4096 0x3
66 #define RTW89_C2HREG_PHYCAP_P1_W2_B1_QAM GENMASK(15, 8)
67
68 #define RTW89_C2HREG_AOAC_RPT_1_W0_KEY_IDX GENMASK(23, 16)
69 #define RTW89_C2HREG_AOAC_RPT_1_W1_IV_0 GENMASK(7, 0)
70 #define RTW89_C2HREG_AOAC_RPT_1_W1_IV_1 GENMASK(15, 8)
71 #define RTW89_C2HREG_AOAC_RPT_1_W1_IV_2 GENMASK(23, 16)
72 #define RTW89_C2HREG_AOAC_RPT_1_W1_IV_3 GENMASK(31, 24)
73 #define RTW89_C2HREG_AOAC_RPT_1_W2_IV_4 GENMASK(7, 0)
74 #define RTW89_C2HREG_AOAC_RPT_1_W2_IV_5 GENMASK(15, 8)
75 #define RTW89_C2HREG_AOAC_RPT_1_W2_IV_6 GENMASK(23, 16)
76 #define RTW89_C2HREG_AOAC_RPT_1_W2_IV_7 GENMASK(31, 24)
77 #define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_0 GENMASK(7, 0)
78 #define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_1 GENMASK(15, 8)
79 #define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_2 GENMASK(23, 16)
80 #define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_3 GENMASK(31, 24)
81 #define RTW89_C2HREG_AOAC_RPT_2_W0_PTK_IV_4 GENMASK(23, 16)
82 #define RTW89_C2HREG_AOAC_RPT_2_W0_PTK_IV_5 GENMASK(31, 24)
83 #define RTW89_C2HREG_AOAC_RPT_2_W1_PTK_IV_6 GENMASK(7, 0)
84 #define RTW89_C2HREG_AOAC_RPT_2_W1_PTK_IV_7 GENMASK(15, 8)
85 #define RTW89_C2HREG_AOAC_RPT_2_W1_IGTK_IPN_IV_0 GENMASK(23, 16)
86 #define RTW89_C2HREG_AOAC_RPT_2_W1_IGTK_IPN_IV_1 GENMASK(31, 24)
87 #define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_2 GENMASK(7, 0)
88 #define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_3 GENMASK(15, 8)
89 #define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_4 GENMASK(23, 16)
90 #define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_5 GENMASK(31, 24)
91 #define RTW89_C2HREG_AOAC_RPT_2_W3_IGTK_IPN_IV_6 GENMASK(7, 0)
92 #define RTW89_C2HREG_AOAC_RPT_2_W3_IGTK_IPN_IV_7 GENMASK(15, 8)
93
94 #define RTW89_C2HREG_PS_LEAVE_ACK_RET GENMASK(7, 0)
95 #define RTW89_C2HREG_PS_LEAVE_ACK_MACID GENMASK(31, 16)
96
97 struct rtw89_h2creg_hdr {
98 u32 w0;
99 };
100
101 #define RTW89_H2CREG_HDR_FUNC_MASK GENMASK(6, 0)
102 #define RTW89_H2CREG_HDR_LEN_MASK GENMASK(11, 8)
103
104 struct rtw89_h2creg_sch_tx_en {
105 u32 w0;
106 u32 w1;
107 } __packed;
108
109 #define RTW89_H2CREG_SCH_TX_EN_W0_EN GENMASK(31, 16)
110 #define RTW89_H2CREG_SCH_TX_EN_W1_MASK GENMASK(15, 0)
111 #define RTW89_H2CREG_SCH_TX_EN_W1_BAND BIT(16)
112
113 #define RTW89_H2CREG_WOW_CPUIO_RX_CTRL_EN GENMASK(23, 16)
114
115 #define RTW89_H2CREG_GET_FEATURE_PART_NUM GENMASK(23, 16)
116
117 #define RTW89_H2CREG_MAX 4
118 #define RTW89_C2HREG_MAX 4
119 #define RTW89_C2HREG_HDR_LEN 2
120 #define RTW89_H2CREG_HDR_LEN 2
121 #define RTW89_C2H_TIMEOUT 1000000
122 #define RTW89_C2H_TIMEOUT_USB 4000
123
124 struct rtw89_mac_c2h_info {
125 u8 id;
126 u8 content_len;
127 u32 timeout;
128 union {
129 u32 c2hreg[RTW89_C2HREG_MAX];
130 struct rtw89_c2hreg_hdr hdr;
131 struct rtw89_c2hreg_phycap phycap;
132 } u;
133 };
134
135 struct rtw89_mac_h2c_info {
136 u8 id;
137 u8 content_len;
138 union {
139 u32 h2creg[RTW89_H2CREG_MAX];
140 struct rtw89_h2creg_hdr hdr;
141 struct rtw89_h2creg_sch_tx_en sch_tx_en;
142 } u;
143 };
144
145 enum rtw89_mac_h2c_type {
146 RTW89_FWCMD_H2CREG_FUNC_H2CREG_LB = 0,
147 RTW89_FWCMD_H2CREG_FUNC_CNSL_CMD,
148 RTW89_FWCMD_H2CREG_FUNC_FWERR,
149 RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE,
150 RTW89_FWCMD_H2CREG_FUNC_GETPKT_INFORM,
151 RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN,
152 RTW89_FWCMD_H2CREG_FUNC_WOW_TRX_STOP,
153 RTW89_FWCMD_H2CREG_FUNC_AOAC_RPT_1,
154 RTW89_FWCMD_H2CREG_FUNC_AOAC_RPT_2,
155 RTW89_FWCMD_H2CREG_FUNC_AOAC_RPT_3_REQ,
156 RTW89_FWCMD_H2CREG_FUNC_WOW_CPUIO_RX_CTRL,
157 };
158
159 enum rtw89_mac_c2h_type {
160 RTW89_FWCMD_C2HREG_FUNC_C2HREG_LB = 0,
161 RTW89_FWCMD_C2HREG_FUNC_ERR_RPT,
162 RTW89_FWCMD_C2HREG_FUNC_ERR_MSG,
163 RTW89_FWCMD_C2HREG_FUNC_PHY_CAP,
164 RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT,
165 RTW89_FWCMD_C2HREG_FUNC_WOW_CPUIO_RX_ACK = 0xA,
166 RTW89_FWCMD_C2HREG_FUNC_PHY_CAP_PART1 = 0xC,
167 RTW89_FWCMD_C2HREG_FUNC_PS_LEAVE_ACK = 0xD,
168 RTW89_FWCMD_C2HREG_FUNC_NULL = 0xFF,
169 };
170
171 enum rtw89_fw_c2h_category {
172 RTW89_C2H_CAT_TEST,
173 RTW89_C2H_CAT_MAC,
174 RTW89_C2H_CAT_OUTSRC,
175 };
176
177 enum rtw89_fw_log_level {
178 RTW89_FW_LOG_LEVEL_OFF,
179 RTW89_FW_LOG_LEVEL_CRT,
180 RTW89_FW_LOG_LEVEL_SER,
181 RTW89_FW_LOG_LEVEL_WARN,
182 RTW89_FW_LOG_LEVEL_LOUD,
183 RTW89_FW_LOG_LEVEL_TR,
184 };
185
186 enum rtw89_fw_log_path {
187 RTW89_FW_LOG_LEVEL_UART,
188 RTW89_FW_LOG_LEVEL_C2H,
189 RTW89_FW_LOG_LEVEL_SNI,
190 };
191
192 enum rtw89_fw_log_comp {
193 RTW89_FW_LOG_COMP_VER,
194 RTW89_FW_LOG_COMP_INIT,
195 RTW89_FW_LOG_COMP_TASK,
196 RTW89_FW_LOG_COMP_CNS,
197 RTW89_FW_LOG_COMP_H2C,
198 RTW89_FW_LOG_COMP_C2H,
199 RTW89_FW_LOG_COMP_TX,
200 RTW89_FW_LOG_COMP_RX,
201 RTW89_FW_LOG_COMP_IPSEC,
202 RTW89_FW_LOG_COMP_TIMER,
203 RTW89_FW_LOG_COMP_DBGPKT,
204 RTW89_FW_LOG_COMP_PS,
205 RTW89_FW_LOG_COMP_ERROR,
206 RTW89_FW_LOG_COMP_WOWLAN,
207 RTW89_FW_LOG_COMP_SECURE_BOOT,
208 RTW89_FW_LOG_COMP_BTC,
209 RTW89_FW_LOG_COMP_BB,
210 RTW89_FW_LOG_COMP_TWT,
211 RTW89_FW_LOG_COMP_RF,
212 RTW89_FW_LOG_COMP_MCC = 20,
213 RTW89_FW_LOG_COMP_MLO = 26,
214 RTW89_FW_LOG_COMP_SCAN = 28,
215 };
216
217 enum rtw89_pkt_offload_op {
218 RTW89_PKT_OFLD_OP_ADD,
219 RTW89_PKT_OFLD_OP_DEL,
220 RTW89_PKT_OFLD_OP_READ,
221
222 NUM_OF_RTW89_PKT_OFFLOAD_OP,
223 };
224
225 #define RTW89_PKT_OFLD_WAIT_TAG(pkt_id, pkt_op) \
226 ((pkt_id) * NUM_OF_RTW89_PKT_OFFLOAD_OP + (pkt_op))
227
228 enum rtw89_scanofld_notify_reason {
229 RTW89_SCAN_DWELL_NOTIFY,
230 RTW89_SCAN_PRE_TX_NOTIFY,
231 RTW89_SCAN_POST_TX_NOTIFY,
232 RTW89_SCAN_ENTER_CH_NOTIFY,
233 RTW89_SCAN_LEAVE_CH_NOTIFY,
234 RTW89_SCAN_END_SCAN_NOTIFY,
235 RTW89_SCAN_REPORT_NOTIFY,
236 RTW89_SCAN_CHKPT_NOTIFY,
237 RTW89_SCAN_ENTER_OP_NOTIFY,
238 RTW89_SCAN_LEAVE_OP_NOTIFY,
239 };
240
241 enum rtw89_scanofld_status {
242 RTW89_SCAN_STATUS_NOTIFY,
243 RTW89_SCAN_STATUS_SUCCESS,
244 RTW89_SCAN_STATUS_FAIL,
245 };
246
247 enum rtw89_chan_type {
248 RTW89_CHAN_OPERATE = 0,
249 RTW89_CHAN_ACTIVE,
250 RTW89_CHAN_DFS,
251 RTW89_CHAN_EXTRA_OP,
252 };
253
254 enum rtw89_p2pps_action {
255 RTW89_P2P_ACT_INIT = 0,
256 RTW89_P2P_ACT_UPDATE = 1,
257 RTW89_P2P_ACT_REMOVE = 2,
258 RTW89_P2P_ACT_TERMINATE = 3,
259 };
260
261 #define RTW89_DEFAULT_CQM_HYST 4
262 #define RTW89_DEFAULT_CQM_THOLD -70
263
264 enum rtw89_bcn_fltr_offload_mode {
265 RTW89_BCN_FLTR_OFFLOAD_MODE_0 = 0,
266 RTW89_BCN_FLTR_OFFLOAD_MODE_1,
267 RTW89_BCN_FLTR_OFFLOAD_MODE_2,
268 RTW89_BCN_FLTR_OFFLOAD_MODE_3,
269
270 RTW89_BCN_FLTR_OFFLOAD_MODE_DEFAULT = RTW89_BCN_FLTR_OFFLOAD_MODE_0,
271 };
272
273 enum rtw89_bcn_fltr_type {
274 RTW89_BCN_FLTR_BEACON_LOSS,
275 RTW89_BCN_FLTR_RSSI,
276 RTW89_BCN_FLTR_NOTIFY,
277 };
278
279 enum rtw89_bcn_fltr_rssi_event {
280 RTW89_BCN_FLTR_RSSI_NOT_CHANGED,
281 RTW89_BCN_FLTR_RSSI_HIGH,
282 RTW89_BCN_FLTR_RSSI_LOW,
283 };
284
285 #define FWDL_SECTION_MAX_NUM 10
286 #define FWDL_SECTION_CHKSUM_LEN 8
287 #define FWDL_SECTION_PER_PKT_LEN 2020
288
289 struct rtw89_fw_hdr_section_info {
290 u8 redl;
291 const u8 *addr;
292 u32 len;
293 u32 len_override;
294 u32 dladdr;
295 u32 mssc;
296 u8 type;
297 bool ignore;
298 const u8 *key_addr;
299 u32 key_len;
300 u32 key_idx;
301 };
302
303 struct rtw89_fw_bin_info {
304 u8 section_num;
305 u32 part_size;
306 u32 hdr_len;
307 bool dynamic_hdr_en;
308 u32 dynamic_hdr_len;
309 u8 idmem_share_mode;
310 bool dsp_checksum;
311 bool secure_section_exist;
312 struct rtw89_fw_hdr_section_info section_info[FWDL_SECTION_MAX_NUM];
313 };
314
315 struct rtw89_fw_macid_pause_grp {
316 __le32 pause_grp[4];
317 __le32 mask_grp[4];
318 } __packed;
319
320 struct rtw89_fw_macid_pause_sleep_grp {
321 struct {
322 __le32 pause_grp[4];
323 __le32 pause_mask_grp[4];
324 __le32 sleep_grp[4];
325 __le32 sleep_mask_grp[4];
326 } __packed n[4];
327 } __packed;
328
329 #define RTW89_H2C_MAX_SIZE 2048
330 #define RTW89_CHANNEL_TIME 45
331 #define RTW89_CHANNEL_TIME_6G 20
332 #define RTW89_CHANNEL_TIME_EXTRA_OP 30
333 #define RTW89_DFS_CHAN_TIME 105
334 #define RTW89_OFF_CHAN_TIME 100
335 #define RTW89_P2P_CHAN_TIME 105
336 #define RTW89_DWELL_TIME 20
337 #define RTW89_DWELL_TIME_6G 10
338 #define RTW89_SCAN_WIDTH 0
339 #define RTW89_SCANOFLD_MAX_SSID 8
340 #define RTW89_SCANOFLD_MAX_IE_LEN 512
341 #define RTW89_SCANOFLD_PKT_NONE 0xFF
342 #define RTW89_SCANOFLD_DEBUG_MASK 0x1F
343 #define RTW89_CHAN_INVALID 0xFF
344 #define RTW89_MAC_CHINFO_SIZE 28
345 #define RTW89_MAC_CHINFO_SIZE_BE 32
346 #define RTW89_SCAN_LIST_GUARD 4
347 #define RTW89_SCAN_LIST_LIMIT(size) \
348 ((RTW89_H2C_MAX_SIZE / (size)) - RTW89_SCAN_LIST_GUARD)
349 #define RTW89_SCAN_LIST_LIMIT_AX RTW89_SCAN_LIST_LIMIT(RTW89_MAC_CHINFO_SIZE)
350 #define RTW89_SCAN_LIST_LIMIT_BE RTW89_SCAN_LIST_LIMIT(RTW89_MAC_CHINFO_SIZE_BE)
351
352 #define RTW89_BCN_LOSS_CNT 60
353
354 struct rtw89_mac_chinfo_ax {
355 u8 period;
356 u8 dwell_time;
357 u8 central_ch;
358 u8 pri_ch;
359 u8 bw:3;
360 u8 notify_action:5;
361 u8 num_pkt:4;
362 u8 tx_pkt:1;
363 u8 pause_data:1;
364 u8 ch_band:2;
365 u8 probe_id;
366 u8 dfs_ch:1;
367 u8 tx_null:1;
368 u8 rand_seq_num:1;
369 u8 cfg_tx_pwr:1;
370 u8 macid_tx: 1;
371 u8 rsvd0: 3;
372 u8 pkt_id[RTW89_SCANOFLD_MAX_SSID];
373 u16 tx_pwr_idx;
374 u8 rsvd1;
375 struct list_head list;
376 bool is_psc;
377 };
378
379 struct rtw89_mac_chinfo_be {
380 u8 period;
381 u8 dwell_time;
382 u8 central_ch;
383 u8 pri_ch;
384 u8 bw:3;
385 u8 ch_band:2;
386 u8 dfs_ch:1;
387 u8 pause_data:1;
388 u8 tx_null:1;
389 u8 rand_seq_num:1;
390 u8 notify_action:5;
391 u8 probe_id;
392 u8 leave_crit;
393 u8 chkpt_timer;
394 u8 leave_time;
395 u8 leave_th;
396 u16 tx_pkt_ctrl;
397 u8 pkt_id[RTW89_SCANOFLD_MAX_SSID];
398 u8 sw_def;
399 u16 fw_probe0_ssids;
400 u16 fw_probe0_shortssids;
401 u16 fw_probe0_bssids;
402
403 struct list_head list;
404 bool is_psc;
405 };
406
407 struct rtw89_pktofld_info {
408 struct list_head list;
409 u8 id;
410 bool wildcard_6ghz;
411
412 /* Below fields are for WiFi 6 chips 6 GHz RNR use only */
413 u8 ssid[IEEE80211_MAX_SSID_LEN];
414 u8 ssid_len;
415 u8 bssid[ETH_ALEN];
416 u16 channel_6ghz;
417 bool cancel;
418 };
419
420 struct rtw89_h2c_ra {
421 __le32 w0;
422 __le32 w1;
423 __le32 w2;
424 __le32 w3;
425 } __packed;
426
427 #define RTW89_H2C_RA_W0_IS_DIS BIT(0)
428 #define RTW89_H2C_RA_W0_MODE GENMASK(5, 1)
429 #define RTW89_H2C_RA_W0_BW_CAP GENMASK(7, 6)
430 #define RTW89_H2C_RA_W0_MACID GENMASK(15, 8)
431 #define RTW89_H2C_RA_W0_DCM BIT(16)
432 #define RTW89_H2C_RA_W0_ER BIT(17)
433 #define RTW89_H2C_RA_W0_INIT_RATE_LV GENMASK(19, 18)
434 #define RTW89_H2C_RA_W0_UPD_ALL BIT(20)
435 #define RTW89_H2C_RA_W0_SGI BIT(21)
436 #define RTW89_H2C_RA_W0_LDPC BIT(22)
437 #define RTW89_H2C_RA_W0_STBC BIT(23)
438 #define RTW89_H2C_RA_W0_SS_NUM GENMASK(26, 24)
439 #define RTW89_H2C_RA_W0_GILTF GENMASK(29, 27)
440 #define RTW89_H2C_RA_W0_UPD_BW_NSS_MASK BIT(30)
441 #define RTW89_H2C_RA_W0_UPD_MASK BIT(31)
442 #define RTW89_H2C_RA_W1_RAMASK_LO32 GENMASK(31, 0)
443 #define RTW89_H2C_RA_W2_RAMASK_HI32 GENMASK(30, 0)
444 #define RTW89_H2C_RA_W2_BFEE_CSI_CTL BIT(31)
445 #define RTW89_H2C_RA_W3_BAND_NUM GENMASK(7, 0)
446 #define RTW89_H2C_RA_W3_RA_CSI_RATE_EN BIT(8)
447 #define RTW89_H2C_RA_W3_FIXED_CSI_RATE_EN BIT(9)
448 #define RTW89_H2C_RA_W3_CR_TBL_SEL BIT(10)
449 #define RTW89_H2C_RA_W3_FIX_GILTF_EN BIT(11)
450 #define RTW89_H2C_RA_W3_FIX_GILTF GENMASK(14, 12)
451 #define RTW89_H2C_RA_W3_FIXED_CSI_MCS_SS_IDX GENMASK(23, 16)
452 #define RTW89_H2C_RA_W3_FIXED_CSI_MODE GENMASK(25, 24)
453 #define RTW89_H2C_RA_W3_FIXED_CSI_GI_LTF GENMASK(28, 26)
454 #define RTW89_H2C_RA_W3_FIXED_CSI_BW GENMASK(31, 29)
455 #define RTW89_H2C_RA_V1_W3_PARTIAL_BW_SU_ER BIT(15)
456 #define RTW89_H2C_RA_V1_W3_FIXED_CSI_RATE_L GENMASK(23, 16)
457 #define RTW89_H2C_RA_V1_W3_IS_NOISY BIT(24)
458 #define RTW89_H2C_RA_V1_W3_PSRA_EN BIT(25)
459 #define RTW89_H2C_RA_V1_W3_MACID_MSB GENMASK(28, 27)
460 #define RTW89_H2C_RA_V1_W3_BAND GENMASK(30, 29)
461 #define RTW89_H2C_RA_V1_W3_NEW_DBGREG BIT(31)
462
463 struct rtw89_h2c_ra_v1 {
464 struct rtw89_h2c_ra v0;
465 __le32 w4;
466 __le32 w5;
467 } __packed;
468
469 #define RTW89_H2C_RA_V1_W4_MODE_EHT GENMASK(6, 0)
470 #define RTW89_H2C_RA_V1_W4_BW_EHT GENMASK(10, 8)
471 #define RTW89_H2C_RA_V1_W4_RAMASK_UHL16 GENMASK(31, 16)
472 #define RTW89_H2C_RA_V1_W5_RAMASK_UHH16 GENMASK(15, 0)
473
RTW89_SET_FWCMD_SEC_IDX(void * cmd,u32 val)474 static inline void RTW89_SET_FWCMD_SEC_IDX(void *cmd, u32 val)
475 {
476 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 0));
477 }
478
RTW89_SET_FWCMD_SEC_OFFSET(void * cmd,u32 val)479 static inline void RTW89_SET_FWCMD_SEC_OFFSET(void *cmd, u32 val)
480 {
481 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8));
482 }
483
RTW89_SET_FWCMD_SEC_LEN(void * cmd,u32 val)484 static inline void RTW89_SET_FWCMD_SEC_LEN(void *cmd, u32 val)
485 {
486 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(23, 16));
487 }
488
RTW89_SET_FWCMD_SEC_TYPE(void * cmd,u32 val)489 static inline void RTW89_SET_FWCMD_SEC_TYPE(void *cmd, u32 val)
490 {
491 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(3, 0));
492 }
493
RTW89_SET_FWCMD_SEC_EXT_KEY(void * cmd,u32 val)494 static inline void RTW89_SET_FWCMD_SEC_EXT_KEY(void *cmd, u32 val)
495 {
496 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(4));
497 }
498
RTW89_SET_FWCMD_SEC_SPP_MODE(void * cmd,u32 val)499 static inline void RTW89_SET_FWCMD_SEC_SPP_MODE(void *cmd, u32 val)
500 {
501 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(5));
502 }
503
RTW89_SET_FWCMD_SEC_KEY0(void * cmd,u32 val)504 static inline void RTW89_SET_FWCMD_SEC_KEY0(void *cmd, u32 val)
505 {
506 le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(31, 0));
507 }
508
RTW89_SET_FWCMD_SEC_KEY1(void * cmd,u32 val)509 static inline void RTW89_SET_FWCMD_SEC_KEY1(void *cmd, u32 val)
510 {
511 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 0));
512 }
513
RTW89_SET_FWCMD_SEC_KEY2(void * cmd,u32 val)514 static inline void RTW89_SET_FWCMD_SEC_KEY2(void *cmd, u32 val)
515 {
516 le32p_replace_bits((__le32 *)(cmd) + 0x04, val, GENMASK(31, 0));
517 }
518
RTW89_SET_FWCMD_SEC_KEY3(void * cmd,u32 val)519 static inline void RTW89_SET_FWCMD_SEC_KEY3(void *cmd, u32 val)
520 {
521 le32p_replace_bits((__le32 *)(cmd) + 0x05, val, GENMASK(31, 0));
522 }
523
RTW89_SET_EDCA_SEL(void * cmd,u32 val)524 static inline void RTW89_SET_EDCA_SEL(void *cmd, u32 val)
525 {
526 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(1, 0));
527 }
528
RTW89_SET_EDCA_BAND(void * cmd,u32 val)529 static inline void RTW89_SET_EDCA_BAND(void *cmd, u32 val)
530 {
531 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(3));
532 }
533
RTW89_SET_EDCA_WMM(void * cmd,u32 val)534 static inline void RTW89_SET_EDCA_WMM(void *cmd, u32 val)
535 {
536 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(4));
537 }
538
RTW89_SET_EDCA_AC(void * cmd,u32 val)539 static inline void RTW89_SET_EDCA_AC(void *cmd, u32 val)
540 {
541 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(6, 5));
542 }
543
RTW89_SET_EDCA_PARAM(void * cmd,u32 val)544 static inline void RTW89_SET_EDCA_PARAM(void *cmd, u32 val)
545 {
546 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 0));
547 }
548 #define FW_EDCA_PARAM_TXOPLMT_MSK GENMASK(26, 16)
549 #define FW_EDCA_PARAM_CWMAX_MSK GENMASK(15, 12)
550 #define FW_EDCA_PARAM_CWMIN_MSK GENMASK(11, 8)
551 #define FW_EDCA_PARAM_AIFS_MSK GENMASK(7, 0)
552
553 #define FWDL_SECURITY_SECTION_TYPE 9
554 #define FWDL_SECURITY_SIGLEN 512
555 #define FWDL_SECURITY_CHKSUM_LEN 8
556
557 struct rtw89_fw_dynhdr_sec {
558 __le32 w0;
559 u8 content[];
560 } __packed;
561
562 struct rtw89_fw_dynhdr_hdr {
563 __le32 hdr_len;
564 __le32 setcion_count;
565 /* struct rtw89_fw_dynhdr_sec (nested flexible structures) */
566 } __packed;
567
568 struct rtw89_fw_hdr_section {
569 __le32 w0;
570 __le32 w1;
571 __le32 w2;
572 __le32 w3;
573 } __packed;
574
575 #define FWSECTION_HDR_W0_DL_ADDR GENMASK(31, 0)
576 #define FWSECTION_HDR_W1_METADATA GENMASK(31, 24)
577 #define FWSECTION_HDR_W1_SECTIONTYPE GENMASK(27, 24)
578 #define FWSECTION_HDR_W1_SEC_SIZE GENMASK(23, 0)
579 #define FWSECTION_HDR_W1_CHECKSUM BIT(28)
580 #define FWSECTION_HDR_W1_REDL BIT(29)
581 #define FWSECTION_HDR_W2_MSSC GENMASK(31, 0)
582
583 struct rtw89_fw_hdr {
584 __le32 w0;
585 __le32 w1;
586 __le32 w2;
587 __le32 w3;
588 __le32 w4;
589 __le32 w5;
590 __le32 w6;
591 __le32 w7;
592 struct rtw89_fw_hdr_section sections[];
593 /* struct rtw89_fw_dynhdr_hdr (optional) */
594 } __packed;
595
596 #define FW_HDR_W1_MAJOR_VERSION GENMASK(7, 0)
597 #define FW_HDR_W1_MINOR_VERSION GENMASK(15, 8)
598 #define FW_HDR_W1_SUBVERSION GENMASK(23, 16)
599 #define FW_HDR_W1_SUBINDEX GENMASK(31, 24)
600 #define FW_HDR_W2_COMMITID GENMASK(31, 0)
601 #define FW_HDR_W3_LEN GENMASK(23, 16)
602 #define FW_HDR_W3_HDR_VER GENMASK(31, 24)
603 #define FW_HDR_W4_MONTH GENMASK(7, 0)
604 #define FW_HDR_W4_DATE GENMASK(15, 8)
605 #define FW_HDR_W4_HOUR GENMASK(23, 16)
606 #define FW_HDR_W4_MIN GENMASK(31, 24)
607 #define FW_HDR_W5_YEAR GENMASK(31, 0)
608 #define FW_HDR_W6_SEC_NUM GENMASK(15, 8)
609 #define FW_HDR_W7_PART_SIZE GENMASK(15, 0)
610 #define FW_HDR_W7_DYN_HDR BIT(16)
611 #define FW_HDR_W7_IDMEM_SHARE_MODE GENMASK(21, 18)
612 #define FW_HDR_W7_CMD_VERSERION GENMASK(31, 24)
613
614 struct rtw89_fw_hdr_section_v1 {
615 __le32 w0;
616 __le32 w1;
617 __le32 w2;
618 __le32 w3;
619 } __packed;
620
621 #define FWSECTION_HDR_V1_W0_DL_ADDR GENMASK(31, 0)
622 #define FWSECTION_HDR_V1_W1_METADATA GENMASK(31, 24)
623 #define FWSECTION_HDR_V1_W1_SECTIONTYPE GENMASK(27, 24)
624 #define FWSECTION_HDR_V1_W1_SEC_SIZE GENMASK(23, 0)
625 #define FWSECTION_HDR_V1_W1_CHECKSUM BIT(28)
626 #define FWSECTION_HDR_V1_W1_REDL BIT(29)
627 #define FWSECTION_HDR_V1_W2_MSSC GENMASK(7, 0)
628 #define FORMATTED_MSSC 0xFF
629 #define FORMATTED_MSSC_MASK GENMASK(7, 0)
630 #define FWSECTION_HDR_V1_W2_BBMCU_IDX GENMASK(27, 24)
631
632 struct rtw89_fw_hdr_v1 {
633 __le32 w0;
634 __le32 w1;
635 __le32 w2;
636 __le32 w3;
637 __le32 w4;
638 __le32 w5;
639 __le32 w6;
640 __le32 w7;
641 __le32 w8;
642 __le32 w9;
643 __le32 w10;
644 __le32 w11;
645 struct rtw89_fw_hdr_section_v1 sections[];
646 } __packed;
647
648 #define FW_HDR_V1_W1_MAJOR_VERSION GENMASK(7, 0)
649 #define FW_HDR_V1_W1_MINOR_VERSION GENMASK(15, 8)
650 #define FW_HDR_V1_W1_SUBVERSION GENMASK(23, 16)
651 #define FW_HDR_V1_W1_SUBINDEX GENMASK(31, 24)
652 #define FW_HDR_V1_W2_COMMITID GENMASK(31, 0)
653 #define FW_HDR_V1_W3_CMD_VERSERION GENMASK(23, 16)
654 #define FW_HDR_V1_W3_HDR_VER GENMASK(31, 24)
655 #define FW_HDR_V1_W4_MONTH GENMASK(7, 0)
656 #define FW_HDR_V1_W4_DATE GENMASK(15, 8)
657 #define FW_HDR_V1_W4_HOUR GENMASK(23, 16)
658 #define FW_HDR_V1_W4_MIN GENMASK(31, 24)
659 #define FW_HDR_V1_W5_YEAR GENMASK(15, 0)
660 #define FW_HDR_V1_W5_HDR_SIZE GENMASK(31, 16)
661 #define FW_HDR_V1_W6_SEC_NUM GENMASK(15, 8)
662 #define FW_HDR_V1_W6_DSP_CHKSUM BIT(24)
663 #define FW_HDR_V1_W7_PART_SIZE GENMASK(15, 0)
664 #define FW_HDR_V1_W7_DYN_HDR BIT(16)
665 #define FW_HDR_V1_W7_IDMEM_SHARE_MODE GENMASK(21, 18)
666
667 enum rtw89_fw_mss_pool_rmp_tbl_type {
668 MSS_POOL_RMP_TBL_BITMASK = 0x0,
669 MSS_POOL_RMP_TBL_RECORD = 0x1,
670 };
671
672 #define FWDL_MSS_POOL_DEFKEYSETS_SIZE 8
673
674 struct rtw89_fw_mss_pool_hdr {
675 u8 signature[8]; /* equal to mss_signature[] */
676 __le32 rmp_tbl_offset;
677 __le32 key_raw_offset;
678 u8 defen;
679 u8 rsvd[3];
680 u8 rmpfmt; /* enum rtw89_fw_mss_pool_rmp_tbl_type */
681 u8 mssdev_max;
682 __le16 keypair_num;
683 __le16 msscust_max;
684 __le16 msskey_num_max;
685 __le32 rsvd3;
686 u8 rmp_tbl[];
687 } __packed;
688
689 union rtw89_fw_section_mssc_content {
690 struct {
691 u8 pad[0x20];
692 u8 bit_in_chip_list;
693 u8 ver;
694 } __packed blacklist;
695 struct {
696 u8 pad[58];
697 __le32 v;
698 } __packed sb_sel_ver;
699 struct {
700 u8 pad[60];
701 __le16 v;
702 } __packed key_sign_len;
703 } __packed;
704
705 struct rtw89_fw_blacklist {
706 u8 ver;
707 u8 list[32];
708 };
709
710 extern const struct rtw89_fw_blacklist rtw89_fw_blacklist_default;
711
SET_CTRL_INFO_MACID(void * table,u32 val)712 static inline void SET_CTRL_INFO_MACID(void *table, u32 val)
713 {
714 le32p_replace_bits((__le32 *)(table) + 0, val, GENMASK(6, 0));
715 }
716
SET_CTRL_INFO_OPERATION(void * table,u32 val)717 static inline void SET_CTRL_INFO_OPERATION(void *table, u32 val)
718 {
719 le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7));
720 }
721 #define SET_CMC_TBL_MASK_DATARATE GENMASK(8, 0)
SET_CMC_TBL_DATARATE(void * table,u32 val)722 static inline void SET_CMC_TBL_DATARATE(void *table, u32 val)
723 {
724 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(8, 0));
725 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATARATE,
726 GENMASK(8, 0));
727 }
728 #define SET_CMC_TBL_MASK_FORCE_TXOP BIT(0)
SET_CMC_TBL_FORCE_TXOP(void * table,u32 val)729 static inline void SET_CMC_TBL_FORCE_TXOP(void *table, u32 val)
730 {
731 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(9));
732 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_FORCE_TXOP,
733 BIT(9));
734 }
735 #define SET_CMC_TBL_MASK_DATA_BW GENMASK(1, 0)
SET_CMC_TBL_DATA_BW(void * table,u32 val)736 static inline void SET_CMC_TBL_DATA_BW(void *table, u32 val)
737 {
738 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(11, 10));
739 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_BW,
740 GENMASK(11, 10));
741 }
742 #define SET_CMC_TBL_MASK_DATA_GI_LTF GENMASK(2, 0)
SET_CMC_TBL_DATA_GI_LTF(void * table,u32 val)743 static inline void SET_CMC_TBL_DATA_GI_LTF(void *table, u32 val)
744 {
745 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(14, 12));
746 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_GI_LTF,
747 GENMASK(14, 12));
748 }
749 #define SET_CMC_TBL_MASK_DARF_TC_INDEX BIT(0)
SET_CMC_TBL_DARF_TC_INDEX(void * table,u32 val)750 static inline void SET_CMC_TBL_DARF_TC_INDEX(void *table, u32 val)
751 {
752 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(15));
753 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DARF_TC_INDEX,
754 BIT(15));
755 }
756 #define SET_CMC_TBL_MASK_ARFR_CTRL GENMASK(3, 0)
SET_CMC_TBL_ARFR_CTRL(void * table,u32 val)757 static inline void SET_CMC_TBL_ARFR_CTRL(void *table, u32 val)
758 {
759 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(19, 16));
760 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ARFR_CTRL,
761 GENMASK(19, 16));
762 }
763 #define SET_CMC_TBL_MASK_ACQ_RPT_EN BIT(0)
SET_CMC_TBL_ACQ_RPT_EN(void * table,u32 val)764 static inline void SET_CMC_TBL_ACQ_RPT_EN(void *table, u32 val)
765 {
766 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(20));
767 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ACQ_RPT_EN,
768 BIT(20));
769 }
770 #define SET_CMC_TBL_MASK_MGQ_RPT_EN BIT(0)
SET_CMC_TBL_MGQ_RPT_EN(void * table,u32 val)771 static inline void SET_CMC_TBL_MGQ_RPT_EN(void *table, u32 val)
772 {
773 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(21));
774 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_MGQ_RPT_EN,
775 BIT(21));
776 }
777 #define SET_CMC_TBL_MASK_ULQ_RPT_EN BIT(0)
SET_CMC_TBL_ULQ_RPT_EN(void * table,u32 val)778 static inline void SET_CMC_TBL_ULQ_RPT_EN(void *table, u32 val)
779 {
780 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(22));
781 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ULQ_RPT_EN,
782 BIT(22));
783 }
784 #define SET_CMC_TBL_MASK_TWTQ_RPT_EN BIT(0)
SET_CMC_TBL_TWTQ_RPT_EN(void * table,u32 val)785 static inline void SET_CMC_TBL_TWTQ_RPT_EN(void *table, u32 val)
786 {
787 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(23));
788 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TWTQ_RPT_EN,
789 BIT(23));
790 }
791 #define SET_CMC_TBL_MASK_DISRTSFB BIT(0)
SET_CMC_TBL_DISRTSFB(void * table,u32 val)792 static inline void SET_CMC_TBL_DISRTSFB(void *table, u32 val)
793 {
794 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(25));
795 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISRTSFB,
796 BIT(25));
797 }
798 #define SET_CMC_TBL_MASK_DISDATAFB BIT(0)
SET_CMC_TBL_DISDATAFB(void * table,u32 val)799 static inline void SET_CMC_TBL_DISDATAFB(void *table, u32 val)
800 {
801 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(26));
802 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISDATAFB,
803 BIT(26));
804 }
805 #define SET_CMC_TBL_MASK_TRYRATE BIT(0)
SET_CMC_TBL_TRYRATE(void * table,u32 val)806 static inline void SET_CMC_TBL_TRYRATE(void *table, u32 val)
807 {
808 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(27));
809 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TRYRATE,
810 BIT(27));
811 }
812 #define SET_CMC_TBL_MASK_AMPDU_DENSITY GENMASK(3, 0)
SET_CMC_TBL_AMPDU_DENSITY(void * table,u32 val)813 static inline void SET_CMC_TBL_AMPDU_DENSITY(void *table, u32 val)
814 {
815 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(31, 28));
816 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_AMPDU_DENSITY,
817 GENMASK(31, 28));
818 }
819 #define SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE GENMASK(8, 0)
SET_CMC_TBL_DATA_RTY_LOWEST_RATE(void * table,u32 val)820 static inline void SET_CMC_TBL_DATA_RTY_LOWEST_RATE(void *table, u32 val)
821 {
822 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(8, 0));
823 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE,
824 GENMASK(8, 0));
825 }
826 #define SET_CMC_TBL_MASK_AMPDU_TIME_SEL BIT(0)
SET_CMC_TBL_AMPDU_TIME_SEL(void * table,u32 val)827 static inline void SET_CMC_TBL_AMPDU_TIME_SEL(void *table, u32 val)
828 {
829 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(9));
830 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_TIME_SEL,
831 BIT(9));
832 }
833 #define SET_CMC_TBL_MASK_AMPDU_LEN_SEL BIT(0)
SET_CMC_TBL_AMPDU_LEN_SEL(void * table,u32 val)834 static inline void SET_CMC_TBL_AMPDU_LEN_SEL(void *table, u32 val)
835 {
836 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(10));
837 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_LEN_SEL,
838 BIT(10));
839 }
840 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL BIT(0)
SET_CMC_TBL_RTS_TXCNT_LMT_SEL(void * table,u32 val)841 static inline void SET_CMC_TBL_RTS_TXCNT_LMT_SEL(void *table, u32 val)
842 {
843 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(11));
844 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL,
845 BIT(11));
846 }
847 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT GENMASK(3, 0)
SET_CMC_TBL_RTS_TXCNT_LMT(void * table,u32 val)848 static inline void SET_CMC_TBL_RTS_TXCNT_LMT(void *table, u32 val)
849 {
850 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(15, 12));
851 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT,
852 GENMASK(15, 12));
853 }
854 #define SET_CMC_TBL_MASK_RTSRATE GENMASK(8, 0)
SET_CMC_TBL_RTSRATE(void * table,u32 val)855 static inline void SET_CMC_TBL_RTSRATE(void *table, u32 val)
856 {
857 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(24, 16));
858 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTSRATE,
859 GENMASK(24, 16));
860 }
861 #define SET_CMC_TBL_MASK_VCS_STBC BIT(0)
SET_CMC_TBL_VCS_STBC(void * table,u32 val)862 static inline void SET_CMC_TBL_VCS_STBC(void *table, u32 val)
863 {
864 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(27));
865 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_VCS_STBC,
866 BIT(27));
867 }
868 #define SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE GENMASK(3, 0)
SET_CMC_TBL_RTS_RTY_LOWEST_RATE(void * table,u32 val)869 static inline void SET_CMC_TBL_RTS_RTY_LOWEST_RATE(void *table, u32 val)
870 {
871 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(31, 28));
872 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE,
873 GENMASK(31, 28));
874 }
875 #define SET_CMC_TBL_MASK_DATA_TX_CNT_LMT GENMASK(5, 0)
SET_CMC_TBL_DATA_TX_CNT_LMT(void * table,u32 val)876 static inline void SET_CMC_TBL_DATA_TX_CNT_LMT(void *table, u32 val)
877 {
878 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(5, 0));
879 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TX_CNT_LMT,
880 GENMASK(5, 0));
881 }
882 #define SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL BIT(0)
SET_CMC_TBL_DATA_TXCNT_LMT_SEL(void * table,u32 val)883 static inline void SET_CMC_TBL_DATA_TXCNT_LMT_SEL(void *table, u32 val)
884 {
885 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(6));
886 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL,
887 BIT(6));
888 }
889 #define SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL BIT(0)
SET_CMC_TBL_MAX_AGG_NUM_SEL(void * table,u32 val)890 static inline void SET_CMC_TBL_MAX_AGG_NUM_SEL(void *table, u32 val)
891 {
892 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(7));
893 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL,
894 BIT(7));
895 }
896 #define SET_CMC_TBL_MASK_RTS_EN BIT(0)
SET_CMC_TBL_RTS_EN(void * table,u32 val)897 static inline void SET_CMC_TBL_RTS_EN(void *table, u32 val)
898 {
899 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(8));
900 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_EN,
901 BIT(8));
902 }
903 #define SET_CMC_TBL_MASK_CTS2SELF_EN BIT(0)
SET_CMC_TBL_CTS2SELF_EN(void * table,u32 val)904 static inline void SET_CMC_TBL_CTS2SELF_EN(void *table, u32 val)
905 {
906 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(9));
907 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CTS2SELF_EN,
908 BIT(9));
909 }
910 #define SET_CMC_TBL_MASK_CCA_RTS GENMASK(1, 0)
SET_CMC_TBL_CCA_RTS(void * table,u32 val)911 static inline void SET_CMC_TBL_CCA_RTS(void *table, u32 val)
912 {
913 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(11, 10));
914 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CCA_RTS,
915 GENMASK(11, 10));
916 }
917 #define SET_CMC_TBL_MASK_HW_RTS_EN BIT(0)
SET_CMC_TBL_HW_RTS_EN(void * table,u32 val)918 static inline void SET_CMC_TBL_HW_RTS_EN(void *table, u32 val)
919 {
920 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(12));
921 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_HW_RTS_EN,
922 BIT(12));
923 }
924 #define SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE GENMASK(1, 0)
SET_CMC_TBL_RTS_DROP_DATA_MODE(void * table,u32 val)925 static inline void SET_CMC_TBL_RTS_DROP_DATA_MODE(void *table, u32 val)
926 {
927 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(14, 13));
928 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE,
929 GENMASK(14, 13));
930 }
931 #define SET_CMC_TBL_MASK_AMPDU_MAX_LEN GENMASK(10, 0)
SET_CMC_TBL_AMPDU_MAX_LEN(void * table,u32 val)932 static inline void SET_CMC_TBL_AMPDU_MAX_LEN(void *table, u32 val)
933 {
934 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(26, 16));
935 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_LEN,
936 GENMASK(26, 16));
937 }
938 #define SET_CMC_TBL_MASK_UL_MU_DIS BIT(0)
SET_CMC_TBL_UL_MU_DIS(void * table,u32 val)939 static inline void SET_CMC_TBL_UL_MU_DIS(void *table, u32 val)
940 {
941 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(27));
942 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_UL_MU_DIS,
943 BIT(27));
944 }
945 #define SET_CMC_TBL_MASK_AMPDU_MAX_TIME GENMASK(3, 0)
SET_CMC_TBL_AMPDU_MAX_TIME(void * table,u32 val)946 static inline void SET_CMC_TBL_AMPDU_MAX_TIME(void *table, u32 val)
947 {
948 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(31, 28));
949 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_TIME,
950 GENMASK(31, 28));
951 }
952 #define SET_CMC_TBL_MASK_MAX_AGG_NUM GENMASK(7, 0)
SET_CMC_TBL_MAX_AGG_NUM(void * table,u32 val)953 static inline void SET_CMC_TBL_MAX_AGG_NUM(void *table, u32 val)
954 {
955 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(7, 0));
956 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_MAX_AGG_NUM,
957 GENMASK(7, 0));
958 }
959 #define SET_CMC_TBL_MASK_BA_BMAP GENMASK(1, 0)
SET_CMC_TBL_BA_BMAP(void * table,u32 val)960 static inline void SET_CMC_TBL_BA_BMAP(void *table, u32 val)
961 {
962 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(9, 8));
963 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BA_BMAP,
964 GENMASK(9, 8));
965 }
966 #define SET_CMC_TBL_MASK_VO_LFTIME_SEL GENMASK(2, 0)
SET_CMC_TBL_VO_LFTIME_SEL(void * table,u32 val)967 static inline void SET_CMC_TBL_VO_LFTIME_SEL(void *table, u32 val)
968 {
969 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(18, 16));
970 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VO_LFTIME_SEL,
971 GENMASK(18, 16));
972 }
973 #define SET_CMC_TBL_MASK_VI_LFTIME_SEL GENMASK(2, 0)
SET_CMC_TBL_VI_LFTIME_SEL(void * table,u32 val)974 static inline void SET_CMC_TBL_VI_LFTIME_SEL(void *table, u32 val)
975 {
976 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(21, 19));
977 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VI_LFTIME_SEL,
978 GENMASK(21, 19));
979 }
980 #define SET_CMC_TBL_MASK_BE_LFTIME_SEL GENMASK(2, 0)
SET_CMC_TBL_BE_LFTIME_SEL(void * table,u32 val)981 static inline void SET_CMC_TBL_BE_LFTIME_SEL(void *table, u32 val)
982 {
983 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(24, 22));
984 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BE_LFTIME_SEL,
985 GENMASK(24, 22));
986 }
987 #define SET_CMC_TBL_MASK_BK_LFTIME_SEL GENMASK(2, 0)
SET_CMC_TBL_BK_LFTIME_SEL(void * table,u32 val)988 static inline void SET_CMC_TBL_BK_LFTIME_SEL(void *table, u32 val)
989 {
990 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(27, 25));
991 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BK_LFTIME_SEL,
992 GENMASK(27, 25));
993 }
994 #define SET_CMC_TBL_MASK_SECTYPE GENMASK(3, 0)
SET_CMC_TBL_SECTYPE(void * table,u32 val)995 static inline void SET_CMC_TBL_SECTYPE(void *table, u32 val)
996 {
997 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(31, 28));
998 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_SECTYPE,
999 GENMASK(31, 28));
1000 }
1001 #define SET_CMC_TBL_MASK_MULTI_PORT_ID GENMASK(2, 0)
SET_CMC_TBL_MULTI_PORT_ID(void * table,u32 val)1002 static inline void SET_CMC_TBL_MULTI_PORT_ID(void *table, u32 val)
1003 {
1004 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(2, 0));
1005 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MULTI_PORT_ID,
1006 GENMASK(2, 0));
1007 }
1008 #define SET_CMC_TBL_MASK_BMC BIT(0)
SET_CMC_TBL_BMC(void * table,u32 val)1009 static inline void SET_CMC_TBL_BMC(void *table, u32 val)
1010 {
1011 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(3));
1012 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_BMC,
1013 BIT(3));
1014 }
1015 #define SET_CMC_TBL_MASK_MBSSID GENMASK(3, 0)
SET_CMC_TBL_MBSSID(void * table,u32 val)1016 static inline void SET_CMC_TBL_MBSSID(void *table, u32 val)
1017 {
1018 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(7, 4));
1019 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MBSSID,
1020 GENMASK(7, 4));
1021 }
1022 #define SET_CMC_TBL_MASK_NAVUSEHDR BIT(0)
SET_CMC_TBL_NAVUSEHDR(void * table,u32 val)1023 static inline void SET_CMC_TBL_NAVUSEHDR(void *table, u32 val)
1024 {
1025 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(8));
1026 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_NAVUSEHDR,
1027 BIT(8));
1028 }
1029 #define SET_CMC_TBL_MASK_TXPWR_MODE GENMASK(2, 0)
SET_CMC_TBL_TXPWR_MODE(void * table,u32 val)1030 static inline void SET_CMC_TBL_TXPWR_MODE(void *table, u32 val)
1031 {
1032 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(11, 9));
1033 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_TXPWR_MODE,
1034 GENMASK(11, 9));
1035 }
1036 #define SET_CMC_TBL_MASK_DATA_DCM BIT(0)
SET_CMC_TBL_DATA_DCM(void * table,u32 val)1037 static inline void SET_CMC_TBL_DATA_DCM(void *table, u32 val)
1038 {
1039 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(12));
1040 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_DCM,
1041 BIT(12));
1042 }
1043 #define SET_CMC_TBL_MASK_DATA_ER BIT(0)
SET_CMC_TBL_DATA_ER(void * table,u32 val)1044 static inline void SET_CMC_TBL_DATA_ER(void *table, u32 val)
1045 {
1046 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(13));
1047 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_ER,
1048 BIT(13));
1049 }
1050 #define SET_CMC_TBL_MASK_DATA_LDPC BIT(0)
SET_CMC_TBL_DATA_LDPC(void * table,u32 val)1051 static inline void SET_CMC_TBL_DATA_LDPC(void *table, u32 val)
1052 {
1053 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(14));
1054 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_LDPC,
1055 BIT(14));
1056 }
1057 #define SET_CMC_TBL_MASK_DATA_STBC BIT(0)
SET_CMC_TBL_DATA_STBC(void * table,u32 val)1058 static inline void SET_CMC_TBL_DATA_STBC(void *table, u32 val)
1059 {
1060 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(15));
1061 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_STBC,
1062 BIT(15));
1063 }
1064 #define SET_CMC_TBL_MASK_A_CTRL_BQR BIT(0)
SET_CMC_TBL_A_CTRL_BQR(void * table,u32 val)1065 static inline void SET_CMC_TBL_A_CTRL_BQR(void *table, u32 val)
1066 {
1067 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(16));
1068 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BQR,
1069 BIT(16));
1070 }
1071 #define SET_CMC_TBL_MASK_A_CTRL_UPH BIT(0)
SET_CMC_TBL_A_CTRL_UPH(void * table,u32 val)1072 static inline void SET_CMC_TBL_A_CTRL_UPH(void *table, u32 val)
1073 {
1074 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(17));
1075 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_UPH,
1076 BIT(17));
1077 }
1078 #define SET_CMC_TBL_MASK_A_CTRL_BSR BIT(0)
SET_CMC_TBL_A_CTRL_BSR(void * table,u32 val)1079 static inline void SET_CMC_TBL_A_CTRL_BSR(void *table, u32 val)
1080 {
1081 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(18));
1082 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BSR,
1083 BIT(18));
1084 }
1085 #define SET_CMC_TBL_MASK_A_CTRL_CAS BIT(0)
SET_CMC_TBL_A_CTRL_CAS(void * table,u32 val)1086 static inline void SET_CMC_TBL_A_CTRL_CAS(void *table, u32 val)
1087 {
1088 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(19));
1089 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_CAS,
1090 BIT(19));
1091 }
1092 #define SET_CMC_TBL_MASK_DATA_BW_ER BIT(0)
SET_CMC_TBL_DATA_BW_ER(void * table,u32 val)1093 static inline void SET_CMC_TBL_DATA_BW_ER(void *table, u32 val)
1094 {
1095 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(20));
1096 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_BW_ER,
1097 BIT(20));
1098 }
1099 #define SET_CMC_TBL_MASK_LSIG_TXOP_EN BIT(0)
SET_CMC_TBL_LSIG_TXOP_EN(void * table,u32 val)1100 static inline void SET_CMC_TBL_LSIG_TXOP_EN(void *table, u32 val)
1101 {
1102 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(21));
1103 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_LSIG_TXOP_EN,
1104 BIT(21));
1105 }
1106 #define SET_CMC_TBL_MASK_CTRL_CNT_VLD BIT(0)
SET_CMC_TBL_CTRL_CNT_VLD(void * table,u32 val)1107 static inline void SET_CMC_TBL_CTRL_CNT_VLD(void *table, u32 val)
1108 {
1109 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(27));
1110 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT_VLD,
1111 BIT(27));
1112 }
1113 #define SET_CMC_TBL_MASK_CTRL_CNT GENMASK(3, 0)
SET_CMC_TBL_CTRL_CNT(void * table,u32 val)1114 static inline void SET_CMC_TBL_CTRL_CNT(void *table, u32 val)
1115 {
1116 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(31, 28));
1117 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT,
1118 GENMASK(31, 28));
1119 }
1120 #define SET_CMC_TBL_MASK_RESP_REF_RATE GENMASK(8, 0)
SET_CMC_TBL_RESP_REF_RATE(void * table,u32 val)1121 static inline void SET_CMC_TBL_RESP_REF_RATE(void *table, u32 val)
1122 {
1123 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(8, 0));
1124 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_RESP_REF_RATE,
1125 GENMASK(8, 0));
1126 }
1127 #define SET_CMC_TBL_MASK_ALL_ACK_SUPPORT BIT(0)
SET_CMC_TBL_ALL_ACK_SUPPORT(void * table,u32 val)1128 static inline void SET_CMC_TBL_ALL_ACK_SUPPORT(void *table, u32 val)
1129 {
1130 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(12));
1131 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ALL_ACK_SUPPORT,
1132 BIT(12));
1133 }
1134 #define SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT BIT(0)
SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(void * table,u32 val)1135 static inline void SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(void *table, u32 val)
1136 {
1137 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(13));
1138 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT,
1139 BIT(13));
1140 }
1141 #define SET_CMC_TBL_MASK_NTX_PATH_EN GENMASK(3, 0)
SET_CMC_TBL_NTX_PATH_EN(void * table,u32 val)1142 static inline void SET_CMC_TBL_NTX_PATH_EN(void *table, u32 val)
1143 {
1144 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(19, 16));
1145 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_NTX_PATH_EN,
1146 GENMASK(19, 16));
1147 }
1148 #define SET_CMC_TBL_MASK_PATH_MAP_A GENMASK(1, 0)
SET_CMC_TBL_PATH_MAP_A(void * table,u32 val)1149 static inline void SET_CMC_TBL_PATH_MAP_A(void *table, u32 val)
1150 {
1151 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(21, 20));
1152 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_A,
1153 GENMASK(21, 20));
1154 }
1155 #define SET_CMC_TBL_MASK_PATH_MAP_B GENMASK(1, 0)
SET_CMC_TBL_PATH_MAP_B(void * table,u32 val)1156 static inline void SET_CMC_TBL_PATH_MAP_B(void *table, u32 val)
1157 {
1158 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(23, 22));
1159 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_B,
1160 GENMASK(23, 22));
1161 }
1162 #define SET_CMC_TBL_MASK_PATH_MAP_C GENMASK(1, 0)
SET_CMC_TBL_PATH_MAP_C(void * table,u32 val)1163 static inline void SET_CMC_TBL_PATH_MAP_C(void *table, u32 val)
1164 {
1165 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(25, 24));
1166 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_C,
1167 GENMASK(25, 24));
1168 }
1169 #define SET_CMC_TBL_MASK_PATH_MAP_D GENMASK(1, 0)
SET_CMC_TBL_PATH_MAP_D(void * table,u32 val)1170 static inline void SET_CMC_TBL_PATH_MAP_D(void *table, u32 val)
1171 {
1172 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(27, 26));
1173 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_D,
1174 GENMASK(27, 26));
1175 }
1176 #define SET_CMC_TBL_MASK_ANTSEL_A BIT(0)
SET_CMC_TBL_ANTSEL_A(void * table,u32 val)1177 static inline void SET_CMC_TBL_ANTSEL_A(void *table, u32 val)
1178 {
1179 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(28));
1180 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_A,
1181 BIT(28));
1182 }
1183 #define SET_CMC_TBL_MASK_ANTSEL_B BIT(0)
SET_CMC_TBL_ANTSEL_B(void * table,u32 val)1184 static inline void SET_CMC_TBL_ANTSEL_B(void *table, u32 val)
1185 {
1186 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(29));
1187 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_B,
1188 BIT(29));
1189 }
1190 #define SET_CMC_TBL_MASK_ANTSEL_C BIT(0)
SET_CMC_TBL_ANTSEL_C(void * table,u32 val)1191 static inline void SET_CMC_TBL_ANTSEL_C(void *table, u32 val)
1192 {
1193 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(30));
1194 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_C,
1195 BIT(30));
1196 }
1197 #define SET_CMC_TBL_MASK_ANTSEL_D BIT(0)
SET_CMC_TBL_ANTSEL_D(void * table,u32 val)1198 static inline void SET_CMC_TBL_ANTSEL_D(void *table, u32 val)
1199 {
1200 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(31));
1201 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_D,
1202 BIT(31));
1203 }
1204
1205 #define SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING GENMASK(1, 0)
SET_CMC_TBL_NOMINAL_PKT_PADDING_V1(void * table,u32 val)1206 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING_V1(void *table, u32 val)
1207 {
1208 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(1, 0));
1209 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1210 GENMASK(1, 0));
1211 }
1212
SET_CMC_TBL_NOMINAL_PKT_PADDING40_V1(void * table,u32 val)1213 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40_V1(void *table, u32 val)
1214 {
1215 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(3, 2));
1216 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1217 GENMASK(3, 2));
1218 }
1219
SET_CMC_TBL_NOMINAL_PKT_PADDING80_V1(void * table,u32 val)1220 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80_V1(void *table, u32 val)
1221 {
1222 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(5, 4));
1223 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1224 GENMASK(5, 4));
1225 }
1226
SET_CMC_TBL_NOMINAL_PKT_PADDING160_V1(void * table,u32 val)1227 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160_V1(void *table, u32 val)
1228 {
1229 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 6));
1230 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1231 GENMASK(7, 6));
1232 }
1233
1234 #define SET_CMC_TBL_MASK_ADDR_CAM_INDEX GENMASK(7, 0)
SET_CMC_TBL_ADDR_CAM_INDEX(void * table,u32 val)1235 static inline void SET_CMC_TBL_ADDR_CAM_INDEX(void *table, u32 val)
1236 {
1237 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 0));
1238 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ADDR_CAM_INDEX,
1239 GENMASK(7, 0));
1240 }
1241 #define SET_CMC_TBL_MASK_PAID GENMASK(8, 0)
SET_CMC_TBL_PAID(void * table,u32 val)1242 static inline void SET_CMC_TBL_PAID(void *table, u32 val)
1243 {
1244 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(16, 8));
1245 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_PAID,
1246 GENMASK(16, 8));
1247 }
1248 #define SET_CMC_TBL_MASK_ULDL BIT(0)
SET_CMC_TBL_ULDL(void * table,u32 val)1249 static inline void SET_CMC_TBL_ULDL(void *table, u32 val)
1250 {
1251 le32p_replace_bits((__le32 *)(table) + 7, val, BIT(17));
1252 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ULDL,
1253 BIT(17));
1254 }
1255 #define SET_CMC_TBL_MASK_DOPPLER_CTRL GENMASK(1, 0)
SET_CMC_TBL_DOPPLER_CTRL(void * table,u32 val)1256 static inline void SET_CMC_TBL_DOPPLER_CTRL(void *table, u32 val)
1257 {
1258 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(19, 18));
1259 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_DOPPLER_CTRL,
1260 GENMASK(19, 18));
1261 }
SET_CMC_TBL_NOMINAL_PKT_PADDING(void * table,u32 val)1262 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING(void *table, u32 val)
1263 {
1264 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(21, 20));
1265 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1266 GENMASK(21, 20));
1267 }
1268
SET_CMC_TBL_NOMINAL_PKT_PADDING40(void * table,u32 val)1269 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40(void *table, u32 val)
1270 {
1271 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(23, 22));
1272 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1273 GENMASK(23, 22));
1274 }
1275 #define SET_CMC_TBL_MASK_TXPWR_TOLERENCE GENMASK(3, 0)
SET_CMC_TBL_TXPWR_TOLERENCE(void * table,u32 val)1276 static inline void SET_CMC_TBL_TXPWR_TOLERENCE(void *table, u32 val)
1277 {
1278 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(27, 24));
1279 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_TXPWR_TOLERENCE,
1280 GENMASK(27, 24));
1281 }
1282
SET_CMC_TBL_NOMINAL_PKT_PADDING80(void * table,u32 val)1283 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80(void *table, u32 val)
1284 {
1285 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(31, 30));
1286 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1287 GENMASK(31, 30));
1288 }
1289 #define SET_CMC_TBL_MASK_NC GENMASK(2, 0)
SET_CMC_TBL_NC(void * table,u32 val)1290 static inline void SET_CMC_TBL_NC(void *table, u32 val)
1291 {
1292 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(2, 0));
1293 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NC,
1294 GENMASK(2, 0));
1295 }
1296 #define SET_CMC_TBL_MASK_NR GENMASK(2, 0)
SET_CMC_TBL_NR(void * table,u32 val)1297 static inline void SET_CMC_TBL_NR(void *table, u32 val)
1298 {
1299 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(5, 3));
1300 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NR,
1301 GENMASK(5, 3));
1302 }
1303 #define SET_CMC_TBL_MASK_NG GENMASK(1, 0)
SET_CMC_TBL_NG(void * table,u32 val)1304 static inline void SET_CMC_TBL_NG(void *table, u32 val)
1305 {
1306 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(7, 6));
1307 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NG,
1308 GENMASK(7, 6));
1309 }
1310 #define SET_CMC_TBL_MASK_CB GENMASK(1, 0)
SET_CMC_TBL_CB(void * table,u32 val)1311 static inline void SET_CMC_TBL_CB(void *table, u32 val)
1312 {
1313 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(9, 8));
1314 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CB,
1315 GENMASK(9, 8));
1316 }
1317 #define SET_CMC_TBL_MASK_CS GENMASK(1, 0)
SET_CMC_TBL_CS(void * table,u32 val)1318 static inline void SET_CMC_TBL_CS(void *table, u32 val)
1319 {
1320 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(11, 10));
1321 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CS,
1322 GENMASK(11, 10));
1323 }
1324 #define SET_CMC_TBL_MASK_CSI_TXBF_EN BIT(0)
SET_CMC_TBL_CSI_TXBF_EN(void * table,u32 val)1325 static inline void SET_CMC_TBL_CSI_TXBF_EN(void *table, u32 val)
1326 {
1327 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(12));
1328 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_TXBF_EN,
1329 BIT(12));
1330 }
1331 #define SET_CMC_TBL_MASK_CSI_STBC_EN BIT(0)
SET_CMC_TBL_CSI_STBC_EN(void * table,u32 val)1332 static inline void SET_CMC_TBL_CSI_STBC_EN(void *table, u32 val)
1333 {
1334 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(13));
1335 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_STBC_EN,
1336 BIT(13));
1337 }
1338 #define SET_CMC_TBL_MASK_CSI_LDPC_EN BIT(0)
SET_CMC_TBL_CSI_LDPC_EN(void * table,u32 val)1339 static inline void SET_CMC_TBL_CSI_LDPC_EN(void *table, u32 val)
1340 {
1341 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(14));
1342 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_LDPC_EN,
1343 BIT(14));
1344 }
1345 #define SET_CMC_TBL_MASK_CSI_PARA_EN BIT(0)
SET_CMC_TBL_CSI_PARA_EN(void * table,u32 val)1346 static inline void SET_CMC_TBL_CSI_PARA_EN(void *table, u32 val)
1347 {
1348 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(15));
1349 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_PARA_EN,
1350 BIT(15));
1351 }
1352 #define SET_CMC_TBL_MASK_CSI_FIX_RATE GENMASK(8, 0)
SET_CMC_TBL_CSI_FIX_RATE(void * table,u32 val)1353 static inline void SET_CMC_TBL_CSI_FIX_RATE(void *table, u32 val)
1354 {
1355 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(24, 16));
1356 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_FIX_RATE,
1357 GENMASK(24, 16));
1358 }
1359 #define SET_CMC_TBL_MASK_CSI_GI_LTF GENMASK(2, 0)
SET_CMC_TBL_CSI_GI_LTF(void * table,u32 val)1360 static inline void SET_CMC_TBL_CSI_GI_LTF(void *table, u32 val)
1361 {
1362 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(27, 25));
1363 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_GI_LTF,
1364 GENMASK(27, 25));
1365 }
1366
SET_CMC_TBL_NOMINAL_PKT_PADDING160(void * table,u32 val)1367 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160(void *table, u32 val)
1368 {
1369 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(29, 28));
1370 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1371 GENMASK(29, 28));
1372 }
1373
1374 #define SET_CMC_TBL_MASK_CSI_BW GENMASK(1, 0)
SET_CMC_TBL_CSI_BW(void * table,u32 val)1375 static inline void SET_CMC_TBL_CSI_BW(void *table, u32 val)
1376 {
1377 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(31, 30));
1378 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_BW,
1379 GENMASK(31, 30));
1380 }
1381
1382 struct rtw89_h2c_cctlinfo_ud_g7 {
1383 __le32 c0;
1384 __le32 w0;
1385 __le32 w1;
1386 __le32 w2;
1387 __le32 w3;
1388 __le32 w4;
1389 __le32 w5;
1390 __le32 w6;
1391 __le32 w7;
1392 __le32 w8;
1393 __le32 w9;
1394 __le32 w10;
1395 __le32 w11;
1396 __le32 w12;
1397 __le32 w13;
1398 __le32 w14;
1399 __le32 w15;
1400 __le32 m0;
1401 __le32 m1;
1402 __le32 m2;
1403 __le32 m3;
1404 __le32 m4;
1405 __le32 m5;
1406 __le32 m6;
1407 __le32 m7;
1408 __le32 m8;
1409 __le32 m9;
1410 __le32 m10;
1411 __le32 m11;
1412 __le32 m12;
1413 __le32 m13;
1414 __le32 m14;
1415 __le32 m15;
1416 } __packed;
1417
1418 #define CCTLINFO_G7_C0_MACID GENMASK(6, 0)
1419 #define CCTLINFO_G7_C0_OP BIT(7)
1420
1421 #define CCTLINFO_G7_W0_DATARATE GENMASK(11, 0)
1422 #define CCTLINFO_G7_W0_DATA_GI_LTF GENMASK(14, 12)
1423 #define CCTLINFO_G7_W0_TRYRATE BIT(15)
1424 #define CCTLINFO_G7_W0_ARFR_CTRL GENMASK(17, 16)
1425 #define CCTLINFO_G7_W0_DIS_HE1SS_STBC BIT(18)
1426 #define CCTLINFO_G7_W0_ACQ_RPT_EN BIT(20)
1427 #define CCTLINFO_G7_W0_MGQ_RPT_EN BIT(21)
1428 #define CCTLINFO_G7_W0_ULQ_RPT_EN BIT(22)
1429 #define CCTLINFO_G7_W0_TWTQ_RPT_EN BIT(23)
1430 #define CCTLINFO_G7_W0_FORCE_TXOP BIT(24)
1431 #define CCTLINFO_G7_W0_DISRTSFB BIT(25)
1432 #define CCTLINFO_G7_W0_DISDATAFB BIT(26)
1433 #define CCTLINFO_G7_W0_NSTR_EN BIT(27)
1434 #define CCTLINFO_G7_W0_AMPDU_DENSITY GENMASK(31, 28)
1435 #define CCTLINFO_G7_W0_ALL (GENMASK(31, 20) | GENMASK(18, 0))
1436 #define CCTLINFO_G7_W1_DATA_RTY_LOWEST_RATE GENMASK(11, 0)
1437 #define CCTLINFO_G7_W1_RTS_TXCNT_LMT GENMASK(15, 12)
1438 #define CCTLINFO_G7_W1_RTSRATE GENMASK(27, 16)
1439 #define CCTLINFO_G7_W1_RTS_RTY_LOWEST_RATE GENMASK(31, 28)
1440 #define CCTLINFO_G7_W1_ALL GENMASK(31, 0)
1441 #define CCTLINFO_G7_W2_DATA_TX_CNT_LMT GENMASK(5, 0)
1442 #define CCTLINFO_G7_W2_DATA_TXCNT_LMT_SEL BIT(6)
1443 #define CCTLINFO_G7_W2_MAX_AGG_NUM_SEL BIT(7)
1444 #define CCTLINFO_G7_W2_RTS_EN BIT(8)
1445 #define CCTLINFO_G7_W2_CTS2SELF_EN BIT(9)
1446 #define CCTLINFO_G7_W2_CCA_RTS GENMASK(11, 10)
1447 #define CCTLINFO_G7_W2_HW_RTS_EN BIT(12)
1448 #define CCTLINFO_G7_W2_RTS_DROP_DATA_MODE GENMASK(14, 13)
1449 #define CCTLINFO_G7_W2_PRELD_EN BIT(15)
1450 #define CCTLINFO_G7_W2_AMPDU_MAX_LEN GENMASK(26, 16)
1451 #define CCTLINFO_G7_W2_UL_MU_DIS BIT(27)
1452 #define CCTLINFO_G7_W2_AMPDU_MAX_TIME GENMASK(31, 28)
1453 #define CCTLINFO_G7_W2_ALL GENMASK(31, 0)
1454 #define CCTLINFO_G7_W3_MAX_AGG_NUM GENMASK(7, 0)
1455 #define CCTLINFO_G7_W3_DATA_BW GENMASK(10, 8)
1456 #define CCTLINFO_G7_W3_DATA_BW_ER BIT(11)
1457 #define CCTLINFO_G7_W3_BA_BMAP GENMASK(14, 12)
1458 #define CCTLINFO_G7_W3_VCS_STBC BIT(15)
1459 #define CCTLINFO_G7_W3_VO_LFTIME_SEL GENMASK(18, 16)
1460 #define CCTLINFO_G7_W3_VI_LFTIME_SEL GENMASK(21, 19)
1461 #define CCTLINFO_G7_W3_BE_LFTIME_SEL GENMASK(24, 22)
1462 #define CCTLINFO_G7_W3_BK_LFTIME_SEL GENMASK(27, 25)
1463 #define CCTLINFO_G7_W3_AMPDU_TIME_SEL BIT(28)
1464 #define CCTLINFO_G7_W3_AMPDU_LEN_SEL BIT(29)
1465 #define CCTLINFO_G7_W3_RTS_TXCNT_LMT_SEL BIT(30)
1466 #define CCTLINFO_G7_W3_LSIG_TXOP_EN BIT(31)
1467 #define CCTLINFO_G7_W3_ALL GENMASK(31, 0)
1468 #define CCTLINFO_G7_W4_MULTI_PORT_ID GENMASK(2, 0)
1469 #define CCTLINFO_G7_W4_BYPASS_PUNC BIT(3)
1470 #define CCTLINFO_G7_W4_MBSSID GENMASK(7, 4)
1471 #define CCTLINFO_G7_W4_DATA_DCM BIT(8)
1472 #define CCTLINFO_G7_W4_DATA_ER BIT(9)
1473 #define CCTLINFO_G7_W4_DATA_LDPC BIT(10)
1474 #define CCTLINFO_G7_W4_DATA_STBC BIT(11)
1475 #define CCTLINFO_G7_W4_A_CTRL_BQR BIT(12)
1476 #define CCTLINFO_G7_W4_A_CTRL_BSR BIT(14)
1477 #define CCTLINFO_G7_W4_A_CTRL_CAS BIT(15)
1478 #define CCTLINFO_G7_W4_ACT_SUBCH_CBW GENMASK(31, 16)
1479 #define CCTLINFO_G7_W4_ALL (GENMASK(31, 14) | GENMASK(12, 0))
1480 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING0 GENMASK(1, 0)
1481 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING1 GENMASK(3, 2)
1482 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING2 GENMASK(5, 4)
1483 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING3 GENMASK(7, 6)
1484 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING4 GENMASK(9, 8)
1485 #define CCTLINFO_G7_W5_SR_RATE GENMASK(14, 10)
1486 #define CCTLINFO_G7_W5_TID_DISABLE GENMASK(23, 16)
1487 #define CCTLINFO_G7_W5_ADDR_CAM_INDEX GENMASK(31, 24)
1488 #define CCTLINFO_G7_W5_ALL (GENMASK(31, 16) | GENMASK(14, 0))
1489 #define CCTLINFO_G7_W6_AID12_PAID GENMASK(11, 0)
1490 #define CCTLINFO_G7_W6_RESP_REF_RATE GENMASK(23, 12)
1491 #define CCTLINFO_G7_W6_ULDL BIT(31)
1492 #define CCTLINFO_G7_W6_ALL (BIT(31) | GENMASK(23, 0))
1493 #define CCTLINFO_G7_W7_NC GENMASK(2, 0)
1494 #define CCTLINFO_G7_W7_NR GENMASK(5, 3)
1495 #define CCTLINFO_G7_W7_NG GENMASK(7, 6)
1496 #define CCTLINFO_G7_W7_CB GENMASK(9, 8)
1497 #define CCTLINFO_G7_W7_CS GENMASK(11, 10)
1498 #define CCTLINFO_G7_W7_CSI_STBC_EN BIT(13)
1499 #define CCTLINFO_G7_W7_CSI_LDPC_EN BIT(14)
1500 #define CCTLINFO_G7_W7_CSI_PARA_EN BIT(15)
1501 #define CCTLINFO_G7_W7_CSI_FIX_RATE GENMASK(27, 16)
1502 #define CCTLINFO_G7_W7_CSI_BW GENMASK(31, 29)
1503 #define CCTLINFO_G7_W7_ALL (GENMASK(31, 29) | GENMASK(27, 13) | GENMASK(11, 0))
1504 #define CCTLINFO_G7_W8_ALL_ACK_SUPPORT BIT(0)
1505 #define CCTLINFO_G7_W8_BSR_QUEUE_SIZE_FORMAT BIT(1)
1506 #define CCTLINFO_G7_W8_BSR_OM_UPD_EN BIT(2)
1507 #define CCTLINFO_G7_W8_MACID_FWD_IDC BIT(3)
1508 #define CCTLINFO_G7_W8_AZ_SEC_EN BIT(4)
1509 #define CCTLINFO_G7_W8_CSI_SEC_EN BIT(5)
1510 #define CCTLINFO_G7_W8_FIX_UL_ADDRCAM_IDX BIT(6)
1511 #define CCTLINFO_G7_W8_CTRL_CNT_VLD BIT(7)
1512 #define CCTLINFO_G7_W8_CTRL_CNT GENMASK(11, 8)
1513 #define CCTLINFO_G7_W8_RESP_SEC_TYPE GENMASK(15, 12)
1514 #define CCTLINFO_G7_W8_ALL GENMASK(15, 0)
1515 /* W9~13 are reserved */
1516 #define CCTLINFO_G7_W14_VO_CURR_RATE GENMASK(11, 0)
1517 #define CCTLINFO_G7_W14_VI_CURR_RATE GENMASK(23, 12)
1518 #define CCTLINFO_G7_W14_BE_CURR_RATE_L GENMASK(31, 24)
1519 #define CCTLINFO_G7_W14_ALL GENMASK(31, 0)
1520 #define CCTLINFO_G7_W15_BE_CURR_RATE_H GENMASK(3, 0)
1521 #define CCTLINFO_G7_W15_BK_CURR_RATE GENMASK(15, 4)
1522 #define CCTLINFO_G7_W15_MGNT_CURR_RATE GENMASK(27, 16)
1523 #define CCTLINFO_G7_W15_ALL GENMASK(27, 0)
1524
1525 struct rtw89_h2c_cctlinfo_ud_be {
1526 __le32 c0;
1527 __le32 w0;
1528 __le32 w1;
1529 __le32 w2;
1530 __le32 w3;
1531 __le32 w4;
1532 __le32 w5;
1533 __le32 w6;
1534 __le32 w7;
1535 __le32 w8;
1536 __le32 w9;
1537 __le32 w10;
1538 __le32 w11;
1539 __le32 w12;
1540 __le32 w13;
1541 __le32 w14;
1542 __le32 w15;
1543 __le32 m0;
1544 __le32 m1;
1545 __le32 m2;
1546 __le32 m3;
1547 __le32 m4;
1548 __le32 m5;
1549 __le32 m6;
1550 __le32 m7;
1551 __le32 m8;
1552 __le32 m9;
1553 __le32 m10;
1554 __le32 m11;
1555 __le32 m12;
1556 __le32 m13;
1557 __le32 m14;
1558 __le32 m15;
1559 } __packed;
1560
1561 #define BE_CCTL_INFO_C0_V1_MACID GENMASK(9, 0)
1562 #define BE_CCTL_INFO_C0_V1_OP BIT(10)
1563
1564 #define BE_CCTL_INFO_W0_DATARATE GENMASK(11, 0)
1565 #define BE_CCTL_INFO_W0_DATA_GI_LTF GENMASK(14, 12)
1566 #define BE_CCTL_INFO_W0_TRYRATE BIT(15)
1567 #define BE_CCTL_INFO_W0_ARFR_CTRL GENMASK(17, 16)
1568 #define BE_CCTL_INFO_W0_DIS_HE1SS_STBC BIT(18)
1569 #define BE_CCTL_INFO_W0_ACQ_RPT_EN BIT(20)
1570 #define BE_CCTL_INFO_W0_MGQ_RPT_EN BIT(21)
1571 #define BE_CCTL_INFO_W0_ULQ_RPT_EN BIT(22)
1572 #define BE_CCTL_INFO_W0_TWTQ_RPT_EN BIT(23)
1573 #define BE_CCTL_INFO_W0_FORCE_TXOP BIT(24)
1574 #define BE_CCTL_INFO_W0_DISRTSFB BIT(25)
1575 #define BE_CCTL_INFO_W0_DISDATAFB BIT(26)
1576 #define BE_CCTL_INFO_W0_NSTR_EN BIT(27)
1577 #define BE_CCTL_INFO_W0_AMPDU_DENSITY GENMASK(31, 28)
1578 #define BE_CCTL_INFO_W0_ALL (GENMASK(31, 20) | GENMASK(18, 0))
1579 #define BE_CCTL_INFO_W1_DATA_RTY_LOWEST_RATE GENMASK(11, 0)
1580 #define BE_CCTL_INFO_W1_RTS_TXCNT_LMT GENMASK(15, 12)
1581 #define BE_CCTL_INFO_W1_RTSRATE GENMASK(27, 16)
1582 #define BE_CCTL_INFO_W1_RTS_RTY_LOWEST_RATE GENMASK(31, 28)
1583 #define BE_CCTL_INFO_W1_ALL GENMASK(31, 0)
1584 #define BE_CCTL_INFO_W2_DATA_TX_CNT_LMT GENMASK(5, 0)
1585 #define BE_CCTL_INFO_W2_DATA_TXCNT_LMT_SEL BIT(6)
1586 #define BE_CCTL_INFO_W2_MAX_AGG_NUM_SEL BIT(7)
1587 #define BE_CCTL_INFO_W2_RTS_EN BIT(8)
1588 #define BE_CCTL_INFO_W2_CTS2SELF_EN BIT(9)
1589 #define BE_CCTL_INFO_W2_CCA_RTS GENMASK(11, 10)
1590 #define BE_CCTL_INFO_W2_HW_RTS_EN BIT(12)
1591 #define BE_CCTL_INFO_W2_RTS_DROP_DATA_MODE GENMASK(14, 13)
1592 #define BE_CCTL_INFO_W2_PRELOAD_ENABLE BIT(15)
1593 #define BE_CCTL_INFO_W2_AMPDU_MAX_LEN GENMASK(26, 16)
1594 #define BE_CCTL_INFO_W2_UL_MU_DIS BIT(27)
1595 #define BE_CCTL_INFO_W2_AMPDU_MAX_TIME GENMASK(31, 28)
1596 #define BE_CCTL_INFO_W2_ALL GENMASK(31, 0)
1597 #define BE_CCTL_INFO_W3_MAX_AGG_NUM GENMASK(7, 0)
1598 #define BE_CCTL_INFO_W3_DATA_BW GENMASK(10, 8)
1599 #define BE_CCTL_INFO_W3_DATA_BW_ER BIT(11)
1600 #define BE_CCTL_INFO_W3_BA_BMAP GENMASK(14, 12)
1601 #define BE_CCTL_INFO_W3_VCS_STBC BIT(15)
1602 #define BE_CCTL_INFO_W3_VO_LFTIME_SEL GENMASK(18, 16)
1603 #define BE_CCTL_INFO_W3_VI_LFTIME_SEL GENMASK(21, 19)
1604 #define BE_CCTL_INFO_W3_BE_LFTIME_SEL GENMASK(24, 22)
1605 #define BE_CCTL_INFO_W3_BK_LFTIME_SEL GENMASK(27, 25)
1606 #define BE_CCTL_INFO_W3_AMPDU_TIME_SEL BIT(28)
1607 #define BE_CCTL_INFO_W3_AMPDU_LEN_SEL BIT(29)
1608 #define BE_CCTL_INFO_W3_RTS_TXCNT_LMT_SEL BIT(30)
1609 #define BE_CCTL_INFO_W3_LSIG_TXOP_EN BIT(31)
1610 #define BE_CCTL_INFO_W3_ALL GENMASK(31, 0)
1611 #define BE_CCTL_INFO_W4_MULTI_PORT_ID GENMASK(2, 0)
1612 #define BE_CCTL_INFO_W4_BYPASS_PUNC BIT(3)
1613 #define BE_CCTL_INFO_W4_MBSSID GENMASK(7, 4)
1614 #define BE_CCTL_INFO_W4_TID_DISABLE_V1 GENMASK(15, 8)
1615 #define BE_CCTL_INFO_W4_ACT_SUBCH_CBW GENMASK(31, 16)
1616 #define BE_CCTL_INFO_W4_ALL GENMASK(31, 0)
1617 #define BE_CCTL_INFO_W5_ADDR_CAM_INDEX_V1 GENMASK(9, 0)
1618 #define BE_CCTL_INFO_W5_SR_MCS_SU GENMASK(14, 10)
1619 #define BE_CCTL_INFO_W5_A_CTRL_BQR_V1 BIT(15)
1620 #define BE_CCTL_INFO_W5_A_CTRL_BSR_V1 BIT(16)
1621 #define BE_CCTL_INFO_W5_A_CTRL_CAS_V1 BIT(17)
1622 #define BE_CCTL_INFO_W5_DATA_ER_V1 BIT(18)
1623 #define BE_CCTL_INFO_W5_DATA_DCM_V1 BIT(19)
1624 #define BE_CCTL_INFO_W5_DATA_LDPC_V1 BIT(20)
1625 #define BE_CCTL_INFO_W5_DATA_STBC_V1 BIT(21)
1626 #define BE_CCTL_INFO_W5_NOMINAL_PKT_PADDING0_V1 GENMASK(23, 22)
1627 #define BE_CCTL_INFO_W5_NOMINAL_PKT_PADDING1_V1 GENMASK(25, 24)
1628 #define BE_CCTL_INFO_W5_NOMINAL_PKT_PADDING2_V1 GENMASK(27, 26)
1629 #define BE_CCTL_INFO_W5_NOMINAL_PKT_PADDING3_V1 GENMASK(29, 28)
1630 #define BE_CCTL_INFO_W5_NOMINAL_PKT_PADDING4_V1 GENMASK(31, 30)
1631 #define BE_CCTL_INFO_W5_ALL GENMASK(31, 0)
1632 #define BE_CCTL_INFO_W6_AID12_PAID GENMASK(11, 0)
1633 #define BE_CCTL_INFO_W6_RESP_REF_RATE GENMASK(23, 12)
1634 #define BE_CCTL_INFO_W6_ULDL BIT(31)
1635 #define BE_CCTL_INFO_W6_ALL (BIT(31) | GENMASK(23, 0))
1636 #define BE_CCTL_INFO_W7_NC GENMASK(2, 0)
1637 #define BE_CCTL_INFO_W7_NR GENMASK(5, 3)
1638 #define BE_CCTL_INFO_W7_NG GENMASK(7, 6)
1639 #define BE_CCTL_INFO_W7_CB GENMASK(9, 8)
1640 #define BE_CCTL_INFO_W7_CS GENMASK(11, 10)
1641 #define BE_CCTL_INFO_W7_CSI_STBC_EN BIT(13)
1642 #define BE_CCTL_INFO_W7_CSI_LDPC_EN BIT(14)
1643 #define BE_CCTL_INFO_W7_CSI_PARA_EN BIT(15)
1644 #define BE_CCTL_INFO_W7_CSI_FIX_RATE GENMASK(27, 16)
1645 #define BE_CCTL_INFO_W7_CSI_BW GENMASK(31, 29)
1646 #define BE_CCTL_INFO_W7_ALL GENMASK(31, 0)
1647 #define BE_CCTL_INFO_W8_ALL_ACK_SUPPORT_V1 BIT(0)
1648 #define BE_CCTL_INFO_W8_BSR_QUEUE_SIZE_FORMAT_V1 BIT(1)
1649 #define BE_CCTL_INFO_W8_BSR_OM_UPD_EN_V1 BIT(2)
1650 #define BE_CCTL_INFO_W8_MACID_FWD_IDC_V1 BIT(3)
1651 #define BE_CCTL_INFO_W8_AZ_SEC_EN BIT(4)
1652 #define BE_CCTL_INFO_W8_BF_SEC_EN BIT(5)
1653 #define BE_CCTL_INFO_W8_FIX_UL_ADDRCAM_IDX_V1 BIT(6)
1654 #define BE_CCTL_INFO_W8_CTRL_CNT_VLD_V1 BIT(7)
1655 #define BE_CCTL_INFO_W8_CTRL_CNT_V1 GENMASK(11, 8)
1656 #define BE_CCTL_INFO_W8_RESP_SEC_TYPE GENMASK(15, 12)
1657 #define BE_CCTL_INFO_W8_ALL GENMASK(15, 0)
1658 #define BE_CCTL_INFO_W9_EMLSR_TRANS_DLY GENMASK(2, 0)
1659 #define BE_CCTL_INFO_W9_ALL GENMASK(2, 0)
1660 #define BE_CCTL_INFO_W10_SW_EHT_NLTF GENMASK(1, 0)
1661 #define BE_CCTL_INFO_W10_TB_MLO_MODE BIT(2)
1662 #define BE_CCTL_INFO_W10_ALL GENMASK(2, 0)
1663 #define BE_CCTL_INFO_W14_VO_CURR_RATE GENMASK(11, 0)
1664 #define BE_CCTL_INFO_W14_VI_CURR_RATE GENMASK(23, 12)
1665 #define BE_CCTL_INFO_W14_BE_CURR_RATE_L GENMASK(31, 24)
1666 #define BE_CCTL_INFO_W14_ALL GENMASK(31, 0)
1667 #define BE_CCTL_INFO_W15_BE_CURR_RATE_H GENMASK(3, 0)
1668 #define BE_CCTL_INFO_W15_BK_CURR_RATE GENMASK(15, 4)
1669 #define BE_CCTL_INFO_W15_MGNT_CURR_RATE GENMASK(27, 16)
1670 #define BE_CCTL_INFO_W15_ALL GENMASK(27, 0)
1671
1672 struct rtw89_h2c_bcn_upd {
1673 __le32 w0;
1674 __le32 w1;
1675 __le32 w2;
1676 } __packed;
1677
1678 #define RTW89_H2C_BCN_UPD_W0_PORT GENMASK(7, 0)
1679 #define RTW89_H2C_BCN_UPD_W0_MBSSID GENMASK(15, 8)
1680 #define RTW89_H2C_BCN_UPD_W0_BAND GENMASK(23, 16)
1681 #define RTW89_H2C_BCN_UPD_W0_GRP_IE_OFST GENMASK(31, 24)
1682 #define RTW89_H2C_BCN_UPD_W1_MACID GENMASK(7, 0)
1683 #define RTW89_H2C_BCN_UPD_W1_SSN_SEL GENMASK(9, 8)
1684 #define RTW89_H2C_BCN_UPD_W1_SSN_MODE GENMASK(11, 10)
1685 #define RTW89_H2C_BCN_UPD_W1_RATE GENMASK(20, 12)
1686 #define RTW89_H2C_BCN_UPD_W1_TXPWR GENMASK(23, 21)
1687 #define RTW89_H2C_BCN_UPD_W2_TXINFO_CTRL_EN BIT(0)
1688 #define RTW89_H2C_BCN_UPD_W2_NTX_PATH_EN GENMASK(4, 1)
1689 #define RTW89_H2C_BCN_UPD_W2_PATH_MAP_A GENMASK(6, 5)
1690 #define RTW89_H2C_BCN_UPD_W2_PATH_MAP_B GENMASK(8, 7)
1691 #define RTW89_H2C_BCN_UPD_W2_PATH_MAP_C GENMASK(10, 9)
1692 #define RTW89_H2C_BCN_UPD_W2_PATH_MAP_D GENMASK(12, 11)
1693 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_A BIT(13)
1694 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_B BIT(14)
1695 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_C BIT(15)
1696 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_D BIT(16)
1697 #define RTW89_H2C_BCN_UPD_W2_CSA_OFST GENMASK(31, 17)
1698
1699 struct rtw89_h2c_bcn_upd_be {
1700 __le32 w0;
1701 __le32 w1;
1702 __le32 w2;
1703 __le32 w3;
1704 __le32 w4;
1705 __le32 w5;
1706 __le32 w6;
1707 __le32 w7;
1708 __le32 w8;
1709 __le32 w9;
1710 __le32 w10;
1711 __le32 w11;
1712 __le32 w12;
1713 __le32 w13;
1714 __le32 w14;
1715 __le32 w15;
1716 __le32 w16;
1717 __le32 w17;
1718 __le32 w18;
1719 __le32 w19;
1720 __le32 w20;
1721 __le32 w21;
1722 __le32 w22;
1723 __le32 w23;
1724 __le32 w24;
1725 __le32 w25;
1726 __le32 w26;
1727 __le32 w27;
1728 __le32 w28;
1729 __le32 w29;
1730 } __packed;
1731
1732 #define RTW89_H2C_BCN_UPD_BE_W0_PORT GENMASK(7, 0)
1733 #define RTW89_H2C_BCN_UPD_BE_W0_MBSSID GENMASK(15, 8)
1734 #define RTW89_H2C_BCN_UPD_BE_W0_BAND GENMASK(23, 16)
1735 #define RTW89_H2C_BCN_UPD_BE_W0_GRP_IE_OFST GENMASK(31, 24)
1736 #define RTW89_H2C_BCN_UPD_BE_W1_MACID GENMASK(7, 0)
1737 #define RTW89_H2C_BCN_UPD_BE_W1_SSN_SEL GENMASK(9, 8)
1738 #define RTW89_H2C_BCN_UPD_BE_W1_SSN_MODE GENMASK(11, 10)
1739 #define RTW89_H2C_BCN_UPD_BE_W1_RATE GENMASK(20, 12)
1740 #define RTW89_H2C_BCN_UPD_BE_W1_TXPWR GENMASK(23, 21)
1741 #define RTW89_H2C_BCN_UPD_BE_W1_MACID_EXT GENMASK(31, 24)
1742 #define RTW89_H2C_BCN_UPD_BE_W2_TXINFO_CTRL_EN BIT(0)
1743 #define RTW89_H2C_BCN_UPD_BE_W2_NTX_PATH_EN GENMASK(4, 1)
1744 #define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_A GENMASK(6, 5)
1745 #define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_B GENMASK(8, 7)
1746 #define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_C GENMASK(10, 9)
1747 #define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_D GENMASK(12, 11)
1748 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_A BIT(13)
1749 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_B BIT(14)
1750 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_C BIT(15)
1751 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_D BIT(16)
1752 #define RTW89_H2C_BCN_UPD_BE_W2_CSA_OFST GENMASK(31, 17)
1753 #define RTW89_H2C_BCN_UPD_BE_W3_MLIE_CSA_OFST GENMASK(15, 0)
1754 #define RTW89_H2C_BCN_UPD_BE_W3_CRITICAL_UPD_FLAG_OFST GENMASK(31, 16)
1755 #define RTW89_H2C_BCN_UPD_BE_W4_VAP1_DTIM_CNT_OFST GENMASK(15, 0)
1756 #define RTW89_H2C_BCN_UPD_BE_W4_VAP2_DTIM_CNT_OFST GENMASK(31, 16)
1757 #define RTW89_H2C_BCN_UPD_BE_W5_VAP3_DTIM_CNT_OFST GENMASK(15, 0)
1758 #define RTW89_H2C_BCN_UPD_BE_W5_VAP4_DTIM_CNT_OFST GENMASK(31, 16)
1759 #define RTW89_H2C_BCN_UPD_BE_W6_VAP5_DTIM_CNT_OFST GENMASK(15, 0)
1760 #define RTW89_H2C_BCN_UPD_BE_W6_VAP6_DTIM_CNT_OFST GENMASK(31, 16)
1761 #define RTW89_H2C_BCN_UPD_BE_W7_VAP7_DTIM_CNT_OFST GENMASK(15, 0)
1762 #define RTW89_H2C_BCN_UPD_BE_W7_ECSA_OFST GENMASK(30, 16)
1763 #define RTW89_H2C_BCN_UPD_BE_W7_PROTECTION_KEY_ID BIT(31)
1764
1765 struct rtw89_h2c_tbtt_tuning {
1766 __le32 w0;
1767 __le32 w1;
1768 } __packed;
1769
1770 #define RTW89_H2C_TBTT_TUNING_W0_BAND GENMASK(3, 0)
1771 #define RTW89_H2C_TBTT_TUNING_W0_PORT GENMASK(7, 4)
1772 #define RTW89_H2C_TBTT_TUNING_W1_SHIFT GENMASK(31, 0)
1773
1774 struct rtw89_h2c_pwr_lvl {
1775 __le32 w0;
1776 __le32 w1;
1777 } __packed;
1778
1779 #define RTW89_H2C_PWR_LVL_W0_MACID GENMASK(7, 0)
1780 #define RTW89_H2C_PWR_LVL_W0_BCN_TO_VAL GENMASK(15, 8)
1781 #define RTW89_H2C_PWR_LVL_W0_PS_LVL GENMASK(19, 16)
1782 #define RTW89_H2C_PWR_LVL_W0_TRX_LVL GENMASK(23, 20)
1783 #define RTW89_H2C_PWR_LVL_W0_BCN_TO_LVL GENMASK(27, 24)
1784 #define RTW89_H2C_PWR_LVL_W0_DTIM_TO_VAL GENMASK(31, 28)
1785 #define RTW89_H2C_PWR_LVL_W1_MACID_EXT GENMASK(7, 0)
1786
1787 struct rtw89_h2c_role_maintain {
1788 __le32 w0;
1789 };
1790
1791 #define RTW89_H2C_ROLE_MAINTAIN_W0_MACID GENMASK(7, 0)
1792 #define RTW89_H2C_ROLE_MAINTAIN_W0_SELF_ROLE GENMASK(9, 8)
1793 #define RTW89_H2C_ROLE_MAINTAIN_W0_UPD_MODE GENMASK(12, 10)
1794 #define RTW89_H2C_ROLE_MAINTAIN_W0_WIFI_ROLE GENMASK(16, 13)
1795 #define RTW89_H2C_ROLE_MAINTAIN_W0_BAND GENMASK(18, 17)
1796 #define RTW89_H2C_ROLE_MAINTAIN_W0_PORT GENMASK(21, 19)
1797 #define RTW89_H2C_ROLE_MAINTAIN_W0_MACID_EXT GENMASK(31, 24)
1798
1799 enum rtw89_fw_sta_type { /* value of RTW89_H2C_JOININFO_W1_STA_TYPE */
1800 RTW89_FW_N_AC_STA = 0,
1801 RTW89_FW_AX_STA = 1,
1802 RTW89_FW_BE_STA = 2,
1803 };
1804
1805 struct rtw89_h2c_join {
1806 __le32 w0;
1807 } __packed;
1808
1809 struct rtw89_h2c_join_v1 {
1810 __le32 w0;
1811 __le32 w1;
1812 __le32 w2;
1813 } __packed;
1814
1815 #define RTW89_H2C_JOININFO_W0_MACID GENMASK(7, 0)
1816 #define RTW89_H2C_JOININFO_W0_OP BIT(8)
1817 #define RTW89_H2C_JOININFO_W0_BAND BIT(9)
1818 #define RTW89_H2C_JOININFO_W0_WMM GENMASK(11, 10)
1819 #define RTW89_H2C_JOININFO_W0_TGR BIT(12)
1820 #define RTW89_H2C_JOININFO_W0_ISHESTA BIT(13)
1821 #define RTW89_H2C_JOININFO_W0_DLBW GENMASK(15, 14)
1822 #define RTW89_H2C_JOININFO_W0_TF_MAC_PAD GENMASK(17, 16)
1823 #define RTW89_H2C_JOININFO_W0_DL_T_PE GENMASK(20, 18)
1824 #define RTW89_H2C_JOININFO_W0_PORT_ID GENMASK(23, 21)
1825 #define RTW89_H2C_JOININFO_W0_NET_TYPE GENMASK(25, 24)
1826 #define RTW89_H2C_JOININFO_W0_WIFI_ROLE GENMASK(29, 26)
1827 #define RTW89_H2C_JOININFO_W0_SELF_ROLE GENMASK(31, 30)
1828 #define RTW89_H2C_JOININFO_W1_STA_TYPE GENMASK(2, 0)
1829 #define RTW89_H2C_JOININFO_W1_IS_MLD BIT(3)
1830 #define RTW89_H2C_JOININFO_W1_MAIN_MACID GENMASK(11, 4)
1831 #define RTW89_H2C_JOININFO_W1_MLO_MODE BIT(12)
1832 #define RTW89_H2C_JOININFO_MLO_MODE_MLMR 0
1833 #define RTW89_H2C_JOININFO_MLO_MODE_MLSR 1
1834 #define RTW89_H2C_JOININFO_W1_EMLSR_CAB BIT(13)
1835 #define RTW89_H2C_JOININFO_W1_NSTR_EN BIT(14)
1836 #define RTW89_H2C_JOININFO_W1_INIT_PWR_STATE BIT(15)
1837 #define RTW89_H2C_JOININFO_W1_EMLSR_PADDING GENMASK(18, 16)
1838 #define RTW89_H2C_JOININFO_W1_EMLSR_TRANS_DELAY GENMASK(21, 19)
1839 #define RTW89_H2C_JOININFO_W2_MACID_EXT GENMASK(7, 0)
1840 #define RTW89_H2C_JOININFO_W2_MAIN_MACID_EXT GENMASK(15, 8)
1841
1842 struct rtw89_h2c_notify_dbcc {
1843 __le32 w0;
1844 } __packed;
1845
1846 #define RTW89_H2C_NOTIFY_DBCC_EN BIT(0)
1847
SET_GENERAL_PKT_MACID(void * h2c,u32 val)1848 static inline void SET_GENERAL_PKT_MACID(void *h2c, u32 val)
1849 {
1850 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1851 }
1852
SET_GENERAL_PKT_PROBRSP_ID(void * h2c,u32 val)1853 static inline void SET_GENERAL_PKT_PROBRSP_ID(void *h2c, u32 val)
1854 {
1855 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1856 }
1857
SET_GENERAL_PKT_PSPOLL_ID(void * h2c,u32 val)1858 static inline void SET_GENERAL_PKT_PSPOLL_ID(void *h2c, u32 val)
1859 {
1860 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16));
1861 }
1862
SET_GENERAL_PKT_NULL_ID(void * h2c,u32 val)1863 static inline void SET_GENERAL_PKT_NULL_ID(void *h2c, u32 val)
1864 {
1865 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1866 }
1867
SET_GENERAL_PKT_QOS_NULL_ID(void * h2c,u32 val)1868 static inline void SET_GENERAL_PKT_QOS_NULL_ID(void *h2c, u32 val)
1869 {
1870 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0));
1871 }
1872
SET_GENERAL_PKT_CTS2SELF_ID(void * h2c,u32 val)1873 static inline void SET_GENERAL_PKT_CTS2SELF_ID(void *h2c, u32 val)
1874 {
1875 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8));
1876 }
1877
SET_LOG_CFG_LEVEL(void * h2c,u32 val)1878 static inline void SET_LOG_CFG_LEVEL(void *h2c, u32 val)
1879 {
1880 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1881 }
1882
SET_LOG_CFG_PATH(void * h2c,u32 val)1883 static inline void SET_LOG_CFG_PATH(void *h2c, u32 val)
1884 {
1885 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1886 }
1887
SET_LOG_CFG_COMP(void * h2c,u32 val)1888 static inline void SET_LOG_CFG_COMP(void *h2c, u32 val)
1889 {
1890 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(31, 0));
1891 }
1892
SET_LOG_CFG_COMP_EXT(void * h2c,u32 val)1893 static inline void SET_LOG_CFG_COMP_EXT(void *h2c, u32 val)
1894 {
1895 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(31, 0));
1896 }
1897
1898 struct rtw89_h2c_ba_cam {
1899 __le32 w0;
1900 __le32 w1;
1901 } __packed;
1902
1903 #define RTW89_H2C_BA_CAM_W0_VALID BIT(0)
1904 #define RTW89_H2C_BA_CAM_W0_INIT_REQ BIT(1)
1905 #define RTW89_H2C_BA_CAM_W0_ENTRY_IDX GENMASK(3, 2)
1906 #define RTW89_H2C_BA_CAM_W0_TID GENMASK(7, 4)
1907 #define RTW89_H2C_BA_CAM_W0_MACID GENMASK(15, 8)
1908 #define RTW89_H2C_BA_CAM_W0_BMAP_SIZE GENMASK(19, 16)
1909 #define RTW89_H2C_BA_CAM_W0_SSN GENMASK(31, 20)
1910 #define RTW89_H2C_BA_CAM_W1_UID GENMASK(7, 0)
1911 #define RTW89_H2C_BA_CAM_W1_STD_EN BIT(8)
1912 #define RTW89_H2C_BA_CAM_W1_BAND BIT(9)
1913 #define RTW89_H2C_BA_CAM_W1_ENTRY_IDX_V1 GENMASK(31, 28)
1914
1915 struct rtw89_h2c_ba_cam_v1 {
1916 __le32 w0;
1917 __le32 w1;
1918 } __packed;
1919
1920 #define RTW89_H2C_BA_CAM_V1_W0_VALID BIT(0)
1921 #define RTW89_H2C_BA_CAM_V1_W0_INIT_REQ BIT(1)
1922 #define RTW89_H2C_BA_CAM_V1_W0_TID_MASK GENMASK(7, 4)
1923 #define RTW89_H2C_BA_CAM_V1_W0_MACID_MASK GENMASK(15, 8)
1924 #define RTW89_H2C_BA_CAM_V1_W0_BMAP_SIZE_MASK GENMASK(19, 16)
1925 #define RTW89_H2C_BA_CAM_V1_W0_SSN_MASK GENMASK(31, 20)
1926 #define RTW89_H2C_BA_CAM_V1_W1_UID_VALUE_MASK GENMASK(7, 0)
1927 #define RTW89_H2C_BA_CAM_V1_W1_STD_ENTRY_EN BIT(8)
1928 #define RTW89_H2C_BA_CAM_V1_W1_BAND_SEL BIT(9)
1929 #define RTW89_H2C_BA_CAM_V1_W1_MLD_EN BIT(10)
1930 #define RTW89_H2C_BA_CAM_V1_W1_ENTRY_IDX_MASK GENMASK(31, 24)
1931
1932 struct rtw89_h2c_ba_cam_init {
1933 __le32 w0;
1934 } __packed;
1935
1936 #define RTW89_H2C_BA_CAM_INIT_USERS_MASK GENMASK(7, 0)
1937 #define RTW89_H2C_BA_CAM_INIT_OFFSET_MASK GENMASK(19, 12)
1938 #define RTW89_H2C_BA_CAM_INIT_BAND_SEL BIT(24)
1939
SET_LPS_PARM_MACID(void * h2c,u32 val)1940 static inline void SET_LPS_PARM_MACID(void *h2c, u32 val)
1941 {
1942 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1943 }
1944
SET_LPS_PARM_PSMODE(void * h2c,u32 val)1945 static inline void SET_LPS_PARM_PSMODE(void *h2c, u32 val)
1946 {
1947 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1948 }
1949
SET_LPS_PARM_RLBM(void * h2c,u32 val)1950 static inline void SET_LPS_PARM_RLBM(void *h2c, u32 val)
1951 {
1952 le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16));
1953 }
1954
SET_LPS_PARM_SMARTPS(void * h2c,u32 val)1955 static inline void SET_LPS_PARM_SMARTPS(void *h2c, u32 val)
1956 {
1957 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 20));
1958 }
1959
SET_LPS_PARM_AWAKEINTERVAL(void * h2c,u32 val)1960 static inline void SET_LPS_PARM_AWAKEINTERVAL(void *h2c, u32 val)
1961 {
1962 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1963 }
1964
SET_LPS_PARM_VOUAPSD(void * h2c,u32 val)1965 static inline void SET_LPS_PARM_VOUAPSD(void *h2c, u32 val)
1966 {
1967 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(0));
1968 }
1969
SET_LPS_PARM_VIUAPSD(void * h2c,u32 val)1970 static inline void SET_LPS_PARM_VIUAPSD(void *h2c, u32 val)
1971 {
1972 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(1));
1973 }
1974
SET_LPS_PARM_BEUAPSD(void * h2c,u32 val)1975 static inline void SET_LPS_PARM_BEUAPSD(void *h2c, u32 val)
1976 {
1977 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(2));
1978 }
1979
SET_LPS_PARM_BKUAPSD(void * h2c,u32 val)1980 static inline void SET_LPS_PARM_BKUAPSD(void *h2c, u32 val)
1981 {
1982 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(3));
1983 }
1984
SET_LPS_PARM_LASTRPWM(void * h2c,u32 val)1985 static inline void SET_LPS_PARM_LASTRPWM(void *h2c, u32 val)
1986 {
1987 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8));
1988 }
1989
1990 struct rtw89_h2c_lps_ch_info {
1991 struct {
1992 u8 pri_ch;
1993 u8 central_ch;
1994 u8 bw;
1995 u8 band;
1996 } __packed info[2];
1997
1998 __le32 mlo_dbcc_mode_lps;
1999 } __packed;
2000
2001 struct rtw89_h2c_lps_ml_cmn_info {
2002 u8 fmt_id;
2003 u8 rfe_type;
2004 u8 rsvd0[2];
2005 __le32 mlo_dbcc_mode;
2006 u8 central_ch[RTW89_PHY_NUM];
2007 u8 pri_ch[RTW89_PHY_NUM];
2008 u8 bw[RTW89_PHY_NUM];
2009 u8 band[RTW89_PHY_NUM];
2010 u8 bcn_rate_type[RTW89_PHY_NUM];
2011 u8 rsvd1[2];
2012 __le16 tia_gain[RTW89_PHY_NUM][TIA_GAIN_NUM];
2013 u8 lna_gain[RTW89_PHY_NUM][LNA_GAIN_NUM];
2014 u8 rsvd2[2];
2015 u8 tia_lna_op1db[RTW89_PHY_NUM][LNA_GAIN_NUM + 1];
2016 u8 lna_op1db[RTW89_PHY_NUM][LNA_GAIN_NUM];
2017 u8 dup_bcn_ofst[RTW89_PHY_NUM];
2018 } __packed;
2019
2020 #define BB_RX_GAIN_TB_RSSI_COMP_NUM 3
2021 #define BB_RX_GAIN_CCK_RPL_BIAS_COMP_NUM 2
2022 #define BB_GT2_GS_IDX_NUM 11
2023 #define BB_GT2_WB_GIDX_ELNA_NUM 16
2024 #define BB_GT2_G_ELNA_NUM 2
2025
2026 enum rtw89_bb_link_rx_gain_table_type {
2027 RTW89_BB_PS_LINK_RX_GAIN_TAB_BCN_PATH_A = 0x00,
2028 RTW89_BB_PS_LINK_RX_GAIN_TAB_BCN_PATH_B = 0x01,
2029 RTW89_BB_PS_LINK_RX_GAIN_TAB_NOR_PATH_A = 0x02,
2030 RTW89_BB_PS_LINK_RX_GAIN_TAB_NOR_PATH_B = 0x03,
2031 RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX,
2032 };
2033
2034 enum rtw89_bb_ps_link_buf_id {
2035 RTW89_BB_PS_LINK_BUF_0 = 0x00,
2036 RTW89_BB_PS_LINK_BUF_1 = 0x01,
2037 RTW89_BB_PS_LINK_BUF_2 = 0x02,
2038 RTW89_BB_PS_LINK_BUF_MAX,
2039 };
2040
2041 struct rtw89_bb_link_info_rx_gain {
2042 u8 gain_ofst[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX];
2043 __le16 rpl_bias_comp[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX];
2044 u8 tb_rssi_m_bias_comp[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX]
2045 [BB_RX_GAIN_TB_RSSI_COMP_NUM];
2046 u8 cck_gain_ofst[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX];
2047 u8 cck_rpl_bias_comp[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX]
2048 [BB_RX_GAIN_CCK_RPL_BIAS_COMP_NUM];
2049 u8 gain_err_lna[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX][LNA_GAIN_NUM];
2050 __le16 gain_err_tia[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX][TIA_GAIN_NUM];
2051 u8 op1db_lna[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX][LNA_GAIN_NUM];
2052 u8 op1db_tia[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX][TIA_LNA_OP1DB_NUM];
2053 struct {
2054 u8 _20M[RTW89_BW20_SC_20M];
2055 u8 _40M[RTW89_BW20_SC_40M];
2056 u8 _80M[RTW89_BW20_SC_80M];
2057 u8 _160M[RTW89_BW20_SC_160M];
2058 } rpl_bias_comp_bw[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX];
2059 u8 wb_gs[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX][BB_GT2_GS_IDX_NUM];
2060 u8 bypass_lna[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX][LNA_GAIN_NUM];
2061 u8 wb_lna_tia[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX][BB_GT2_WB_GIDX_ELNA_NUM];
2062 u8 wb_g_elna[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX][BB_GT2_G_ELNA_NUM];
2063 } __packed;
2064
2065 struct rtw89_h2c_lps_ml_cmn_info_v1 {
2066 u8 fmt_id;
2067 u8 rfe_type;
2068 u8 rssi_main;
2069 u8 rsvd0;
2070 __le32 mlo_dbcc_mode;
2071 u8 link_id[RTW89_BB_PS_LINK_BUF_MAX];
2072 u8 central_ch[RTW89_BB_PS_LINK_BUF_MAX];
2073 u8 pri_ch[RTW89_BB_PS_LINK_BUF_MAX];
2074 u8 bw[RTW89_BB_PS_LINK_BUF_MAX];
2075 u8 band[RTW89_BB_PS_LINK_BUF_MAX];
2076 u8 dup_bcn_ofst[RTW89_BB_PS_LINK_BUF_MAX];
2077 struct rtw89_bb_link_info_rx_gain rx_gain[RTW89_BB_PS_LINK_BUF_MAX];
2078 } __packed;
2079
2080 struct rtw89_h2c_trig_cpu_except {
2081 __le32 w0;
2082 } __packed;
2083
2084 #define RTW89_H2C_CPU_EXCEPTION_TYPE GENMASK(31, 0)
2085
RTW89_SET_FWCMD_PKT_DROP_SEL(void * cmd,u32 val)2086 static inline void RTW89_SET_FWCMD_PKT_DROP_SEL(void *cmd, u32 val)
2087 {
2088 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
2089 }
2090
RTW89_SET_FWCMD_PKT_DROP_MACID(void * cmd,u32 val)2091 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID(void *cmd, u32 val)
2092 {
2093 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
2094 }
2095
RTW89_SET_FWCMD_PKT_DROP_BAND(void * cmd,u32 val)2096 static inline void RTW89_SET_FWCMD_PKT_DROP_BAND(void *cmd, u32 val)
2097 {
2098 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
2099 }
2100
RTW89_SET_FWCMD_PKT_DROP_PORT(void * cmd,u32 val)2101 static inline void RTW89_SET_FWCMD_PKT_DROP_PORT(void *cmd, u32 val)
2102 {
2103 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
2104 }
2105
RTW89_SET_FWCMD_PKT_DROP_MBSSID(void * cmd,u32 val)2106 static inline void RTW89_SET_FWCMD_PKT_DROP_MBSSID(void *cmd, u32 val)
2107 {
2108 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 0));
2109 }
2110
RTW89_SET_FWCMD_PKT_DROP_ROLE_A_INFO_TF_TRS(void * cmd,u32 val)2111 static inline void RTW89_SET_FWCMD_PKT_DROP_ROLE_A_INFO_TF_TRS(void *cmd, u32 val)
2112 {
2113 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(15, 8));
2114 }
2115
RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_0(void * cmd,u32 val)2116 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_0(void *cmd, u32 val)
2117 {
2118 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
2119 }
2120
RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_1(void * cmd,u32 val)2121 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_1(void *cmd, u32 val)
2122 {
2123 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0));
2124 }
2125
RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_2(void * cmd,u32 val)2126 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_2(void *cmd, u32 val)
2127 {
2128 le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0));
2129 }
2130
RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_3(void * cmd,u32 val)2131 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_3(void *cmd, u32 val)
2132 {
2133 le32p_replace_bits((__le32 *)cmd + 5, val, GENMASK(31, 0));
2134 }
2135
RTW89_SET_KEEP_ALIVE_ENABLE(void * h2c,u32 val)2136 static inline void RTW89_SET_KEEP_ALIVE_ENABLE(void *h2c, u32 val)
2137 {
2138 le32p_replace_bits((__le32 *)h2c, val, GENMASK(1, 0));
2139 }
2140
RTW89_SET_KEEP_ALIVE_PKT_NULL_ID(void * h2c,u32 val)2141 static inline void RTW89_SET_KEEP_ALIVE_PKT_NULL_ID(void *h2c, u32 val)
2142 {
2143 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
2144 }
2145
RTW89_SET_KEEP_ALIVE_PERIOD(void * h2c,u32 val)2146 static inline void RTW89_SET_KEEP_ALIVE_PERIOD(void *h2c, u32 val)
2147 {
2148 le32p_replace_bits((__le32 *)h2c, val, GENMASK(24, 16));
2149 }
2150
RTW89_SET_KEEP_ALIVE_MACID(void * h2c,u32 val)2151 static inline void RTW89_SET_KEEP_ALIVE_MACID(void *h2c, u32 val)
2152 {
2153 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
2154 }
2155
RTW89_SET_DISCONNECT_DETECT_ENABLE(void * h2c,u32 val)2156 static inline void RTW89_SET_DISCONNECT_DETECT_ENABLE(void *h2c, u32 val)
2157 {
2158 le32p_replace_bits((__le32 *)h2c, val, BIT(0));
2159 }
2160
RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_EN(void * h2c,u32 val)2161 static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_EN(void *h2c, u32 val)
2162 {
2163 le32p_replace_bits((__le32 *)h2c, val, BIT(1));
2164 }
2165
RTW89_SET_DISCONNECT_DETECT_DISCONNECT(void * h2c,u32 val)2166 static inline void RTW89_SET_DISCONNECT_DETECT_DISCONNECT(void *h2c, u32 val)
2167 {
2168 le32p_replace_bits((__le32 *)h2c, val, BIT(2));
2169 }
2170
RTW89_SET_DISCONNECT_DETECT_MAC_ID(void * h2c,u32 val)2171 static inline void RTW89_SET_DISCONNECT_DETECT_MAC_ID(void *h2c, u32 val)
2172 {
2173 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
2174 }
2175
RTW89_SET_DISCONNECT_DETECT_CHECK_PERIOD(void * h2c,u32 val)2176 static inline void RTW89_SET_DISCONNECT_DETECT_CHECK_PERIOD(void *h2c, u32 val)
2177 {
2178 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16));
2179 }
2180
RTW89_SET_DISCONNECT_DETECT_TRY_PKT_COUNT(void * h2c,u32 val)2181 static inline void RTW89_SET_DISCONNECT_DETECT_TRY_PKT_COUNT(void *h2c, u32 val)
2182 {
2183 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
2184 }
2185
RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_LIMIT(void * h2c,u32 val)2186 static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_LIMIT(void *h2c, u32 val)
2187 {
2188 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0));
2189 }
2190
2191 struct rtw89_h2c_wow_global {
2192 __le32 w0;
2193 struct rtw89_wow_key_info key_info;
2194 } __packed;
2195
2196 #define RTW89_H2C_WOW_GLOBAL_W0_ENABLE BIT(0)
2197 #define RTW89_H2C_WOW_GLOBAL_W0_DROP_ALL_PKT BIT(1)
2198 #define RTW89_H2C_WOW_GLOBAL_W0_RX_PARSE_AFTER_WAKE BIT(2)
2199 #define RTW89_H2C_WOW_GLOBAL_W0_WAKE_BAR_PULLED BIT(3)
2200 #define RTW89_H2C_WOW_GLOBAL_W0_MAC_ID GENMASK(15, 8)
2201 #define RTW89_H2C_WOW_GLOBAL_W0_PAIRWISE_SEC_ALGO GENMASK(23, 16)
2202 #define RTW89_H2C_WOW_GLOBAL_W0_GROUP_SEC_ALGO GENMASK(31, 24)
2203
2204 #define RTW89_MAX_SUPPORT_NL_NUM 16
2205 struct rtw89_h2c_cfg_nlo {
2206 __le32 w0;
2207 u8 nlo_cnt;
2208 u8 rsvd[3];
2209 __le32 patterncheck;
2210 __le32 rsvd1;
2211 __le32 rsvd2;
2212 u8 ssid_len[RTW89_MAX_SUPPORT_NL_NUM];
2213 u8 chiper[RTW89_MAX_SUPPORT_NL_NUM];
2214 u8 rsvd3[24];
2215 u8 ssid[RTW89_MAX_SUPPORT_NL_NUM][IEEE80211_MAX_SSID_LEN];
2216 } __packed;
2217
2218 #define RTW89_H2C_NLO_W0_ENABLE BIT(0)
2219 #define RTW89_H2C_NLO_W0_IGNORE_CIPHER BIT(2)
2220 #define RTW89_H2C_NLO_W0_MACID GENMASK(31, 24)
2221
RTW89_SET_WOW_WAKEUP_CTRL_PATTERN_MATCH_ENABLE(void * h2c,u32 val)2222 static inline void RTW89_SET_WOW_WAKEUP_CTRL_PATTERN_MATCH_ENABLE(void *h2c, u32 val)
2223 {
2224 le32p_replace_bits((__le32 *)h2c, val, BIT(0));
2225 }
2226
RTW89_SET_WOW_WAKEUP_CTRL_MAGIC_ENABLE(void * h2c,u32 val)2227 static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAGIC_ENABLE(void *h2c, u32 val)
2228 {
2229 le32p_replace_bits((__le32 *)h2c, val, BIT(1));
2230 }
2231
RTW89_SET_WOW_WAKEUP_CTRL_HW_UNICAST_ENABLE(void * h2c,u32 val)2232 static inline void RTW89_SET_WOW_WAKEUP_CTRL_HW_UNICAST_ENABLE(void *h2c, u32 val)
2233 {
2234 le32p_replace_bits((__le32 *)h2c, val, BIT(2));
2235 }
2236
RTW89_SET_WOW_WAKEUP_CTRL_FW_UNICAST_ENABLE(void * h2c,u32 val)2237 static inline void RTW89_SET_WOW_WAKEUP_CTRL_FW_UNICAST_ENABLE(void *h2c, u32 val)
2238 {
2239 le32p_replace_bits((__le32 *)h2c, val, BIT(3));
2240 }
2241
RTW89_SET_WOW_WAKEUP_CTRL_DEAUTH_ENABLE(void * h2c,u32 val)2242 static inline void RTW89_SET_WOW_WAKEUP_CTRL_DEAUTH_ENABLE(void *h2c, u32 val)
2243 {
2244 le32p_replace_bits((__le32 *)h2c, val, BIT(4));
2245 }
2246
RTW89_SET_WOW_WAKEUP_CTRL_REKEYP_ENABLE(void * h2c,u32 val)2247 static inline void RTW89_SET_WOW_WAKEUP_CTRL_REKEYP_ENABLE(void *h2c, u32 val)
2248 {
2249 le32p_replace_bits((__le32 *)h2c, val, BIT(5));
2250 }
2251
RTW89_SET_WOW_WAKEUP_CTRL_EAP_ENABLE(void * h2c,u32 val)2252 static inline void RTW89_SET_WOW_WAKEUP_CTRL_EAP_ENABLE(void *h2c, u32 val)
2253 {
2254 le32p_replace_bits((__le32 *)h2c, val, BIT(6));
2255 }
2256
RTW89_SET_WOW_WAKEUP_CTRL_ALL_DATA_ENABLE(void * h2c,u32 val)2257 static inline void RTW89_SET_WOW_WAKEUP_CTRL_ALL_DATA_ENABLE(void *h2c, u32 val)
2258 {
2259 le32p_replace_bits((__le32 *)h2c, val, BIT(7));
2260 }
2261
RTW89_SET_WOW_WAKEUP_CTRL_MAC_ID(void * h2c,u32 val)2262 static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAC_ID(void *h2c, u32 val)
2263 {
2264 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
2265 }
2266
2267 struct rtw89_h2c_wow_cam_update {
2268 __le32 w0;
2269 __le32 wkfm0;
2270 __le32 wkfm1;
2271 __le32 wkfm2;
2272 __le32 wkfm3;
2273 __le32 w5;
2274 } __packed;
2275
2276 #define RTW89_H2C_WOW_CAM_UPD_W0_R_W BIT(0)
2277 #define RTW89_H2C_WOW_CAM_UPD_W0_IDX GENMASK(7, 1)
2278 #define RTW89_H2C_WOW_CAM_UPD_WKFM0 GENMASK(31, 0)
2279 #define RTW89_H2C_WOW_CAM_UPD_WKFM1 GENMASK(31, 0)
2280 #define RTW89_H2C_WOW_CAM_UPD_WKFM2 GENMASK(31, 0)
2281 #define RTW89_H2C_WOW_CAM_UPD_WKFM3 GENMASK(31, 0)
2282 #define RTW89_H2C_WOW_CAM_UPD_W5_CRC GENMASK(15, 0)
2283 #define RTW89_H2C_WOW_CAM_UPD_W5_NEGATIVE_PATTERN_MATCH BIT(22)
2284 #define RTW89_H2C_WOW_CAM_UPD_W5_SKIP_MAC_HDR BIT(23)
2285 #define RTW89_H2C_WOW_CAM_UPD_W5_UC BIT(24)
2286 #define RTW89_H2C_WOW_CAM_UPD_W5_MC BIT(25)
2287 #define RTW89_H2C_WOW_CAM_UPD_W5_BC BIT(26)
2288 #define RTW89_H2C_WOW_CAM_UPD_W5_VALID BIT(31)
2289
2290 struct rtw89_h2c_wow_payload_cam_update {
2291 __le32 w0;
2292 __le32 wkfm0;
2293 __le32 wkfm1;
2294 __le32 wkfm2;
2295 __le32 wkfm3;
2296 __le32 w5;
2297 __le32 w6;
2298 __le32 w7;
2299 __le32 w8;
2300 } __packed;
2301
2302 #define RTW89_H2C_WOW_PLD_CAM_UPD_W0_R_W BIT(0)
2303 #define RTW89_H2C_WOW_PLD_CAM_UPD_W0_IDX GENMASK(7, 1)
2304 #define RTW89_H2C_WOW_PLD_CAM_UPD_WKFM0 GENMASK(31, 0)
2305 #define RTW89_H2C_WOW_PLD_CAM_UPD_WKFM1 GENMASK(31, 0)
2306 #define RTW89_H2C_WOW_PLD_CAM_UPD_WKFM2 GENMASK(31, 0)
2307 #define RTW89_H2C_WOW_PLD_CAM_UPD_WKFM3 GENMASK(31, 0)
2308 #define RTW89_H2C_WOW_PLD_CAM_UPD_W5_UC BIT(0)
2309 #define RTW89_H2C_WOW_PLD_CAM_UPD_W5_MC BIT(1)
2310 #define RTW89_H2C_WOW_PLD_CAM_UPD_W5_BC BIT(2)
2311 #define RTW89_H2C_WOW_PLD_CAM_UPD_W5_SKIP_MAC_HDR BIT(7)
2312 #define RTW89_H2C_WOW_PLD_CAM_UPD_W6_CRC GENMASK(15, 0)
2313 #define RTW89_H2C_WOW_PLD_CAM_UPD_W7_NEGATIVE_PATTERN_MATCH BIT(0)
2314 #define RTW89_H2C_WOW_PLD_CAM_UPD_W8_VALID BIT(0)
2315 #define RTW89_H2C_WOW_PLD_CAM_UPD_W8_WOW_PTR BIT(1)
2316
2317 struct rtw89_h2c_wow_gtk_ofld {
2318 __le32 w0;
2319 __le32 w1;
2320 struct rtw89_wow_gtk_info gtk_info;
2321 } __packed;
2322
2323 #define RTW89_H2C_WOW_GTK_OFLD_W0_EN BIT(0)
2324 #define RTW89_H2C_WOW_GTK_OFLD_W0_TKIP_EN BIT(1)
2325 #define RTW89_H2C_WOW_GTK_OFLD_W0_IEEE80211W_EN BIT(2)
2326 #define RTW89_H2C_WOW_GTK_OFLD_W0_PAIRWISE_WAKEUP BIT(3)
2327 #define RTW89_H2C_WOW_GTK_OFLD_W0_NOREKEY_WAKEUP BIT(4)
2328 #define RTW89_H2C_WOW_GTK_OFLD_W0_MAC_ID GENMASK(23, 16)
2329 #define RTW89_H2C_WOW_GTK_OFLD_W0_GTK_RSP_ID GENMASK(31, 24)
2330 #define RTW89_H2C_WOW_GTK_OFLD_W1_PMF_SA_QUERY_ID GENMASK(7, 0)
2331 #define RTW89_H2C_WOW_GTK_OFLD_W1_PMF_BIP_SEC_ALGO GENMASK(9, 8)
2332 #define RTW89_H2C_WOW_GTK_OFLD_W1_ALGO_AKM_SUIT GENMASK(17, 10)
2333
2334 struct rtw89_h2c_arp_offload {
2335 __le32 w0;
2336 __le32 w1;
2337 } __packed;
2338
2339 #define RTW89_H2C_ARP_OFFLOAD_W0_ENABLE BIT(0)
2340 #define RTW89_H2C_ARP_OFFLOAD_W0_ACTION BIT(1)
2341 #define RTW89_H2C_ARP_OFFLOAD_W0_MACID GENMASK(23, 16)
2342 #define RTW89_H2C_ARP_OFFLOAD_W0_PKT_ID GENMASK(31, 24)
2343 #define RTW89_H2C_ARP_OFFLOAD_W1_CONTENT GENMASK(31, 0)
2344
2345 enum rtw89_btc_btf_h2c_class {
2346 BTFC_SET = 0x10,
2347 BTFC_GET = 0x11,
2348 BTFC_FW_EVENT = 0x12,
2349 };
2350
2351 enum rtw89_btc_btf_set {
2352 SET_REPORT_EN = 0x0,
2353 SET_SLOT_TABLE,
2354 SET_MREG_TABLE,
2355 SET_CX_POLICY,
2356 SET_GPIO_DBG,
2357 SET_DRV_INFO,
2358 SET_DRV_EVENT,
2359 SET_BT_WREG_ADDR,
2360 SET_BT_WREG_VAL,
2361 SET_BT_RREG_ADDR,
2362 SET_BT_WL_CH_INFO,
2363 SET_BT_INFO_REPORT,
2364 SET_BT_IGNORE_WLAN_ACT,
2365 SET_BT_TX_PWR,
2366 SET_BT_LNA_CONSTRAIN,
2367 SET_BT_QUERY_DEV_LIST,
2368 SET_BT_QUERY_DEV_INFO,
2369 SET_BT_PSD_REPORT,
2370 SET_H2C_TEST,
2371 SET_IOFLD_RF,
2372 SET_IOFLD_BB,
2373 SET_IOFLD_MAC,
2374 SET_IOFLD_SCBD,
2375 SET_H2C_MACRO,
2376 SET_MAX1,
2377 };
2378
2379 enum rtw89_btc_cxdrvinfo {
2380 CXDRVINFO_INIT = 0,
2381 CXDRVINFO_ROLE,
2382 CXDRVINFO_DBCC,
2383 CXDRVINFO_SMAP,
2384 CXDRVINFO_RFK,
2385 CXDRVINFO_RUN,
2386 CXDRVINFO_CTRL,
2387 CXDRVINFO_SCAN,
2388 CXDRVINFO_TRX, /* WL traffic to WL fw */
2389 CXDRVINFO_TXPWR,
2390 CXDRVINFO_FDDT,
2391 CXDRVINFO_MLO,
2392 CXDRVINFO_OSI,
2393 CXDRVINFO_MAX,
2394 };
2395
2396 enum rtw89_scan_mode {
2397 RTW89_SCAN_IMMEDIATE,
2398 RTW89_SCAN_DELAY,
2399 };
2400
2401 enum rtw89_scan_type {
2402 RTW89_SCAN_ONCE,
2403 RTW89_SCAN_NORMAL,
2404 RTW89_SCAN_NORMAL_SLOW,
2405 RTW89_SCAN_SEAMLESS,
2406 RTW89_SCAN_MAX,
2407 };
2408
RTW89_SET_FWCMD_CXHDR_TYPE(void * cmd,u8 val)2409 static inline void RTW89_SET_FWCMD_CXHDR_TYPE(void *cmd, u8 val)
2410 {
2411 u8p_replace_bits((u8 *)(cmd) + 0, val, GENMASK(7, 0));
2412 }
2413
RTW89_SET_FWCMD_CXHDR_LEN(void * cmd,u8 val)2414 static inline void RTW89_SET_FWCMD_CXHDR_LEN(void *cmd, u8 val)
2415 {
2416 u8p_replace_bits((u8 *)(cmd) + 1, val, GENMASK(7, 0));
2417 }
2418
2419 struct rtw89_h2c_cxhdr {
2420 u8 type;
2421 u8 len;
2422 } __packed;
2423
2424 struct rtw89_h2c_cxhdr_v7 {
2425 u8 type;
2426 u8 ver;
2427 u8 len;
2428 } __packed;
2429
2430 struct rtw89_h2c_cxctrl_v7 {
2431 struct rtw89_h2c_cxhdr_v7 hdr;
2432 struct rtw89_btc_ctrl_v7 ctrl;
2433 } __packed;
2434
2435 #define H2C_LEN_CXDRVHDR sizeof(struct rtw89_h2c_cxhdr)
2436 #define H2C_LEN_CXDRVHDR_V7 sizeof(struct rtw89_h2c_cxhdr_v7)
2437
2438 struct rtw89_btc_wl_role_info_v7_u8 {
2439 u8 connect_cnt;
2440 u8 link_mode;
2441 u8 link_mode_chg;
2442 u8 p2p_2g;
2443
2444 struct rtw89_btc_wl_active_role_v7 active_role[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER];
2445 } __packed;
2446
2447 struct rtw89_btc_wl_role_info_v7_u32 {
2448 __le32 role_map;
2449 __le32 mrole_type;
2450 __le32 mrole_noa_duration;
2451 __le32 dbcc_en;
2452 __le32 dbcc_chg;
2453 __le32 dbcc_2g_phy;
2454 } __packed;
2455
2456 struct rtw89_h2c_cxrole_v7 {
2457 struct rtw89_h2c_cxhdr_v7 hdr;
2458 struct rtw89_btc_wl_role_info_v7_u8 _u8;
2459 struct rtw89_btc_wl_role_info_v7_u32 _u32;
2460 } __packed;
2461
2462 struct rtw89_btc_wl_role_info_v8_u8 {
2463 u8 connect_cnt;
2464 u8 link_mode;
2465 u8 link_mode_chg;
2466 u8 p2p_2g;
2467
2468 u8 pta_req_band;
2469 u8 dbcc_en;
2470 u8 dbcc_chg;
2471 u8 dbcc_2g_phy;
2472
2473 struct rtw89_btc_wl_rlink rlink[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM];
2474 } __packed;
2475
2476 struct rtw89_btc_wl_role_info_v8_u32 {
2477 __le32 role_map;
2478 __le32 mrole_type;
2479 __le32 mrole_noa_duration;
2480 } __packed;
2481
2482 struct rtw89_h2c_cxrole_v8 {
2483 struct rtw89_h2c_cxhdr_v7 hdr;
2484 struct rtw89_btc_wl_role_info_v8_u8 _u8;
2485 struct rtw89_btc_wl_role_info_v8_u32 _u32;
2486 } __packed;
2487
2488 struct rtw89_h2c_cxosi {
2489 struct rtw89_h2c_cxhdr_v7 hdr;
2490 struct rtw89_btc_fbtc_outsrc_set_info osi;
2491 } __packed;
2492
2493 struct rtw89_h2c_cxinit {
2494 struct rtw89_h2c_cxhdr hdr;
2495 u8 ant_type;
2496 u8 ant_num;
2497 u8 ant_iso;
2498 u8 ant_info;
2499 u8 mod_rfe;
2500 u8 mod_cv;
2501 u8 mod_info;
2502 u8 mod_adie_kt;
2503 u8 wl_gch;
2504 u8 info;
2505 u8 rsvd;
2506 u8 rsvd1;
2507 } __packed;
2508
2509 #define RTW89_H2C_CXINIT_ANT_INFO_POS BIT(0)
2510 #define RTW89_H2C_CXINIT_ANT_INFO_DIVERSITY BIT(1)
2511 #define RTW89_H2C_CXINIT_ANT_INFO_BTG_POS GENMASK(3, 2)
2512 #define RTW89_H2C_CXINIT_ANT_INFO_STREAM_CNT GENMASK(7, 4)
2513
2514 #define RTW89_H2C_CXINIT_MOD_INFO_BT_SOLO BIT(0)
2515 #define RTW89_H2C_CXINIT_MOD_INFO_BT_POS BIT(1)
2516 #define RTW89_H2C_CXINIT_MOD_INFO_SW_TYPE BIT(2)
2517 #define RTW89_H2C_CXINIT_MOD_INFO_WA_TYPE GENMASK(5, 3)
2518
2519 #define RTW89_H2C_CXINIT_INFO_WL_ONLY BIT(0)
2520 #define RTW89_H2C_CXINIT_INFO_WL_INITOK BIT(1)
2521 #define RTW89_H2C_CXINIT_INFO_DBCC_EN BIT(2)
2522 #define RTW89_H2C_CXINIT_INFO_CX_OTHER BIT(3)
2523 #define RTW89_H2C_CXINIT_INFO_BT_ONLY BIT(4)
2524
2525 struct rtw89_h2c_cxinit_v7 {
2526 struct rtw89_h2c_cxhdr_v7 hdr;
2527 struct rtw89_btc_init_info_v7 init;
2528 } __packed;
2529
RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(void * cmd,u8 val)2530 static inline void RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(void *cmd, u8 val)
2531 {
2532 u8p_replace_bits((u8 *)(cmd) + 2, val, GENMASK(7, 0));
2533 }
2534
RTW89_SET_FWCMD_CXROLE_LINK_MODE(void * cmd,u8 val)2535 static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE(void *cmd, u8 val)
2536 {
2537 u8p_replace_bits((u8 *)(cmd) + 3, val, GENMASK(7, 0));
2538 }
2539
RTW89_SET_FWCMD_CXROLE_ROLE_NONE(void * cmd,u16 val)2540 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NONE(void *cmd, u16 val)
2541 {
2542 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(0));
2543 }
2544
RTW89_SET_FWCMD_CXROLE_ROLE_STA(void * cmd,u16 val)2545 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_STA(void *cmd, u16 val)
2546 {
2547 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(1));
2548 }
2549
RTW89_SET_FWCMD_CXROLE_ROLE_AP(void * cmd,u16 val)2550 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_AP(void *cmd, u16 val)
2551 {
2552 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(2));
2553 }
2554
RTW89_SET_FWCMD_CXROLE_ROLE_VAP(void * cmd,u16 val)2555 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_VAP(void *cmd, u16 val)
2556 {
2557 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(3));
2558 }
2559
RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(void * cmd,u16 val)2560 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(void *cmd, u16 val)
2561 {
2562 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(4));
2563 }
2564
RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(void * cmd,u16 val)2565 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(void *cmd, u16 val)
2566 {
2567 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(5));
2568 }
2569
RTW89_SET_FWCMD_CXROLE_ROLE_MESH(void * cmd,u16 val)2570 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MESH(void *cmd, u16 val)
2571 {
2572 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(6));
2573 }
2574
RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(void * cmd,u16 val)2575 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(void *cmd, u16 val)
2576 {
2577 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(7));
2578 }
2579
RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(void * cmd,u16 val)2580 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(void *cmd, u16 val)
2581 {
2582 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(8));
2583 }
2584
RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(void * cmd,u16 val)2585 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(void *cmd, u16 val)
2586 {
2587 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(9));
2588 }
2589
RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(void * cmd,u16 val)2590 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(void *cmd, u16 val)
2591 {
2592 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(10));
2593 }
2594
RTW89_SET_FWCMD_CXROLE_ROLE_NAN(void * cmd,u16 val)2595 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NAN(void *cmd, u16 val)
2596 {
2597 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(11));
2598 }
2599
RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(void * cmd,u8 val,int n,u8 offset)2600 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(void *cmd, u8 val, int n, u8 offset)
2601 {
2602 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0));
2603 }
2604
RTW89_SET_FWCMD_CXROLE_ACT_PID(void * cmd,u8 val,int n,u8 offset)2605 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PID(void *cmd, u8 val, int n, u8 offset)
2606 {
2607 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(3, 1));
2608 }
2609
RTW89_SET_FWCMD_CXROLE_ACT_PHY(void * cmd,u8 val,int n,u8 offset)2610 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PHY(void *cmd, u8 val, int n, u8 offset)
2611 {
2612 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4));
2613 }
2614
RTW89_SET_FWCMD_CXROLE_ACT_NOA(void * cmd,u8 val,int n,u8 offset)2615 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA(void *cmd, u8 val, int n, u8 offset)
2616 {
2617 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5));
2618 }
2619
RTW89_SET_FWCMD_CXROLE_ACT_BAND(void * cmd,u8 val,int n,u8 offset)2620 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BAND(void *cmd, u8 val, int n, u8 offset)
2621 {
2622 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6));
2623 }
2624
RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(void * cmd,u8 val,int n,u8 offset)2625 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(void *cmd, u8 val, int n, u8 offset)
2626 {
2627 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0));
2628 }
2629
RTW89_SET_FWCMD_CXROLE_ACT_BW(void * cmd,u8 val,int n,u8 offset)2630 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BW(void *cmd, u8 val, int n, u8 offset)
2631 {
2632 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1));
2633 }
2634
RTW89_SET_FWCMD_CXROLE_ACT_ROLE(void * cmd,u8 val,int n,u8 offset)2635 static inline void RTW89_SET_FWCMD_CXROLE_ACT_ROLE(void *cmd, u8 val, int n, u8 offset)
2636 {
2637 u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0));
2638 }
2639
RTW89_SET_FWCMD_CXROLE_ACT_CH(void * cmd,u8 val,int n,u8 offset)2640 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CH(void *cmd, u8 val, int n, u8 offset)
2641 {
2642 u8p_replace_bits((u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0));
2643 }
2644
RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(void * cmd,u16 val,int n,u8 offset)2645 static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(void *cmd, u16 val, int n, u8 offset)
2646 {
2647 le16p_replace_bits((__le16 *)((u8 *)cmd + (10 + (12 + offset) * n)), val, GENMASK(15, 0));
2648 }
2649
RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(void * cmd,u16 val,int n,u8 offset)2650 static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(void *cmd, u16 val, int n, u8 offset)
2651 {
2652 le16p_replace_bits((__le16 *)((u8 *)cmd + (12 + (12 + offset) * n)), val, GENMASK(15, 0));
2653 }
2654
RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(void * cmd,u16 val,int n,u8 offset)2655 static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(void *cmd, u16 val, int n, u8 offset)
2656 {
2657 le16p_replace_bits((__le16 *)((u8 *)cmd + (14 + (12 + offset) * n)), val, GENMASK(15, 0));
2658 }
2659
RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(void * cmd,u16 val,int n,u8 offset)2660 static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(void *cmd, u16 val, int n, u8 offset)
2661 {
2662 le16p_replace_bits((__le16 *)((u8 *)cmd + (16 + (12 + offset) * n)), val, GENMASK(15, 0));
2663 }
2664
RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR(void * cmd,u32 val,int n,u8 offset)2665 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR(void *cmd, u32 val, int n, u8 offset)
2666 {
2667 le32p_replace_bits((__le32 *)((u8 *)cmd + (20 + (12 + offset) * n)), val, GENMASK(31, 0));
2668 }
2669
RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED_V2(void * cmd,u8 val,int n,u8 offset)2670 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED_V2(void *cmd, u8 val, int n, u8 offset)
2671 {
2672 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0));
2673 }
2674
RTW89_SET_FWCMD_CXROLE_ACT_PID_V2(void * cmd,u8 val,int n,u8 offset)2675 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PID_V2(void *cmd, u8 val, int n, u8 offset)
2676 {
2677 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(3, 1));
2678 }
2679
RTW89_SET_FWCMD_CXROLE_ACT_PHY_V2(void * cmd,u8 val,int n,u8 offset)2680 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PHY_V2(void *cmd, u8 val, int n, u8 offset)
2681 {
2682 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4));
2683 }
2684
RTW89_SET_FWCMD_CXROLE_ACT_NOA_V2(void * cmd,u8 val,int n,u8 offset)2685 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_V2(void *cmd, u8 val, int n, u8 offset)
2686 {
2687 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5));
2688 }
2689
RTW89_SET_FWCMD_CXROLE_ACT_BAND_V2(void * cmd,u8 val,int n,u8 offset)2690 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BAND_V2(void *cmd, u8 val, int n, u8 offset)
2691 {
2692 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6));
2693 }
2694
RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS_V2(void * cmd,u8 val,int n,u8 offset)2695 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS_V2(void *cmd, u8 val, int n, u8 offset)
2696 {
2697 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0));
2698 }
2699
RTW89_SET_FWCMD_CXROLE_ACT_BW_V2(void * cmd,u8 val,int n,u8 offset)2700 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BW_V2(void *cmd, u8 val, int n, u8 offset)
2701 {
2702 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1));
2703 }
2704
RTW89_SET_FWCMD_CXROLE_ACT_ROLE_V2(void * cmd,u8 val,int n,u8 offset)2705 static inline void RTW89_SET_FWCMD_CXROLE_ACT_ROLE_V2(void *cmd, u8 val, int n, u8 offset)
2706 {
2707 u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0));
2708 }
2709
RTW89_SET_FWCMD_CXROLE_ACT_CH_V2(void * cmd,u8 val,int n,u8 offset)2710 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CH_V2(void *cmd, u8 val, int n, u8 offset)
2711 {
2712 u8p_replace_bits((u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0));
2713 }
2714
RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR_V2(void * cmd,u32 val,int n,u8 offset)2715 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR_V2(void *cmd, u32 val, int n, u8 offset)
2716 {
2717 le32p_replace_bits((__le32 *)((u8 *)cmd + (10 + (12 + offset) * n)), val, GENMASK(31, 0));
2718 }
2719
RTW89_SET_FWCMD_CXROLE_MROLE_TYPE(void * cmd,u32 val,u8 offset)2720 static inline void RTW89_SET_FWCMD_CXROLE_MROLE_TYPE(void *cmd, u32 val, u8 offset)
2721 {
2722 le32p_replace_bits((__le32 *)((u8 *)cmd + offset), val, GENMASK(31, 0));
2723 }
2724
RTW89_SET_FWCMD_CXROLE_MROLE_NOA(void * cmd,u32 val,u8 offset)2725 static inline void RTW89_SET_FWCMD_CXROLE_MROLE_NOA(void *cmd, u32 val, u8 offset)
2726 {
2727 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 4), val, GENMASK(31, 0));
2728 }
2729
RTW89_SET_FWCMD_CXROLE_DBCC_EN(void * cmd,u32 val,u8 offset)2730 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_EN(void *cmd, u32 val, u8 offset)
2731 {
2732 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(0));
2733 }
2734
RTW89_SET_FWCMD_CXROLE_DBCC_CHG(void * cmd,u32 val,u8 offset)2735 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_CHG(void *cmd, u32 val, u8 offset)
2736 {
2737 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(1));
2738 }
2739
RTW89_SET_FWCMD_CXROLE_DBCC_2G_PHY(void * cmd,u32 val,u8 offset)2740 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_2G_PHY(void *cmd, u32 val, u8 offset)
2741 {
2742 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, GENMASK(3, 2));
2743 }
2744
RTW89_SET_FWCMD_CXROLE_LINK_MODE_CHG(void * cmd,u32 val,u8 offset)2745 static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE_CHG(void *cmd, u32 val, u8 offset)
2746 {
2747 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(4));
2748 }
2749
RTW89_SET_FWCMD_CXCTRL_MANUAL(void * cmd,u32 val)2750 static inline void RTW89_SET_FWCMD_CXCTRL_MANUAL(void *cmd, u32 val)
2751 {
2752 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(0));
2753 }
2754
RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(void * cmd,u32 val)2755 static inline void RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(void *cmd, u32 val)
2756 {
2757 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(1));
2758 }
2759
RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(void * cmd,u32 val)2760 static inline void RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(void *cmd, u32 val)
2761 {
2762 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(2));
2763 }
2764
RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(void * cmd,u32 val)2765 static inline void RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(void *cmd, u32 val)
2766 {
2767 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(18, 3));
2768 }
2769
RTW89_SET_FWCMD_CXTRX_TXLV(void * cmd,u8 val)2770 static inline void RTW89_SET_FWCMD_CXTRX_TXLV(void *cmd, u8 val)
2771 {
2772 u8p_replace_bits((u8 *)cmd + 2, val, GENMASK(7, 0));
2773 }
2774
RTW89_SET_FWCMD_CXTRX_RXLV(void * cmd,u8 val)2775 static inline void RTW89_SET_FWCMD_CXTRX_RXLV(void *cmd, u8 val)
2776 {
2777 u8p_replace_bits((u8 *)cmd + 3, val, GENMASK(7, 0));
2778 }
2779
RTW89_SET_FWCMD_CXTRX_WLRSSI(void * cmd,u8 val)2780 static inline void RTW89_SET_FWCMD_CXTRX_WLRSSI(void *cmd, u8 val)
2781 {
2782 u8p_replace_bits((u8 *)cmd + 4, val, GENMASK(7, 0));
2783 }
2784
RTW89_SET_FWCMD_CXTRX_BTRSSI(void * cmd,u8 val)2785 static inline void RTW89_SET_FWCMD_CXTRX_BTRSSI(void *cmd, u8 val)
2786 {
2787 u8p_replace_bits((u8 *)cmd + 5, val, GENMASK(7, 0));
2788 }
2789
RTW89_SET_FWCMD_CXTRX_TXPWR(void * cmd,s8 val)2790 static inline void RTW89_SET_FWCMD_CXTRX_TXPWR(void *cmd, s8 val)
2791 {
2792 u8p_replace_bits((u8 *)cmd + 6, val, GENMASK(7, 0));
2793 }
2794
RTW89_SET_FWCMD_CXTRX_RXGAIN(void * cmd,s8 val)2795 static inline void RTW89_SET_FWCMD_CXTRX_RXGAIN(void *cmd, s8 val)
2796 {
2797 u8p_replace_bits((u8 *)cmd + 7, val, GENMASK(7, 0));
2798 }
2799
RTW89_SET_FWCMD_CXTRX_BTTXPWR(void * cmd,s8 val)2800 static inline void RTW89_SET_FWCMD_CXTRX_BTTXPWR(void *cmd, s8 val)
2801 {
2802 u8p_replace_bits((u8 *)cmd + 8, val, GENMASK(7, 0));
2803 }
2804
RTW89_SET_FWCMD_CXTRX_BTRXGAIN(void * cmd,s8 val)2805 static inline void RTW89_SET_FWCMD_CXTRX_BTRXGAIN(void *cmd, s8 val)
2806 {
2807 u8p_replace_bits((u8 *)cmd + 9, val, GENMASK(7, 0));
2808 }
2809
RTW89_SET_FWCMD_CXTRX_CN(void * cmd,u8 val)2810 static inline void RTW89_SET_FWCMD_CXTRX_CN(void *cmd, u8 val)
2811 {
2812 u8p_replace_bits((u8 *)cmd + 10, val, GENMASK(7, 0));
2813 }
2814
RTW89_SET_FWCMD_CXTRX_NHM(void * cmd,s8 val)2815 static inline void RTW89_SET_FWCMD_CXTRX_NHM(void *cmd, s8 val)
2816 {
2817 u8p_replace_bits((u8 *)cmd + 11, val, GENMASK(7, 0));
2818 }
2819
RTW89_SET_FWCMD_CXTRX_BTPROFILE(void * cmd,u8 val)2820 static inline void RTW89_SET_FWCMD_CXTRX_BTPROFILE(void *cmd, u8 val)
2821 {
2822 u8p_replace_bits((u8 *)cmd + 12, val, GENMASK(7, 0));
2823 }
2824
RTW89_SET_FWCMD_CXTRX_RSVD2(void * cmd,u8 val)2825 static inline void RTW89_SET_FWCMD_CXTRX_RSVD2(void *cmd, u8 val)
2826 {
2827 u8p_replace_bits((u8 *)cmd + 13, val, GENMASK(7, 0));
2828 }
2829
RTW89_SET_FWCMD_CXTRX_TXRATE(void * cmd,u16 val)2830 static inline void RTW89_SET_FWCMD_CXTRX_TXRATE(void *cmd, u16 val)
2831 {
2832 le16p_replace_bits((__le16 *)((u8 *)cmd + 14), val, GENMASK(15, 0));
2833 }
2834
RTW89_SET_FWCMD_CXTRX_RXRATE(void * cmd,u16 val)2835 static inline void RTW89_SET_FWCMD_CXTRX_RXRATE(void *cmd, u16 val)
2836 {
2837 le16p_replace_bits((__le16 *)((u8 *)cmd + 16), val, GENMASK(15, 0));
2838 }
2839
RTW89_SET_FWCMD_CXTRX_TXTP(void * cmd,u32 val)2840 static inline void RTW89_SET_FWCMD_CXTRX_TXTP(void *cmd, u32 val)
2841 {
2842 le32p_replace_bits((__le32 *)((u8 *)cmd + 18), val, GENMASK(31, 0));
2843 }
2844
RTW89_SET_FWCMD_CXTRX_RXTP(void * cmd,u32 val)2845 static inline void RTW89_SET_FWCMD_CXTRX_RXTP(void *cmd, u32 val)
2846 {
2847 le32p_replace_bits((__le32 *)((u8 *)cmd + 22), val, GENMASK(31, 0));
2848 }
2849
RTW89_SET_FWCMD_CXTRX_RXERRRA(void * cmd,u32 val)2850 static inline void RTW89_SET_FWCMD_CXTRX_RXERRRA(void *cmd, u32 val)
2851 {
2852 le32p_replace_bits((__le32 *)((u8 *)cmd + 26), val, GENMASK(31, 0));
2853 }
2854
RTW89_SET_FWCMD_CXRFK_STATE(void * cmd,u32 val)2855 static inline void RTW89_SET_FWCMD_CXRFK_STATE(void *cmd, u32 val)
2856 {
2857 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(1, 0));
2858 }
2859
RTW89_SET_FWCMD_CXRFK_PATH_MAP(void * cmd,u32 val)2860 static inline void RTW89_SET_FWCMD_CXRFK_PATH_MAP(void *cmd, u32 val)
2861 {
2862 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(5, 2));
2863 }
2864
RTW89_SET_FWCMD_CXRFK_PHY_MAP(void * cmd,u32 val)2865 static inline void RTW89_SET_FWCMD_CXRFK_PHY_MAP(void *cmd, u32 val)
2866 {
2867 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(7, 6));
2868 }
2869
RTW89_SET_FWCMD_CXRFK_BAND(void * cmd,u32 val)2870 static inline void RTW89_SET_FWCMD_CXRFK_BAND(void *cmd, u32 val)
2871 {
2872 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(9, 8));
2873 }
2874
RTW89_SET_FWCMD_CXRFK_TYPE(void * cmd,u32 val)2875 static inline void RTW89_SET_FWCMD_CXRFK_TYPE(void *cmd, u32 val)
2876 {
2877 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(17, 10));
2878 }
2879
RTW89_SET_FWCMD_PACKET_OFLD_PKT_IDX(void * cmd,u32 val)2880 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_IDX(void *cmd, u32 val)
2881 {
2882 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0));
2883 }
2884
RTW89_SET_FWCMD_PACKET_OFLD_PKT_OP(void * cmd,u32 val)2885 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_OP(void *cmd, u32 val)
2886 {
2887 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(10, 8));
2888 }
2889
RTW89_SET_FWCMD_PACKET_OFLD_PKT_LENGTH(void * cmd,u32 val)2890 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_LENGTH(void *cmd, u32 val)
2891 {
2892 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(31, 16));
2893 }
2894
2895 struct rtw89_h2c_chinfo_elem {
2896 __le32 w0;
2897 __le32 w1;
2898 __le32 w2;
2899 __le32 w3;
2900 __le32 w4;
2901 __le32 w5;
2902 __le32 w6;
2903 } __packed;
2904
2905 #define RTW89_H2C_CHINFO_W0_PERIOD GENMASK(7, 0)
2906 #define RTW89_H2C_CHINFO_W0_DWELL GENMASK(15, 8)
2907 #define RTW89_H2C_CHINFO_W0_CENTER_CH GENMASK(23, 16)
2908 #define RTW89_H2C_CHINFO_W0_PRI_CH GENMASK(31, 24)
2909 #define RTW89_H2C_CHINFO_W1_BW GENMASK(2, 0)
2910 #define RTW89_H2C_CHINFO_W1_ACTION GENMASK(7, 3)
2911 #define RTW89_H2C_CHINFO_W1_NUM_PKT GENMASK(11, 8)
2912 #define RTW89_H2C_CHINFO_W1_TX BIT(12)
2913 #define RTW89_H2C_CHINFO_W1_PAUSE_DATA BIT(13)
2914 #define RTW89_H2C_CHINFO_W1_BAND GENMASK(15, 14)
2915 #define RTW89_H2C_CHINFO_W1_PKT_ID GENMASK(23, 16)
2916 #define RTW89_H2C_CHINFO_W1_DFS BIT(24)
2917 #define RTW89_H2C_CHINFO_W1_TX_NULL BIT(25)
2918 #define RTW89_H2C_CHINFO_W1_RANDOM BIT(26)
2919 #define RTW89_H2C_CHINFO_W1_CFG_TX BIT(27)
2920 #define RTW89_H2C_CHINFO_W1_MACID_TX BIT(29)
2921 #define RTW89_H2C_CHINFO_W2_PKT0 GENMASK(7, 0)
2922 #define RTW89_H2C_CHINFO_W2_PKT1 GENMASK(15, 8)
2923 #define RTW89_H2C_CHINFO_W2_PKT2 GENMASK(23, 16)
2924 #define RTW89_H2C_CHINFO_W2_PKT3 GENMASK(31, 24)
2925 #define RTW89_H2C_CHINFO_W3_PKT4 GENMASK(7, 0)
2926 #define RTW89_H2C_CHINFO_W3_PKT5 GENMASK(15, 8)
2927 #define RTW89_H2C_CHINFO_W3_PKT6 GENMASK(23, 16)
2928 #define RTW89_H2C_CHINFO_W3_PKT7 GENMASK(31, 24)
2929 #define RTW89_H2C_CHINFO_W4_POWER_IDX GENMASK(15, 0)
2930
2931 struct rtw89_h2c_chinfo_elem_be {
2932 __le32 w0;
2933 __le32 w1;
2934 __le32 w2;
2935 __le32 w3;
2936 __le32 w4;
2937 __le32 w5;
2938 __le32 w6;
2939 __le32 w7;
2940 } __packed;
2941
2942 #define RTW89_H2C_CHINFO_BE_W0_PERIOD GENMASK(7, 0)
2943 #define RTW89_H2C_CHINFO_BE_W0_DWELL GENMASK(15, 8)
2944 #define RTW89_H2C_CHINFO_BE_W0_CENTER_CH GENMASK(23, 16)
2945 #define RTW89_H2C_CHINFO_BE_W0_PRI_CH GENMASK(31, 24)
2946 #define RTW89_H2C_CHINFO_BE_W1_BW GENMASK(2, 0)
2947 #define RTW89_H2C_CHINFO_BE_W1_CH_BAND GENMASK(4, 3)
2948 #define RTW89_H2C_CHINFO_BE_W1_DFS BIT(5)
2949 #define RTW89_H2C_CHINFO_BE_W1_PAUSE_DATA BIT(6)
2950 #define RTW89_H2C_CHINFO_BE_W1_TX_NULL BIT(7)
2951 #define RTW89_H2C_CHINFO_BE_W1_RANDOM BIT(8)
2952 #define RTW89_H2C_CHINFO_BE_W1_NOTIFY GENMASK(13, 9)
2953 #define RTW89_H2C_CHINFO_BE_W1_PROBE BIT(14)
2954 #define RTW89_H2C_CHINFO_BE_W1_EARLY_LEAVE_CRIT GENMASK(17, 15)
2955 #define RTW89_H2C_CHINFO_BE_W1_CHKPT_TIMER GENMASK(31, 24)
2956 #define RTW89_H2C_CHINFO_BE_W2_EARLY_LEAVE_TIME GENMASK(7, 0)
2957 #define RTW89_H2C_CHINFO_BE_W2_EARLY_LEAVE_TH GENMASK(15, 8)
2958 #define RTW89_H2C_CHINFO_BE_W2_TX_PKT_CTRL GENMASK(31, 16)
2959 #define RTW89_H2C_CHINFO_BE_W3_PKT0 GENMASK(7, 0)
2960 #define RTW89_H2C_CHINFO_BE_W3_PKT1 GENMASK(15, 8)
2961 #define RTW89_H2C_CHINFO_BE_W3_PKT2 GENMASK(23, 16)
2962 #define RTW89_H2C_CHINFO_BE_W3_PKT3 GENMASK(31, 24)
2963 #define RTW89_H2C_CHINFO_BE_W4_PKT4 GENMASK(7, 0)
2964 #define RTW89_H2C_CHINFO_BE_W4_PKT5 GENMASK(15, 8)
2965 #define RTW89_H2C_CHINFO_BE_W4_PKT6 GENMASK(23, 16)
2966 #define RTW89_H2C_CHINFO_BE_W4_PKT7 GENMASK(31, 24)
2967 #define RTW89_H2C_CHINFO_BE_W5_SW_DEF GENMASK(7, 0)
2968 #define RTW89_H2C_CHINFO_BE_W5_FW_PROBE0_SSIDS GENMASK(31, 16)
2969 #define RTW89_H2C_CHINFO_BE_W6_FW_PROBE0_SHORTSSIDS GENMASK(15, 0)
2970 #define RTW89_H2C_CHINFO_BE_W6_FW_PROBE0_BSSIDS GENMASK(31, 16)
2971 #define RTW89_H2C_CHINFO_BE_W7_PERIOD_V1 GENMASK(15, 0)
2972
2973 struct rtw89_h2c_chinfo {
2974 u8 ch_num;
2975 u8 elem_size;
2976 u8 arg;
2977 u8 rsvd0;
2978 struct rtw89_h2c_chinfo_elem elem[] __counted_by(ch_num);
2979 } __packed;
2980
2981 struct rtw89_h2c_chinfo_be {
2982 u8 ch_num;
2983 u8 elem_size;
2984 u8 arg;
2985 u8 rsvd0;
2986 struct rtw89_h2c_chinfo_elem_be elem[] __counted_by(ch_num);
2987 } __packed;
2988
2989 #define RTW89_H2C_CHINFO_ARG_MAC_IDX_MASK BIT(0)
2990 #define RTW89_H2C_CHINFO_ARG_APPEND_MASK BIT(1)
2991
2992 struct rtw89_h2c_scanofld {
2993 __le32 w0;
2994 __le32 w1;
2995 __le32 w2;
2996 __le32 tsf_high;
2997 __le32 tsf_low;
2998 __le32 w5;
2999 __le32 w6;
3000 } __packed;
3001
3002 #define RTW89_H2C_SCANOFLD_W0_MACID GENMASK(7, 0)
3003 #define RTW89_H2C_SCANOFLD_W0_NORM_CY GENMASK(15, 8)
3004 #define RTW89_H2C_SCANOFLD_W0_PORT_ID GENMASK(18, 16)
3005 #define RTW89_H2C_SCANOFLD_W0_BAND BIT(19)
3006 #define RTW89_H2C_SCANOFLD_W0_OPERATION GENMASK(21, 20)
3007 #define RTW89_H2C_SCANOFLD_W0_TARGET_CH_BAND GENMASK(23, 22)
3008 #define RTW89_H2C_SCANOFLD_W1_NOTIFY_END BIT(0)
3009 #define RTW89_H2C_SCANOFLD_W1_TARGET_CH_MODE BIT(1)
3010 #define RTW89_H2C_SCANOFLD_W1_START_MODE BIT(2)
3011 #define RTW89_H2C_SCANOFLD_W1_SCAN_TYPE GENMASK(4, 3)
3012 #define RTW89_H2C_SCANOFLD_W1_TARGET_CH_BW GENMASK(7, 5)
3013 #define RTW89_H2C_SCANOFLD_W1_TARGET_PRI_CH GENMASK(15, 8)
3014 #define RTW89_H2C_SCANOFLD_W1_TARGET_CENTRAL_CH GENMASK(23, 16)
3015 #define RTW89_H2C_SCANOFLD_W1_PROBE_REQ_PKT_ID GENMASK(31, 24)
3016 #define RTW89_H2C_SCANOFLD_W2_NORM_PD GENMASK(15, 0)
3017 #define RTW89_H2C_SCANOFLD_W2_SLOW_PD GENMASK(23, 16)
3018 #define RTW89_H2C_SCANOFLD_W3_TSF_HIGH GENMASK(31, 0)
3019 #define RTW89_H2C_SCANOFLD_W4_TSF_LOW GENMASK(31, 0)
3020 #define RTW89_H2C_SCANOFLD_W6_SECOND_MACID GENMASK(31, 24)
3021
3022 struct rtw89_h2c_scanofld_be_macc_role {
3023 __le32 w0;
3024 } __packed;
3025
3026 #define RTW89_MAX_OP_NUM_BE 2
3027 #define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_BAND GENMASK(1, 0)
3028 #define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_PORT GENMASK(4, 2)
3029 #define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_MACID GENMASK(23, 8)
3030 #define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_OPCH_END GENMASK(31, 24)
3031
3032 struct rtw89_h2c_scanofld_be_opch {
3033 __le32 w0;
3034 __le32 w1;
3035 __le32 w2;
3036 __le32 w3;
3037 __le32 w4;
3038 } __packed;
3039
3040 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_MACID GENMASK(15, 0)
3041 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_BAND GENMASK(17, 16)
3042 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_PORT GENMASK(20, 18)
3043 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_POLICY GENMASK(22, 21)
3044 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_TXNULL BIT(23)
3045 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_POLICY_VAL GENMASK(31, 24)
3046 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_DURATION GENMASK(7, 0)
3047 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_CH_BAND GENMASK(9, 8)
3048 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_BW GENMASK(12, 10)
3049 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_NOTIFY GENMASK(14, 13)
3050 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_PRI_CH GENMASK(23, 16)
3051 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_CENTRAL_CH GENMASK(31, 24)
3052 #define RTW89_H2C_SCANOFLD_BE_OPCH_W2_PKTS_CTRL GENMASK(7, 0)
3053 #define RTW89_H2C_SCANOFLD_BE_OPCH_W2_SW_DEF GENMASK(15, 8)
3054 #define RTW89_H2C_SCANOFLD_BE_OPCH_W2_SS GENMASK(18, 16)
3055 #define RTW89_H2C_SCANOFLD_BE_OPCH_W2_TXBCN BIT(19)
3056 #define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT0 GENMASK(7, 0)
3057 #define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT1 GENMASK(15, 8)
3058 #define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT2 GENMASK(23, 16)
3059 #define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT3 GENMASK(31, 24)
3060 #define RTW89_H2C_SCANOFLD_BE_OPCH_W4_DURATION_V1 GENMASK(15, 0)
3061
3062 struct rtw89_h2c_scanofld_be {
3063 __le32 w0;
3064 __le32 w1;
3065 __le32 w2;
3066 __le32 w3;
3067 __le32 w4;
3068 __le32 w5;
3069 __le32 w6;
3070 __le32 w7;
3071 __le32 w8;
3072 __le32 w9; /* Added after SCAN_OFFLOAD_BE_V1 */
3073 /* struct rtw89_h2c_scanofld_be_macc_role (flexible number) */
3074 /* struct rtw89_h2c_scanofld_be_opch (flexible number) */
3075 } __packed;
3076
3077 #define RTW89_H2C_SCANOFLD_BE_W0_OP GENMASK(1, 0)
3078 #define RTW89_H2C_SCANOFLD_BE_W0_SCAN_MODE GENMASK(3, 2)
3079 #define RTW89_H2C_SCANOFLD_BE_W0_REPEAT GENMASK(5, 4)
3080 #define RTW89_H2C_SCANOFLD_BE_W0_NOTIFY_END BIT(6)
3081 #define RTW89_H2C_SCANOFLD_BE_W0_LEARN_CH BIT(7)
3082 #define RTW89_H2C_SCANOFLD_BE_W0_MACID GENMASK(23, 8)
3083 #define RTW89_H2C_SCANOFLD_BE_W0_PORT GENMASK(26, 24)
3084 #define RTW89_H2C_SCANOFLD_BE_W0_BAND GENMASK(28, 27)
3085 #define RTW89_H2C_SCANOFLD_BE_W0_PROBE_WITH_RATE BIT(29)
3086 #define RTW89_H2C_SCANOFLD_BE_W1_NUM_MACC_ROLE GENMASK(7, 0)
3087 #define RTW89_H2C_SCANOFLD_BE_W1_NUM_OP GENMASK(15, 8)
3088 #define RTW89_H2C_SCANOFLD_BE_W1_NORM_PD GENMASK(31, 16)
3089 #define RTW89_H2C_SCANOFLD_BE_W2_SLOW_PD GENMASK(15, 0)
3090 #define RTW89_H2C_SCANOFLD_BE_W2_NORM_CY GENMASK(23, 16)
3091 #define RTW89_H2C_SCANOFLD_BE_W2_OPCH_END GENMASK(31, 24)
3092 #define RTW89_H2C_SCANOFLD_BE_W3_NUM_SSID GENMASK(7, 0)
3093 #define RTW89_H2C_SCANOFLD_BE_W3_NUM_SHORT_SSID GENMASK(15, 8)
3094 #define RTW89_H2C_SCANOFLD_BE_W3_NUM_BSSID GENMASK(23, 16)
3095 #define RTW89_H2C_SCANOFLD_BE_W3_PROBEID GENMASK(31, 24)
3096 #define RTW89_H2C_SCANOFLD_BE_W4_PROBE_5G GENMASK(7, 0)
3097 #define RTW89_H2C_SCANOFLD_BE_W4_PROBE_6G GENMASK(15, 8)
3098 #define RTW89_H2C_SCANOFLD_BE_W4_DELAY_START GENMASK(31, 16)
3099 #define RTW89_H2C_SCANOFLD_BE_W5_MLO_MODE GENMASK(31, 0)
3100 #define RTW89_H2C_SCANOFLD_BE_W6_CHAN_PROHIB_LOW GENMASK(31, 0)
3101 #define RTW89_H2C_SCANOFLD_BE_W7_CHAN_PROHIB_HIGH GENMASK(31, 0)
3102 #define RTW89_H2C_SCANOFLD_BE_W8_PROBE_RATE_2GHZ GENMASK(7, 0)
3103 #define RTW89_H2C_SCANOFLD_BE_W8_PROBE_RATE_5GHZ GENMASK(15, 8)
3104 #define RTW89_H2C_SCANOFLD_BE_W8_PROBE_RATE_6GHZ GENMASK(23, 16)
3105 #define RTW89_H2C_SCANOFLD_BE_W9_SIZE_CFG GENMASK(7, 0)
3106 #define RTW89_H2C_SCANOFLD_BE_W9_SIZE_MACC GENMASK(15, 8)
3107 #define RTW89_H2C_SCANOFLD_BE_W9_SIZE_OP GENMASK(23, 16)
3108
3109 struct rtw89_h2c_fwips {
3110 __le32 w0;
3111 } __packed;
3112
3113 #define RTW89_H2C_FW_IPS_W0_MACID GENMASK(7, 0)
3114 #define RTW89_H2C_FW_IPS_W0_ENABLE BIT(8)
3115
3116 struct rtw89_h2c_mlo_link_cfg {
3117 __le32 w0;
3118 };
3119
3120 #define RTW89_H2C_MLO_LINK_CFG_W0_MACID GENMASK(15, 0)
3121 #define RTW89_H2C_MLO_LINK_CFG_W0_OPTION GENMASK(19, 16)
3122
RTW89_SET_FWCMD_P2P_MACID(void * cmd,u32 val)3123 static inline void RTW89_SET_FWCMD_P2P_MACID(void *cmd, u32 val)
3124 {
3125 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
3126 }
3127
RTW89_SET_FWCMD_P2P_P2PID(void * cmd,u32 val)3128 static inline void RTW89_SET_FWCMD_P2P_P2PID(void *cmd, u32 val)
3129 {
3130 le32p_replace_bits((__le32 *)cmd, val, GENMASK(11, 8));
3131 }
3132
RTW89_SET_FWCMD_P2P_NOAID(void * cmd,u32 val)3133 static inline void RTW89_SET_FWCMD_P2P_NOAID(void *cmd, u32 val)
3134 {
3135 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 12));
3136 }
3137
RTW89_SET_FWCMD_P2P_ACT(void * cmd,u32 val)3138 static inline void RTW89_SET_FWCMD_P2P_ACT(void *cmd, u32 val)
3139 {
3140 le32p_replace_bits((__le32 *)cmd, val, GENMASK(19, 16));
3141 }
3142
RTW89_SET_FWCMD_P2P_TYPE(void * cmd,u32 val)3143 static inline void RTW89_SET_FWCMD_P2P_TYPE(void *cmd, u32 val)
3144 {
3145 le32p_replace_bits((__le32 *)cmd, val, BIT(20));
3146 }
3147
RTW89_SET_FWCMD_P2P_ALL_SLEP(void * cmd,u32 val)3148 static inline void RTW89_SET_FWCMD_P2P_ALL_SLEP(void *cmd, u32 val)
3149 {
3150 le32p_replace_bits((__le32 *)cmd, val, BIT(21));
3151 }
3152
RTW89_SET_FWCMD_NOA_START_TIME(void * cmd,__le32 val)3153 static inline void RTW89_SET_FWCMD_NOA_START_TIME(void *cmd, __le32 val)
3154 {
3155 *((__le32 *)cmd + 1) = val;
3156 }
3157
RTW89_SET_FWCMD_NOA_INTERVAL(void * cmd,__le32 val)3158 static inline void RTW89_SET_FWCMD_NOA_INTERVAL(void *cmd, __le32 val)
3159 {
3160 *((__le32 *)cmd + 2) = val;
3161 }
3162
RTW89_SET_FWCMD_NOA_DURATION(void * cmd,__le32 val)3163 static inline void RTW89_SET_FWCMD_NOA_DURATION(void *cmd, __le32 val)
3164 {
3165 *((__le32 *)cmd + 3) = val;
3166 }
3167
RTW89_SET_FWCMD_NOA_COUNT(void * cmd,u32 val)3168 static inline void RTW89_SET_FWCMD_NOA_COUNT(void *cmd, u32 val)
3169 {
3170 le32p_replace_bits((__le32 *)(cmd) + 4, val, GENMASK(7, 0));
3171 }
3172
RTW89_SET_FWCMD_NOA_CTWINDOW(void * cmd,u32 val)3173 static inline void RTW89_SET_FWCMD_NOA_CTWINDOW(void *cmd, u32 val)
3174 {
3175 u8 ctwnd;
3176
3177 if (!(val & IEEE80211_P2P_OPPPS_ENABLE_BIT))
3178 return;
3179 ctwnd = FIELD_GET(IEEE80211_P2P_OPPPS_CTWINDOW_MASK, val);
3180 le32p_replace_bits((__le32 *)(cmd) + 4, ctwnd, GENMASK(23, 8));
3181 }
3182
RTW89_SET_FWCMD_TSF32_TOGL_BAND(void * cmd,u32 val)3183 static inline void RTW89_SET_FWCMD_TSF32_TOGL_BAND(void *cmd, u32 val)
3184 {
3185 le32p_replace_bits((__le32 *)cmd, val, BIT(0));
3186 }
3187
RTW89_SET_FWCMD_TSF32_TOGL_EN(void * cmd,u32 val)3188 static inline void RTW89_SET_FWCMD_TSF32_TOGL_EN(void *cmd, u32 val)
3189 {
3190 le32p_replace_bits((__le32 *)cmd, val, BIT(1));
3191 }
3192
RTW89_SET_FWCMD_TSF32_TOGL_PORT(void * cmd,u32 val)3193 static inline void RTW89_SET_FWCMD_TSF32_TOGL_PORT(void *cmd, u32 val)
3194 {
3195 le32p_replace_bits((__le32 *)cmd, val, GENMASK(4, 2));
3196 }
3197
RTW89_SET_FWCMD_TSF32_TOGL_EARLY(void * cmd,u32 val)3198 static inline void RTW89_SET_FWCMD_TSF32_TOGL_EARLY(void *cmd, u32 val)
3199 {
3200 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 16));
3201 }
3202
3203 enum rtw89_fw_mcc_c2h_rpt_cfg {
3204 RTW89_FW_MCC_C2H_RPT_OFF = 0,
3205 RTW89_FW_MCC_C2H_RPT_FAIL_ONLY = 1,
3206 RTW89_FW_MCC_C2H_RPT_ALL = 2,
3207 };
3208
3209 struct rtw89_fw_mcc_add_req {
3210 u8 macid;
3211 u8 central_ch_seg0;
3212 u8 central_ch_seg1;
3213 u8 primary_ch;
3214 enum rtw89_bandwidth bandwidth: 4;
3215 u32 group: 2;
3216 u32 c2h_rpt: 2;
3217 u32 dis_tx_null: 1;
3218 u32 dis_sw_retry: 1;
3219 u32 in_curr_ch: 1;
3220 u32 sw_retry_count: 3;
3221 u32 tx_null_early: 4;
3222 u32 btc_in_2g: 1;
3223 u32 pta_en: 1;
3224 u32 rfk_by_pass: 1;
3225 u32 ch_band_type: 2;
3226 u32 rsvd0: 9;
3227 u32 duration;
3228 u8 courtesy_en;
3229 u8 courtesy_num;
3230 u8 courtesy_target;
3231 u8 rsvd1;
3232 };
3233
RTW89_SET_FWCMD_ADD_MCC_MACID(void * cmd,u32 val)3234 static inline void RTW89_SET_FWCMD_ADD_MCC_MACID(void *cmd, u32 val)
3235 {
3236 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
3237 }
3238
RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG0(void * cmd,u32 val)3239 static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG0(void *cmd, u32 val)
3240 {
3241 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3242 }
3243
RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG1(void * cmd,u32 val)3244 static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG1(void *cmd, u32 val)
3245 {
3246 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3247 }
3248
RTW89_SET_FWCMD_ADD_MCC_PRIMARY_CH(void * cmd,u32 val)3249 static inline void RTW89_SET_FWCMD_ADD_MCC_PRIMARY_CH(void *cmd, u32 val)
3250 {
3251 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
3252 }
3253
RTW89_SET_FWCMD_ADD_MCC_BANDWIDTH(void * cmd,u32 val)3254 static inline void RTW89_SET_FWCMD_ADD_MCC_BANDWIDTH(void *cmd, u32 val)
3255 {
3256 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(3, 0));
3257 }
3258
RTW89_SET_FWCMD_ADD_MCC_GROUP(void * cmd,u32 val)3259 static inline void RTW89_SET_FWCMD_ADD_MCC_GROUP(void *cmd, u32 val)
3260 {
3261 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(5, 4));
3262 }
3263
RTW89_SET_FWCMD_ADD_MCC_C2H_RPT(void * cmd,u32 val)3264 static inline void RTW89_SET_FWCMD_ADD_MCC_C2H_RPT(void *cmd, u32 val)
3265 {
3266 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 6));
3267 }
3268
RTW89_SET_FWCMD_ADD_MCC_DIS_TX_NULL(void * cmd,u32 val)3269 static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_TX_NULL(void *cmd, u32 val)
3270 {
3271 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(8));
3272 }
3273
RTW89_SET_FWCMD_ADD_MCC_DIS_SW_RETRY(void * cmd,u32 val)3274 static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_SW_RETRY(void *cmd, u32 val)
3275 {
3276 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(9));
3277 }
3278
RTW89_SET_FWCMD_ADD_MCC_IN_CURR_CH(void * cmd,u32 val)3279 static inline void RTW89_SET_FWCMD_ADD_MCC_IN_CURR_CH(void *cmd, u32 val)
3280 {
3281 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(10));
3282 }
3283
RTW89_SET_FWCMD_ADD_MCC_SW_RETRY_COUNT(void * cmd,u32 val)3284 static inline void RTW89_SET_FWCMD_ADD_MCC_SW_RETRY_COUNT(void *cmd, u32 val)
3285 {
3286 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(13, 11));
3287 }
3288
RTW89_SET_FWCMD_ADD_MCC_TX_NULL_EARLY(void * cmd,u32 val)3289 static inline void RTW89_SET_FWCMD_ADD_MCC_TX_NULL_EARLY(void *cmd, u32 val)
3290 {
3291 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(17, 14));
3292 }
3293
RTW89_SET_FWCMD_ADD_MCC_BTC_IN_2G(void * cmd,u32 val)3294 static inline void RTW89_SET_FWCMD_ADD_MCC_BTC_IN_2G(void *cmd, u32 val)
3295 {
3296 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(18));
3297 }
3298
RTW89_SET_FWCMD_ADD_MCC_PTA_EN(void * cmd,u32 val)3299 static inline void RTW89_SET_FWCMD_ADD_MCC_PTA_EN(void *cmd, u32 val)
3300 {
3301 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(19));
3302 }
3303
RTW89_SET_FWCMD_ADD_MCC_RFK_BY_PASS(void * cmd,u32 val)3304 static inline void RTW89_SET_FWCMD_ADD_MCC_RFK_BY_PASS(void *cmd, u32 val)
3305 {
3306 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(20));
3307 }
3308
RTW89_SET_FWCMD_ADD_MCC_CH_BAND_TYPE(void * cmd,u32 val)3309 static inline void RTW89_SET_FWCMD_ADD_MCC_CH_BAND_TYPE(void *cmd, u32 val)
3310 {
3311 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(22, 21));
3312 }
3313
RTW89_SET_FWCMD_ADD_MCC_DURATION(void * cmd,u32 val)3314 static inline void RTW89_SET_FWCMD_ADD_MCC_DURATION(void *cmd, u32 val)
3315 {
3316 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
3317 }
3318
RTW89_SET_FWCMD_ADD_MCC_COURTESY_EN(void * cmd,u32 val)3319 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_EN(void *cmd, u32 val)
3320 {
3321 le32p_replace_bits((__le32 *)cmd + 3, val, BIT(0));
3322 }
3323
RTW89_SET_FWCMD_ADD_MCC_COURTESY_NUM(void * cmd,u32 val)3324 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_NUM(void *cmd, u32 val)
3325 {
3326 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(15, 8));
3327 }
3328
RTW89_SET_FWCMD_ADD_MCC_COURTESY_TARGET(void * cmd,u32 val)3329 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_TARGET(void *cmd, u32 val)
3330 {
3331 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(23, 16));
3332 }
3333
3334 enum rtw89_fw_mcc_old_group_actions {
3335 RTW89_FW_MCC_OLD_GROUP_ACT_NONE = 0,
3336 RTW89_FW_MCC_OLD_GROUP_ACT_REPLACE = 1,
3337 };
3338
3339 struct rtw89_fw_mcc_start_req {
3340 u32 group: 2;
3341 u32 btc_in_group: 1;
3342 u32 old_group_action: 2;
3343 u32 old_group: 2;
3344 u32 rsvd0: 9;
3345 u32 notify_cnt: 3;
3346 u32 rsvd1: 2;
3347 u32 notify_rxdbg_en: 1;
3348 u32 rsvd2: 2;
3349 u32 macid: 8;
3350 u32 tsf_low;
3351 u32 tsf_high;
3352 };
3353
RTW89_SET_FWCMD_START_MCC_GROUP(void * cmd,u32 val)3354 static inline void RTW89_SET_FWCMD_START_MCC_GROUP(void *cmd, u32 val)
3355 {
3356 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3357 }
3358
RTW89_SET_FWCMD_START_MCC_BTC_IN_GROUP(void * cmd,u32 val)3359 static inline void RTW89_SET_FWCMD_START_MCC_BTC_IN_GROUP(void *cmd, u32 val)
3360 {
3361 le32p_replace_bits((__le32 *)cmd, val, BIT(2));
3362 }
3363
RTW89_SET_FWCMD_START_MCC_OLD_GROUP_ACTION(void * cmd,u32 val)3364 static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP_ACTION(void *cmd, u32 val)
3365 {
3366 le32p_replace_bits((__le32 *)cmd, val, GENMASK(4, 3));
3367 }
3368
RTW89_SET_FWCMD_START_MCC_OLD_GROUP(void * cmd,u32 val)3369 static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP(void *cmd, u32 val)
3370 {
3371 le32p_replace_bits((__le32 *)cmd, val, GENMASK(6, 5));
3372 }
3373
RTW89_SET_FWCMD_START_MCC_NOTIFY_CNT(void * cmd,u32 val)3374 static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_CNT(void *cmd, u32 val)
3375 {
3376 le32p_replace_bits((__le32 *)cmd, val, GENMASK(18, 16));
3377 }
3378
RTW89_SET_FWCMD_START_MCC_NOTIFY_RXDBG_EN(void * cmd,u32 val)3379 static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_RXDBG_EN(void *cmd, u32 val)
3380 {
3381 le32p_replace_bits((__le32 *)cmd, val, BIT(21));
3382 }
3383
RTW89_SET_FWCMD_START_MCC_MACID(void * cmd,u32 val)3384 static inline void RTW89_SET_FWCMD_START_MCC_MACID(void *cmd, u32 val)
3385 {
3386 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
3387 }
3388
RTW89_SET_FWCMD_START_MCC_TSF_LOW(void * cmd,u32 val)3389 static inline void RTW89_SET_FWCMD_START_MCC_TSF_LOW(void *cmd, u32 val)
3390 {
3391 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0));
3392 }
3393
RTW89_SET_FWCMD_START_MCC_TSF_HIGH(void * cmd,u32 val)3394 static inline void RTW89_SET_FWCMD_START_MCC_TSF_HIGH(void *cmd, u32 val)
3395 {
3396 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
3397 }
3398
RTW89_SET_FWCMD_STOP_MCC_MACID(void * cmd,u32 val)3399 static inline void RTW89_SET_FWCMD_STOP_MCC_MACID(void *cmd, u32 val)
3400 {
3401 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
3402 }
3403
RTW89_SET_FWCMD_STOP_MCC_GROUP(void * cmd,u32 val)3404 static inline void RTW89_SET_FWCMD_STOP_MCC_GROUP(void *cmd, u32 val)
3405 {
3406 le32p_replace_bits((__le32 *)cmd, val, GENMASK(9, 8));
3407 }
3408
RTW89_SET_FWCMD_STOP_MCC_PREV_GROUPS(void * cmd,u32 val)3409 static inline void RTW89_SET_FWCMD_STOP_MCC_PREV_GROUPS(void *cmd, u32 val)
3410 {
3411 le32p_replace_bits((__le32 *)cmd, val, BIT(10));
3412 }
3413
RTW89_SET_FWCMD_DEL_MCC_GROUP_GROUP(void * cmd,u32 val)3414 static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_GROUP(void *cmd, u32 val)
3415 {
3416 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3417 }
3418
RTW89_SET_FWCMD_DEL_MCC_GROUP_PREV_GROUPS(void * cmd,u32 val)3419 static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_PREV_GROUPS(void *cmd, u32 val)
3420 {
3421 le32p_replace_bits((__le32 *)cmd, val, BIT(2));
3422 }
3423
RTW89_SET_FWCMD_RESET_MCC_GROUP_GROUP(void * cmd,u32 val)3424 static inline void RTW89_SET_FWCMD_RESET_MCC_GROUP_GROUP(void *cmd, u32 val)
3425 {
3426 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3427 }
3428
3429 struct rtw89_fw_mcc_tsf_req {
3430 u8 group: 2;
3431 u8 rsvd0: 6;
3432 u8 macid_x;
3433 u8 macid_y;
3434 u8 rsvd1;
3435 };
3436
RTW89_SET_FWCMD_MCC_REQ_TSF_GROUP(void * cmd,u32 val)3437 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_GROUP(void *cmd, u32 val)
3438 {
3439 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3440 }
3441
RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_X(void * cmd,u32 val)3442 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_X(void *cmd, u32 val)
3443 {
3444 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3445 }
3446
RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_Y(void * cmd,u32 val)3447 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_Y(void *cmd, u32 val)
3448 {
3449 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3450 }
3451
RTW89_SET_FWCMD_MCC_MACID_BITMAP_GROUP(void * cmd,u32 val)3452 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_GROUP(void *cmd, u32 val)
3453 {
3454 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3455 }
3456
RTW89_SET_FWCMD_MCC_MACID_BITMAP_MACID(void * cmd,u32 val)3457 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_MACID(void *cmd, u32 val)
3458 {
3459 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3460 }
3461
RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP_LENGTH(void * cmd,u32 val)3462 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP_LENGTH(void *cmd, u32 val)
3463 {
3464 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3465 }
3466
RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP(void * cmd,u8 * bitmap,u8 len)3467 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP(void *cmd,
3468 u8 *bitmap, u8 len)
3469 {
3470 memcpy((__le32 *)cmd + 1, bitmap, len);
3471 }
3472
RTW89_SET_FWCMD_MCC_SYNC_GROUP(void * cmd,u32 val)3473 static inline void RTW89_SET_FWCMD_MCC_SYNC_GROUP(void *cmd, u32 val)
3474 {
3475 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3476 }
3477
RTW89_SET_FWCMD_MCC_SYNC_MACID_SOURCE(void * cmd,u32 val)3478 static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_SOURCE(void *cmd, u32 val)
3479 {
3480 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3481 }
3482
RTW89_SET_FWCMD_MCC_SYNC_MACID_TARGET(void * cmd,u32 val)3483 static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_TARGET(void *cmd, u32 val)
3484 {
3485 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3486 }
3487
RTW89_SET_FWCMD_MCC_SYNC_SYNC_OFFSET(void * cmd,u32 val)3488 static inline void RTW89_SET_FWCMD_MCC_SYNC_SYNC_OFFSET(void *cmd, u32 val)
3489 {
3490 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
3491 }
3492
3493 struct rtw89_fw_mcc_duration {
3494 u32 group: 2;
3495 u32 btc_in_group: 1;
3496 u32 rsvd0: 5;
3497 u32 start_macid: 8;
3498 u32 macid_x: 8;
3499 u32 macid_y: 8;
3500 u32 start_tsf_low;
3501 u32 start_tsf_high;
3502 u32 duration_x;
3503 u32 duration_y;
3504 };
3505
RTW89_SET_FWCMD_MCC_SET_DURATION_GROUP(void * cmd,u32 val)3506 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_GROUP(void *cmd, u32 val)
3507 {
3508 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3509 }
3510
3511 static
RTW89_SET_FWCMD_MCC_SET_DURATION_BTC_IN_GROUP(void * cmd,u32 val)3512 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_BTC_IN_GROUP(void *cmd, u32 val)
3513 {
3514 le32p_replace_bits((__le32 *)cmd, val, BIT(2));
3515 }
3516
3517 static
RTW89_SET_FWCMD_MCC_SET_DURATION_START_MACID(void * cmd,u32 val)3518 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_MACID(void *cmd, u32 val)
3519 {
3520 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3521 }
3522
RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_X(void * cmd,u32 val)3523 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_X(void *cmd, u32 val)
3524 {
3525 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3526 }
3527
RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_Y(void * cmd,u32 val)3528 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_Y(void *cmd, u32 val)
3529 {
3530 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
3531 }
3532
3533 static
RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_LOW(void * cmd,u32 val)3534 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_LOW(void *cmd, u32 val)
3535 {
3536 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0));
3537 }
3538
3539 static
RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_HIGH(void * cmd,u32 val)3540 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_HIGH(void *cmd, u32 val)
3541 {
3542 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
3543 }
3544
3545 static
RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_X(void * cmd,u32 val)3546 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_X(void *cmd, u32 val)
3547 {
3548 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0));
3549 }
3550
3551 static
RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_Y(void * cmd,u32 val)3552 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_Y(void *cmd, u32 val)
3553 {
3554 le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0));
3555 }
3556
3557 enum rtw89_h2c_mrc_sch_types {
3558 RTW89_H2C_MRC_SCH_BAND0_ONLY = 0,
3559 RTW89_H2C_MRC_SCH_BAND1_ONLY = 1,
3560 RTW89_H2C_MRC_SCH_DUAL_BAND = 2,
3561 };
3562
3563 enum rtw89_h2c_mrc_role_types {
3564 RTW89_H2C_MRC_ROLE_WIFI = 0,
3565 RTW89_H2C_MRC_ROLE_BT = 1,
3566 RTW89_H2C_MRC_ROLE_EMPTY = 2,
3567 };
3568
3569 #define RTW89_MAC_MRC_MAX_ADD_SLOT_NUM 3
3570 #define RTW89_MAC_MRC_MAX_ADD_ROLE_NUM_PER_SLOT 1 /* before MLO */
3571
3572 struct rtw89_fw_mrc_add_slot_arg {
3573 u16 duration; /* unit: TU */
3574 bool courtesy_en;
3575 u8 courtesy_period;
3576 u8 courtesy_target; /* slot idx */
3577
3578 unsigned int role_num;
3579 struct {
3580 enum rtw89_h2c_mrc_role_types role_type;
3581 bool is_master;
3582 bool en_tx_null;
3583 enum rtw89_band band;
3584 enum rtw89_bandwidth bw;
3585 u8 macid;
3586 u8 central_ch;
3587 u8 primary_ch;
3588 u8 null_early; /* unit: TU */
3589
3590 /* if MLD, for macid: [0, chip::support_mld_num)
3591 * otherwise, for macid: [0, 32)
3592 */
3593 u32 macid_main_bitmap;
3594 /* for MLD, bit X maps to macid: X + chip::support_mld_num */
3595 u32 macid_paired_bitmap;
3596 } roles[RTW89_MAC_MRC_MAX_ADD_ROLE_NUM_PER_SLOT];
3597 };
3598
3599 struct rtw89_fw_mrc_add_arg {
3600 u8 sch_idx;
3601 enum rtw89_h2c_mrc_sch_types sch_type;
3602 bool btc_in_sch;
3603
3604 unsigned int slot_num;
3605 struct rtw89_fw_mrc_add_slot_arg slots[RTW89_MAC_MRC_MAX_ADD_SLOT_NUM];
3606 };
3607
3608 struct rtw89_h2c_mrc_add_role {
3609 __le32 w0;
3610 __le32 w1;
3611 __le32 w2;
3612 __le32 macid_main_bitmap;
3613 __le32 macid_paired_bitmap;
3614 } __packed;
3615
3616 #define RTW89_H2C_MRC_ADD_ROLE_W0_MACID GENMASK(15, 0)
3617 #define RTW89_H2C_MRC_ADD_ROLE_W0_ROLE_TYPE GENMASK(23, 16)
3618 #define RTW89_H2C_MRC_ADD_ROLE_W0_IS_MASTER BIT(24)
3619 #define RTW89_H2C_MRC_ADD_ROLE_W0_IS_ALT_ROLE BIT(25)
3620 #define RTW89_H2C_MRC_ADD_ROLE_W0_TX_NULL_EN BIT(26)
3621 #define RTW89_H2C_MRC_ADD_ROLE_W0_ROLE_ALT_EN BIT(27)
3622 #define RTW89_H2C_MRC_ADD_ROLE_W1_CENTRAL_CH_SEG GENMASK(7, 0)
3623 #define RTW89_H2C_MRC_ADD_ROLE_W1_PRI_CH GENMASK(15, 8)
3624 #define RTW89_H2C_MRC_ADD_ROLE_W1_BW GENMASK(19, 16)
3625 #define RTW89_H2C_MRC_ADD_ROLE_W1_CH_BAND_TYPE GENMASK(21, 20)
3626 #define RTW89_H2C_MRC_ADD_ROLE_W1_RFK_BY_PASS BIT(22)
3627 #define RTW89_H2C_MRC_ADD_ROLE_W1_CAN_BTC BIT(23)
3628 #define RTW89_H2C_MRC_ADD_ROLE_W1_NULL_EARLY GENMASK(31, 24)
3629 #define RTW89_H2C_MRC_ADD_ROLE_W2_ALT_PERIOD GENMASK(7, 0)
3630 #define RTW89_H2C_MRC_ADD_ROLE_W2_ALT_ROLE_TYPE GENMASK(15, 8)
3631 #define RTW89_H2C_MRC_ADD_ROLE_W2_ALT_ROLE_MACID GENMASK(23, 16)
3632
3633 struct rtw89_h2c_mrc_add_slot {
3634 __le32 w0;
3635 __le32 w1;
3636 struct rtw89_h2c_mrc_add_role roles[];
3637 } __packed;
3638
3639 #define RTW89_H2C_MRC_ADD_SLOT_W0_DURATION GENMASK(15, 0)
3640 #define RTW89_H2C_MRC_ADD_SLOT_W0_COURTESY_EN BIT(17)
3641 #define RTW89_H2C_MRC_ADD_SLOT_W0_ROLE_NUM GENMASK(31, 24)
3642 #define RTW89_H2C_MRC_ADD_SLOT_W1_COURTESY_PERIOD GENMASK(7, 0)
3643 #define RTW89_H2C_MRC_ADD_SLOT_W1_COURTESY_TARGET GENMASK(15, 8)
3644
3645 struct rtw89_h2c_mrc_add {
3646 __le32 w0;
3647 /* Logically append flexible struct rtw89_h2c_mrc_add_slot, but there
3648 * are other flexible array inside it. We cannot access them correctly
3649 * through this struct. So, in case misusing, we don't really declare
3650 * it here.
3651 */
3652 } __packed;
3653
3654 #define RTW89_H2C_MRC_ADD_W0_SCH_IDX GENMASK(3, 0)
3655 #define RTW89_H2C_MRC_ADD_W0_SCH_TYPE GENMASK(7, 4)
3656 #define RTW89_H2C_MRC_ADD_W0_SLOT_NUM GENMASK(15, 8)
3657 #define RTW89_H2C_MRC_ADD_W0_BTC_IN_SCH BIT(16)
3658
3659 enum rtw89_h2c_mrc_start_actions {
3660 RTW89_H2C_MRC_START_ACTION_START_NEW = 0,
3661 RTW89_H2C_MRC_START_ACTION_REPLACE_OLD = 1,
3662 };
3663
3664 struct rtw89_fw_mrc_start_arg {
3665 u8 sch_idx;
3666 u8 old_sch_idx;
3667 u64 start_tsf;
3668 enum rtw89_h2c_mrc_start_actions action;
3669 };
3670
3671 struct rtw89_h2c_mrc_start {
3672 __le32 w0;
3673 __le32 start_tsf_low;
3674 __le32 start_tsf_high;
3675 } __packed;
3676
3677 #define RTW89_H2C_MRC_START_W0_SCH_IDX GENMASK(3, 0)
3678 #define RTW89_H2C_MRC_START_W0_OLD_SCH_IDX GENMASK(7, 4)
3679 #define RTW89_H2C_MRC_START_W0_ACTION GENMASK(15, 8)
3680
3681 struct rtw89_h2c_mrc_del {
3682 __le32 w0;
3683 } __packed;
3684
3685 #define RTW89_H2C_MRC_DEL_W0_SCH_IDX GENMASK(3, 0)
3686 #define RTW89_H2C_MRC_DEL_W0_DEL_ALL BIT(4)
3687 #define RTW89_H2C_MRC_DEL_W0_STOP_ONLY BIT(5)
3688 #define RTW89_H2C_MRC_DEL_W0_SPECIFIC_ROLE_EN BIT(6)
3689 #define RTW89_H2C_MRC_DEL_W0_STOP_SLOT_IDX GENMASK(15, 8)
3690 #define RTW89_H2C_MRC_DEL_W0_SPECIFIC_ROLE_MACID GENMASK(31, 16)
3691
3692 #define RTW89_MAC_MRC_MAX_REQ_TSF_NUM 2
3693
3694 struct rtw89_fw_mrc_req_tsf_arg {
3695 unsigned int num;
3696 struct {
3697 u8 band;
3698 u8 port;
3699 } infos[RTW89_MAC_MRC_MAX_REQ_TSF_NUM];
3700 };
3701
3702 struct rtw89_h2c_mrc_req_tsf {
3703 u8 req_tsf_num;
3704 u8 infos[] __counted_by(req_tsf_num);
3705 } __packed;
3706
3707 #define RTW89_H2C_MRC_REQ_TSF_INFO_BAND GENMASK(3, 0)
3708 #define RTW89_H2C_MRC_REQ_TSF_INFO_PORT GENMASK(7, 4)
3709
3710 enum rtw89_h2c_mrc_upd_bitmap_actions {
3711 RTW89_H2C_MRC_UPD_BITMAP_ACTION_DEL = 0,
3712 RTW89_H2C_MRC_UPD_BITMAP_ACTION_ADD = 1,
3713 };
3714
3715 struct rtw89_fw_mrc_upd_bitmap_arg {
3716 u8 sch_idx;
3717 u8 macid;
3718 u8 client_macid;
3719 enum rtw89_h2c_mrc_upd_bitmap_actions action;
3720 };
3721
3722 struct rtw89_h2c_mrc_upd_bitmap {
3723 __le32 w0;
3724 __le32 w1;
3725 } __packed;
3726
3727 #define RTW89_H2C_MRC_UPD_BITMAP_W0_SCH_IDX GENMASK(3, 0)
3728 #define RTW89_H2C_MRC_UPD_BITMAP_W0_ACTION BIT(4)
3729 #define RTW89_H2C_MRC_UPD_BITMAP_W0_MACID GENMASK(31, 16)
3730 #define RTW89_H2C_MRC_UPD_BITMAP_W1_CLIENT_MACID GENMASK(15, 0)
3731
3732 struct rtw89_fw_mrc_sync_arg {
3733 u8 offset; /* unit: TU */
3734 struct {
3735 u8 band;
3736 u8 port;
3737 } src, dest;
3738 };
3739
3740 struct rtw89_h2c_mrc_sync {
3741 __le32 w0;
3742 __le32 w1;
3743 } __packed;
3744
3745 #define RTW89_H2C_MRC_SYNC_W0_SYNC_EN BIT(0)
3746 #define RTW89_H2C_MRC_SYNC_W0_SRC_PORT GENMASK(11, 8)
3747 #define RTW89_H2C_MRC_SYNC_W0_SRC_BAND GENMASK(15, 12)
3748 #define RTW89_H2C_MRC_SYNC_W0_DEST_PORT GENMASK(19, 16)
3749 #define RTW89_H2C_MRC_SYNC_W0_DEST_BAND GENMASK(23, 20)
3750 #define RTW89_H2C_MRC_SYNC_W1_OFFSET GENMASK(15, 0)
3751
3752 struct rtw89_fw_mrc_upd_duration_arg {
3753 u8 sch_idx;
3754 u64 start_tsf;
3755
3756 unsigned int slot_num;
3757 struct {
3758 u8 slot_idx;
3759 u16 duration; /* unit: TU */
3760 } slots[RTW89_MAC_MRC_MAX_ADD_SLOT_NUM];
3761 };
3762
3763 struct rtw89_h2c_mrc_upd_duration {
3764 __le32 w0;
3765 __le32 start_tsf_low;
3766 __le32 start_tsf_high;
3767 __le32 slots[];
3768 } __packed;
3769
3770 #define RTW89_H2C_MRC_UPD_DURATION_W0_SCH_IDX GENMASK(3, 0)
3771 #define RTW89_H2C_MRC_UPD_DURATION_W0_SLOT_NUM GENMASK(15, 8)
3772 #define RTW89_H2C_MRC_UPD_DURATION_W0_BTC_IN_SCH BIT(16)
3773 #define RTW89_H2C_MRC_UPD_DURATION_SLOT_SLOT_IDX GENMASK(7, 0)
3774 #define RTW89_H2C_MRC_UPD_DURATION_SLOT_DURATION GENMASK(31, 16)
3775
3776 struct rtw89_h2c_wow_aoac {
3777 __le32 w0;
3778 } __packed;
3779
3780 struct rtw89_h2c_ap_info {
3781 __le32 w0;
3782 } __packed;
3783
3784 #define RTW89_H2C_AP_INFO_W0_PWR_INT_EN BIT(0)
3785
3786 #define RTW89_C2H_HEADER_LEN 8
3787
3788 struct rtw89_c2h_hdr {
3789 __le32 w0;
3790 __le32 w1;
3791 } __packed;
3792
3793 #define RTW89_C2H_HDR_W0_CATEGORY GENMASK(1, 0)
3794 #define RTW89_C2H_HDR_W0_CLASS GENMASK(7, 2)
3795 #define RTW89_C2H_HDR_W0_FUNC GENMASK(15, 8)
3796 #define RTW89_C2H_HDR_W1_LEN GENMASK(13, 0)
3797
3798 struct rtw89_fw_c2h_attr {
3799 u8 category;
3800 u8 class;
3801 u8 func;
3802 u16 len;
3803 u8 is_scan_event: 1;
3804 u8 scan_seq: 2;
3805 };
3806
RTW89_SKB_C2H_CB(struct sk_buff * skb)3807 static inline struct rtw89_fw_c2h_attr *RTW89_SKB_C2H_CB(struct sk_buff *skb)
3808 {
3809 static_assert(sizeof(skb->cb) >= sizeof(struct rtw89_fw_c2h_attr));
3810
3811 return (struct rtw89_fw_c2h_attr *)skb->cb;
3812 }
3813
3814 struct rtw89_c2h_done_ack {
3815 __le32 w0;
3816 __le32 w1;
3817 __le32 w2;
3818 } __packed;
3819
3820 #define RTW89_C2H_DONE_ACK_W2_CAT GENMASK(1, 0)
3821 #define RTW89_C2H_DONE_ACK_W2_CLASS GENMASK(7, 2)
3822 #define RTW89_C2H_DONE_ACK_W2_FUNC GENMASK(15, 8)
3823 #define RTW89_C2H_DONE_ACK_W2_H2C_RETURN GENMASK(23, 16)
3824 #define RTW89_C2H_SCAN_DONE_ACK_RETURN GENMASK(5, 0)
3825 #define RTW89_C2H_DONE_ACK_W2_H2C_SEQ GENMASK(31, 24)
3826
3827 #define RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h) \
3828 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
3829 #define RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h) \
3830 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2))
3831 #define RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h) \
3832 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3833 #define RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h) \
3834 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16))
3835
3836 struct rtw89_fw_c2h_log_fmt {
3837 __le16 signature;
3838 u8 feature;
3839 u8 syntax;
3840 __le32 fmt_id;
3841 u8 file_num;
3842 __le16 line_num;
3843 u8 argc;
3844 union {
3845 DECLARE_FLEX_ARRAY(u8, raw);
3846 DECLARE_FLEX_ARRAY(__le32, argv);
3847 } __packed u;
3848 } __packed;
3849
3850 #define RTW89_C2H_FW_FORMATTED_LOG_MIN_LEN 11
3851 #define RTW89_C2H_FW_LOG_FEATURE_PARA_INT BIT(2)
3852 #define RTW89_C2H_FW_LOG_MAX_PARA_NUM 16
3853 #define RTW89_C2H_FW_LOG_SIGNATURE 0xA5A5
3854 #define RTW89_C2H_FW_LOG_STR_BUF_SIZE 512
3855
3856 struct rtw89_c2h_bcn_upd_done {
3857 struct rtw89_c2h_hdr hdr;
3858 __le32 w2;
3859 } __packed;
3860
3861 #define RTW89_C2H_BCN_UPD_DONE_W2_PORT GENMASK(2, 0)
3862 #define RTW89_C2H_BCN_UPD_DONE_W2_MBSSID GENMASK(6, 3)
3863 #define RTW89_C2H_BCN_UPD_DONE_W2_BAND_IDX BIT(7)
3864
3865 struct rtw89_c2h_mac_bcnfltr_rpt {
3866 __le32 w0;
3867 __le32 w1;
3868 __le32 w2;
3869 } __packed;
3870
3871 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_MACID GENMASK(7, 0)
3872 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_TYPE GENMASK(9, 8)
3873 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_EVENT GENMASK(11, 10)
3874 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_MA GENMASK(23, 16)
3875
3876 struct rtw89_c2h_ra_rpt {
3877 struct rtw89_c2h_hdr hdr;
3878 __le32 w2;
3879 __le32 w3;
3880 } __packed;
3881
3882 #define RTW89_C2H_RA_RPT_W2_MACID GENMASK(15, 0)
3883 #define RTW89_C2H_RA_RPT_W2_RETRY_RATIO GENMASK(23, 16)
3884 #define RTW89_C2H_RA_RPT_W2_MCSNSS_B7 BIT(31)
3885 #define RTW89_C2H_RA_RPT_W3_MCSNSS GENMASK(6, 0)
3886 #define RTW89_C2H_RA_RPT_W3_MD_SEL GENMASK(9, 8)
3887 #define RTW89_C2H_RA_RPT_W3_GILTF GENMASK(12, 10)
3888 #define RTW89_C2H_RA_RPT_W3_BW GENMASK(14, 13)
3889 #define RTW89_C2H_RA_RPT_W3_MD_SEL_B2 BIT(15)
3890 #define RTW89_C2H_RA_RPT_W3_BW_B2 BIT(16)
3891
3892 struct rtw89_c2h_lps_rpt {
3893 struct rtw89_c2h_hdr hdr;
3894 u8 type;
3895 u8 cnt_bbcr;
3896 u8 cnt_bbmcucr;
3897 u8 cnt_rfcr;
3898 u8 data[];
3899 /*
3900 * The layout of data:
3901 * u8 info[][4], size = total_len - size of below fields
3902 * __le16 bbcr_addr[], size = cnt_bbcr
3903 * __le32 bbcr_data[], size = cnt_bbcr
3904 * __le16 bbmcucr_addr[], size = cnt_bbmcucr
3905 * __le32 bbmcucr_data[], size = cnt_bbmcucr
3906 * __le16 rfcr_addr[], size = cnt_rfcr
3907 * __le32 rfcr_data_a[], size = cnt_rfcr
3908 * __le32 rfcr_data_b[], size = cnt_rfcr
3909 */
3910 } __packed;
3911
3912 struct rtw89_c2h_fw_scan_rpt {
3913 struct rtw89_c2h_hdr hdr;
3914 u8 phy_idx;
3915 u8 band;
3916 u8 center_ch;
3917 u8 ofdm_pd_idx; /* in unit of 2 dBm */
3918 #define PD_LOWER_BOUND_BASE 102
3919 s8 cck_pd_idx;
3920 u8 rsvd0;
3921 u8 rsvd1;
3922 u8 rsvd2;
3923 } __packed;
3924
3925 /* For WiFi 6 chips:
3926 * VHT, HE, HT-old: [6:4]: NSS, [3:0]: MCS
3927 * HT-new: [6:5]: NA, [4:0]: MCS
3928 * For WiFi 7 chips (V1):
3929 * HT, VHT, HE, EHT: [7:5]: NSS, [4:0]: MCS
3930 */
3931 #define RTW89_RA_RATE_MASK_NSS GENMASK(6, 4)
3932 #define RTW89_RA_RATE_MASK_MCS GENMASK(3, 0)
3933 #define RTW89_RA_RATE_MASK_NSS_V1 GENMASK(7, 5)
3934 #define RTW89_RA_RATE_MASK_MCS_V1 GENMASK(4, 0)
3935 #define RTW89_RA_RATE_MASK_HT_MCS GENMASK(4, 0)
3936 #define RTW89_MK_HT_RATE(nss, mcs) (FIELD_PREP(GENMASK(4, 3), nss) | \
3937 FIELD_PREP(GENMASK(2, 0), mcs))
3938
3939 #define RTW89_GET_MAC_C2H_PKTOFLD_ID(c2h) \
3940 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0))
3941 #define RTW89_GET_MAC_C2H_PKTOFLD_OP(c2h) \
3942 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(10, 8))
3943 #define RTW89_GET_MAC_C2H_PKTOFLD_LEN(c2h) \
3944 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 16))
3945
3946 struct rtw89_c2h_scanofld {
3947 __le32 w0;
3948 __le32 w1;
3949 __le32 w2;
3950 __le32 w3;
3951 __le32 w4;
3952 __le32 w5;
3953 __le32 w6;
3954 __le32 w7;
3955 __le32 w8;
3956 } __packed;
3957
3958 #define RTW89_C2H_SCANOFLD_W2_PRI_CH GENMASK(7, 0)
3959 #define RTW89_C2H_SCANOFLD_W2_RSN GENMASK(19, 16)
3960 #define RTW89_C2H_SCANOFLD_W2_STATUS GENMASK(23, 20)
3961 #define RTW89_C2H_SCANOFLD_W2_PERIOD GENMASK(31, 24)
3962 #define RTW89_C2H_SCANOFLD_W5_TX_FAIL GENMASK(3, 0)
3963 #define RTW89_C2H_SCANOFLD_W5_AIR_DENSITY GENMASK(7, 4)
3964 #define RTW89_C2H_SCANOFLD_W5_BAND GENMASK(25, 24)
3965 #define RTW89_C2H_SCANOFLD_W5_MAC_IDX BIT(26)
3966 #define RTW89_C2H_SCANOFLD_W6_SW_DEF GENMASK(7, 0)
3967 #define RTW89_C2H_SCANOFLD_W6_EXPECT_PERIOD GENMASK(15, 8)
3968 #define RTW89_C2H_SCANOFLD_W6_FW_DEF GENMASK(23, 16)
3969 #define RTW89_C2H_SCANOFLD_W7_REPORT_TSF GENMASK(31, 0)
3970 #define RTW89_C2H_SCANOFLD_W8_PERIOD_V1 GENMASK(15, 0)
3971 #define RTW89_C2H_SCANOFLD_W8_EXPECT_PERIOD_V1 GENMASK(31, 16)
3972
3973 #define RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h) \
3974 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
3975 #define RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h) \
3976 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3977
3978 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h) \
3979 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
3980 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h) \
3981 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2))
3982 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h) \
3983 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3984
3985 struct rtw89_c2h_mac_tx_rpt {
3986 struct rtw89_c2h_hdr hdr;
3987 __le32 w2;
3988 __le32 w3;
3989 __le32 w4;
3990 __le32 w5;
3991 __le32 w6;
3992 __le32 w7;
3993 } __packed;
3994
3995 #define RTW89_C2H_MAC_TX_RPT_W2_TX_STATE GENMASK(7, 6)
3996 #define RTW89_C2H_MAC_TX_RPT_W2_SW_DEFINE GENMASK(11, 8)
3997 #define RTW89_C2H_MAC_TX_RPT_W5_DATA_TX_CNT GENMASK(13, 8)
3998 #define RTW89_C2H_MAC_TX_RPT_W5_DATA_TX_CNT_V1 GENMASK(15, 10)
3999
4000 struct rtw89_c2h_mac_tx_rpt_v2 {
4001 struct rtw89_c2h_hdr hdr;
4002 __le32 w2;
4003 __le32 w3;
4004 __le32 w4;
4005 __le32 w5;
4006 __le32 w6;
4007 __le32 w7;
4008 __le32 w8;
4009 __le32 w9;
4010 __le32 w10;
4011 __le32 w11;
4012 __le32 w12;
4013 __le32 w13;
4014 __le32 w14;
4015 __le32 w15;
4016 __le32 w16;
4017 __le32 w17;
4018 __le32 w18;
4019 __le32 w19;
4020 } __packed;
4021
4022 #define RTW89_C2H_MAC_TX_RPT_W12_TX_STATE_V2 GENMASK(9, 8)
4023 #define RTW89_C2H_MAC_TX_RPT_W12_SW_DEFINE_V2 GENMASK(15, 12)
4024 #define RTW89_C2H_MAC_TX_RPT_W14_DATA_TX_CNT_V2 GENMASK(15, 10)
4025
4026 struct rtw89_mac_mcc_tsf_rpt {
4027 u32 macid_x;
4028 u32 macid_y;
4029 u32 tsf_x_low;
4030 u32 tsf_x_high;
4031 u32 tsf_y_low;
4032 u32 tsf_y_high;
4033 };
4034
4035 static_assert(sizeof(struct rtw89_mac_mcc_tsf_rpt) <= RTW89_COMPLETION_BUF_SIZE);
4036
4037 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h) \
4038 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0))
4039 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h) \
4040 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
4041 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h) \
4042 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(17, 16))
4043 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h) \
4044 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(31, 0))
4045 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h) \
4046 le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0))
4047 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h) \
4048 le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(31, 0))
4049 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h) \
4050 le32_get_bits(*((const __le32 *)(c2h) + 6), GENMASK(31, 0))
4051
4052 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h) \
4053 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(5, 0))
4054 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h) \
4055 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 6))
4056 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h) \
4057 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
4058 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h) \
4059 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(31, 0))
4060 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h) \
4061 le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0))
4062
4063 struct rtw89_c2h_mlo_link_cfg_rpt {
4064 struct rtw89_c2h_hdr hdr;
4065 __le32 w2;
4066 } __packed;
4067
4068 #define RTW89_C2H_MLO_LINK_CFG_RPT_W2_MACID GENMASK(15, 0)
4069 #define RTW89_C2H_MLO_LINK_CFG_RPT_W2_STATUS GENMASK(19, 16)
4070
4071 enum rtw89_c2h_mlo_link_status {
4072 RTW89_C2H_MLO_LINK_CFG_IDLE = 0,
4073 RTW89_C2H_MLO_LINK_CFG_DONE = 1,
4074 RTW89_C2H_MLO_LINK_CFG_ISSUE_NULL_FAIL = 2,
4075 RTW89_C2H_MLO_LINK_CFG_TX_NULL_FAIL = 3,
4076 RTW89_C2H_MLO_LINK_CFG_ROLE_NOT_EXIST = 4,
4077 RTW89_C2H_MLO_LINK_CFG_NULL_1_TIMEOUT = 5,
4078 RTW89_C2H_MLO_LINK_CFG_NULL_0_TIMEOUT = 6,
4079 RTW89_C2H_MLO_LINK_CFG_RUNNING = 0xff,
4080 };
4081
4082 struct rtw89_mac_mrc_tsf_rpt {
4083 unsigned int num;
4084 u64 tsfs[RTW89_MAC_MRC_MAX_REQ_TSF_NUM];
4085 };
4086
4087 static_assert(sizeof(struct rtw89_mac_mrc_tsf_rpt) <= RTW89_COMPLETION_BUF_SIZE);
4088
4089 struct rtw89_c2h_mrc_tsf_rpt_info {
4090 __le32 tsf_low;
4091 __le32 tsf_high;
4092 } __packed;
4093
4094 struct rtw89_c2h_mrc_tsf_rpt {
4095 struct rtw89_c2h_hdr hdr;
4096 __le32 w2;
4097 struct rtw89_c2h_mrc_tsf_rpt_info infos[];
4098 } __packed;
4099
4100 #define RTW89_C2H_MRC_TSF_RPT_W2_REQ_TSF_NUM GENMASK(7, 0)
4101
4102 struct rtw89_c2h_mrc_status_rpt {
4103 struct rtw89_c2h_hdr hdr;
4104 __le32 w2;
4105 __le32 tsf_low;
4106 __le32 tsf_high;
4107 } __packed;
4108
4109 #define RTW89_C2H_MRC_STATUS_RPT_W2_STATUS GENMASK(5, 0)
4110 #define RTW89_C2H_MRC_STATUS_RPT_W2_SCH_IDX GENMASK(7, 6)
4111
4112 struct rtw89_c2h_pkt_ofld_rsp {
4113 __le32 w0;
4114 __le32 w1;
4115 __le32 w2;
4116 } __packed;
4117
4118 #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_ID GENMASK(7, 0)
4119 #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_OP GENMASK(10, 8)
4120 #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_LEN GENMASK(31, 16)
4121
4122 struct rtw89_c2h_tx_duty_rpt {
4123 struct rtw89_c2h_hdr c2h_hdr;
4124 __le32 w2;
4125 } __packed;
4126
4127 #define RTW89_C2H_TX_DUTY_RPT_W2_TIMER_ERR GENMASK(2, 0)
4128
4129 struct rtw89_c2h_wow_aoac_report {
4130 struct rtw89_c2h_hdr c2h_hdr;
4131 u8 rpt_ver;
4132 u8 sec_type;
4133 u8 key_idx;
4134 u8 pattern_idx;
4135 u8 rekey_ok;
4136 u8 rsvd1[3];
4137 u8 ptk_tx_iv[8];
4138 u8 eapol_key_replay_count[8];
4139 u8 gtk[32];
4140 u8 ptk_rx_iv[8];
4141 u8 gtk_rx_iv[4][8];
4142 __le64 igtk_key_id;
4143 __le64 igtk_ipn;
4144 u8 igtk[32];
4145 u8 csa_pri_ch;
4146 u8 csa_bw_ch_offset;
4147 u8 csa_ch_band_chsw_failed;
4148 u8 csa_rsvd1;
4149 } __packed;
4150
4151 #define RTW89_C2H_WOW_AOAC_RPT_REKEY_IDX BIT(0)
4152
4153 struct rtw89_c2h_pwr_int_notify {
4154 struct rtw89_c2h_hdr hdr;
4155 __le32 w2;
4156 } __packed;
4157
4158 #define RTW89_C2H_PWR_INT_NOTIFY_W2_MACID GENMASK(15, 0)
4159 #define RTW89_C2H_PWR_INT_NOTIFY_W2_PWR_STATUS BIT(16)
4160
4161 struct rtw89_h2c_tx_duty {
4162 __le32 w0;
4163 __le32 w1;
4164 } __packed;
4165
4166 #define RTW89_H2C_TX_DUTY_W0_PAUSE_INTVL_MASK GENMASK(15, 0)
4167 #define RTW89_H2C_TX_DUTY_W0_TX_INTVL_MASK GENMASK(31, 16)
4168 #define RTW89_H2C_TX_DUTY_W1_STOP BIT(0)
4169
4170 struct rtw89_h2c_bcnfltr {
4171 __le32 w0;
4172 } __packed;
4173
4174 #define RTW89_H2C_BCNFLTR_W0_MON_RSSI BIT(0)
4175 #define RTW89_H2C_BCNFLTR_W0_MON_BCN BIT(1)
4176 #define RTW89_H2C_BCNFLTR_W0_MON_EN BIT(2)
4177 #define RTW89_H2C_BCNFLTR_W0_MODE GENMASK(4, 3)
4178 #define RTW89_H2C_BCNFLTR_W0_BCN_LOSS_CNT_H3 GENMASK(7, 5)
4179 #define RTW89_H2C_BCNFLTR_W0_BCN_LOSS_CNT_L4 GENMASK(11, 8)
4180 #define RTW89_H2C_BCNFLTR_W0_RSSI_HYST GENMASK(15, 12)
4181 #define RTW89_H2C_BCNFLTR_W0_RSSI_THRESHOLD GENMASK(23, 16)
4182 #define RTW89_H2C_BCNFLTR_W0_MAC_ID GENMASK(31, 24)
4183
4184 struct rtw89_h2c_ofld_rssi {
4185 __le32 w0;
4186 __le32 w1;
4187 } __packed;
4188
4189 #define RTW89_H2C_OFLD_RSSI_W0_MACID GENMASK(7, 0)
4190 #define RTW89_H2C_OFLD_RSSI_W0_NUM GENMASK(15, 8)
4191 #define RTW89_H2C_OFLD_RSSI_W1_VAL GENMASK(7, 0)
4192
4193 struct rtw89_h2c_ofld {
4194 __le32 w0;
4195 } __packed;
4196
4197 #define RTW89_H2C_OFLD_W0_MAC_ID GENMASK(7, 0)
4198 #define RTW89_H2C_OFLD_W0_TX_TP GENMASK(17, 8)
4199 #define RTW89_H2C_OFLD_W0_RX_TP GENMASK(27, 18)
4200
4201 #define RTW89_MFW_SIG 0xFF
4202
4203 struct rtw89_mfw_info {
4204 u8 cv;
4205 u8 type; /* enum rtw89_fw_type */
4206 u8 mp;
4207 u8 rsvd;
4208 __le32 shift;
4209 __le32 size;
4210 u8 rsvd2[4];
4211 } __packed;
4212
4213 struct rtw89_mfw_hdr {
4214 u8 sig; /* RTW89_MFW_SIG */
4215 u8 fw_nr;
4216 u8 rsvd0[2];
4217 struct {
4218 u8 major;
4219 u8 minor;
4220 u8 sub;
4221 u8 idx;
4222 } ver;
4223 u8 rsvd1[8];
4224 struct rtw89_mfw_info info[];
4225 } __packed;
4226
4227 struct rtw89_fw_logsuit_hdr {
4228 __le32 rsvd;
4229 __le32 count;
4230 __le32 ids[];
4231 } __packed;
4232
4233 #define RTW89_FW_ELEMENT_ALIGN 16
4234
4235 enum rtw89_fw_element_id {
4236 RTW89_FW_ELEMENT_ID_BBMCU0 = 0,
4237 RTW89_FW_ELEMENT_ID_BBMCU1 = 1,
4238 RTW89_FW_ELEMENT_ID_BB_REG = 2,
4239 RTW89_FW_ELEMENT_ID_BB_GAIN = 3,
4240 RTW89_FW_ELEMENT_ID_RADIO_A = 4,
4241 RTW89_FW_ELEMENT_ID_RADIO_B = 5,
4242 RTW89_FW_ELEMENT_ID_RADIO_C = 6,
4243 RTW89_FW_ELEMENT_ID_RADIO_D = 7,
4244 RTW89_FW_ELEMENT_ID_RF_NCTL = 8,
4245 RTW89_FW_ELEMENT_ID_TXPWR_BYRATE = 9,
4246 RTW89_FW_ELEMENT_ID_TXPWR_LMT_2GHZ = 10,
4247 RTW89_FW_ELEMENT_ID_TXPWR_LMT_5GHZ = 11,
4248 RTW89_FW_ELEMENT_ID_TXPWR_LMT_6GHZ = 12,
4249 RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_2GHZ = 13,
4250 RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_5GHZ = 14,
4251 RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_6GHZ = 15,
4252 RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT = 16,
4253 RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT_RU = 17,
4254 RTW89_FW_ELEMENT_ID_TXPWR_TRK = 18,
4255 RTW89_FW_ELEMENT_ID_RFKLOG_FMT = 19,
4256 RTW89_FW_ELEMENT_ID_REGD = 20,
4257 RTW89_FW_ELEMENT_ID_TXPWR_DA_LMT_2GHZ = 21,
4258 RTW89_FW_ELEMENT_ID_TXPWR_DA_LMT_5GHZ = 22,
4259 RTW89_FW_ELEMENT_ID_TXPWR_DA_LMT_6GHZ = 23,
4260 RTW89_FW_ELEMENT_ID_TXPWR_DA_LMT_RU_2GHZ = 24,
4261 RTW89_FW_ELEMENT_ID_TXPWR_DA_LMT_RU_5GHZ = 25,
4262 RTW89_FW_ELEMENT_ID_TXPWR_DA_LMT_RU_6GHZ = 26,
4263 RTW89_FW_ELEMENT_ID_AFE_PWR_SEQ = 27,
4264 RTW89_FW_ELEMENT_ID_DIAG_MAC = 28,
4265 RTW89_FW_ELEMENT_ID_TX_COMP = 29,
4266
4267 RTW89_FW_ELEMENT_ID_NUM,
4268 };
4269
4270 #define BITS_OF_RTW89_TXPWR_FW_ELEMENTS_NO_6GHZ \
4271 (BIT(RTW89_FW_ELEMENT_ID_TXPWR_BYRATE) | \
4272 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_2GHZ) | \
4273 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_5GHZ) | \
4274 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_2GHZ) | \
4275 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_5GHZ) | \
4276 BIT(RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT) | \
4277 BIT(RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT_RU))
4278
4279 #define BITS_OF_RTW89_TXPWR_FW_ELEMENTS \
4280 (BITS_OF_RTW89_TXPWR_FW_ELEMENTS_NO_6GHZ | \
4281 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_6GHZ) | \
4282 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_6GHZ))
4283
4284 #define RTW89_AX_GEN_DEF_NEEDED_FW_ELEMENTS_NO_6GHZ \
4285 (BIT(RTW89_FW_ELEMENT_ID_BB_REG) | \
4286 BIT(RTW89_FW_ELEMENT_ID_RADIO_A) | \
4287 BIT(RTW89_FW_ELEMENT_ID_RADIO_B) | \
4288 BIT(RTW89_FW_ELEMENT_ID_RF_NCTL) | \
4289 BIT(RTW89_FW_ELEMENT_ID_TXPWR_TRK) | \
4290 BITS_OF_RTW89_TXPWR_FW_ELEMENTS_NO_6GHZ)
4291
4292 #define RTW89_BE_GEN_DEF_NEEDED_FW_ELEMENTS (BIT(RTW89_FW_ELEMENT_ID_BBMCU0) | \
4293 BIT(RTW89_FW_ELEMENT_ID_BB_REG) | \
4294 BIT(RTW89_FW_ELEMENT_ID_RADIO_A) | \
4295 BIT(RTW89_FW_ELEMENT_ID_RADIO_B) | \
4296 BIT(RTW89_FW_ELEMENT_ID_RF_NCTL) | \
4297 BIT(RTW89_FW_ELEMENT_ID_TXPWR_TRK) | \
4298 BITS_OF_RTW89_TXPWR_FW_ELEMENTS)
4299
4300 struct __rtw89_fw_txpwr_element {
4301 u8 rsvd0;
4302 u8 rsvd1;
4303 u8 rfe_type;
4304 u8 ent_sz;
4305 __le32 num_ents;
4306 u8 content[];
4307 } __packed;
4308
4309 struct __rtw89_fw_regd_element {
4310 u8 rsvd0;
4311 u8 rsvd1;
4312 u8 rsvd2;
4313 u8 ent_sz;
4314 __le32 num_ents;
4315 u8 content[];
4316 } __packed;
4317
4318 enum rtw89_fw_txpwr_trk_type {
4319 __RTW89_FW_TXPWR_TRK_TYPE_6GHZ_START = 0,
4320 RTW89_FW_TXPWR_TRK_TYPE_6GB_N = 0,
4321 RTW89_FW_TXPWR_TRK_TYPE_6GB_P = 1,
4322 RTW89_FW_TXPWR_TRK_TYPE_6GA_N = 2,
4323 RTW89_FW_TXPWR_TRK_TYPE_6GA_P = 3,
4324 __RTW89_FW_TXPWR_TRK_TYPE_6GHZ_MAX = 3,
4325
4326 __RTW89_FW_TXPWR_TRK_TYPE_5GHZ_START = 4,
4327 RTW89_FW_TXPWR_TRK_TYPE_5GB_N = 4,
4328 RTW89_FW_TXPWR_TRK_TYPE_5GB_P = 5,
4329 RTW89_FW_TXPWR_TRK_TYPE_5GA_N = 6,
4330 RTW89_FW_TXPWR_TRK_TYPE_5GA_P = 7,
4331 __RTW89_FW_TXPWR_TRK_TYPE_5GHZ_MAX = 7,
4332
4333 __RTW89_FW_TXPWR_TRK_TYPE_2GHZ_START = 8,
4334 RTW89_FW_TXPWR_TRK_TYPE_2GB_N = 8,
4335 RTW89_FW_TXPWR_TRK_TYPE_2GB_P = 9,
4336 RTW89_FW_TXPWR_TRK_TYPE_2GA_N = 10,
4337 RTW89_FW_TXPWR_TRK_TYPE_2GA_P = 11,
4338 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_N = 12,
4339 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_P = 13,
4340 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_N = 14,
4341 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_P = 15,
4342 __RTW89_FW_TXPWR_TRK_TYPE_2GHZ_MAX = 15,
4343
4344 RTW89_FW_TXPWR_TRK_TYPE_NR,
4345 };
4346
4347 struct rtw89_fw_txpwr_track_cfg {
4348 const s8 (*delta[RTW89_FW_TXPWR_TRK_TYPE_NR])[DELTA_SWINGIDX_SIZE];
4349 };
4350
4351 #define RTW89_DEFAULT_NEEDED_FW_TXPWR_TRK_6GHZ \
4352 (BIT(RTW89_FW_TXPWR_TRK_TYPE_6GB_N) | \
4353 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GB_P) | \
4354 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GA_N) | \
4355 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GA_P))
4356 #define RTW89_DEFAULT_NEEDED_FW_TXPWR_TRK_5GHZ \
4357 (BIT(RTW89_FW_TXPWR_TRK_TYPE_5GB_N) | \
4358 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GB_P) | \
4359 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GA_N) | \
4360 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GA_P))
4361 #define RTW89_DEFAULT_NEEDED_FW_TXPWR_TRK_2GHZ \
4362 (BIT(RTW89_FW_TXPWR_TRK_TYPE_2GB_N) | \
4363 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GB_P) | \
4364 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GA_N) | \
4365 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GA_P) | \
4366 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_N) | \
4367 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_P) | \
4368 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_N) | \
4369 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_P))
4370
4371 enum rtw89_fw_afe_action {
4372 RTW89_FW_AFE_ACTION_WRITE = 0,
4373 RTW89_FW_AFE_ACTION_DELAY = 1,
4374 RTW89_FW_AFE_ACTION_POLL = 2,
4375 };
4376
4377 enum rtw89_fw_afe_cat {
4378 RTW89_FW_AFE_CAT_BB = 0,
4379 RTW89_FW_AFE_CAT_BB1 = 1,
4380 RTW89_FW_AFE_CAT_MAC = 2,
4381 RTW89_FW_AFE_CAT_MAC1 = 3,
4382 RTW89_FW_AFE_CAT_AFEDIG = 4,
4383 RTW89_FW_AFE_CAT_AFEDIG1 = 5,
4384 };
4385
4386 enum rtw89_fw_afe_class {
4387 RTW89_FW_AFE_CLASS_P0 = 0,
4388 RTW89_FW_AFE_CLASS_P1 = 1,
4389 RTW89_FW_AFE_CLASS_P2 = 2,
4390 RTW89_FW_AFE_CLASS_P3 = 3,
4391 RTW89_FW_AFE_CLASS_P4 = 4,
4392 RTW89_FW_AFE_CLASS_CMN = 5,
4393 };
4394
4395 struct rtw89_fw_element_hdr {
4396 __le32 id; /* enum rtw89_fw_element_id */
4397 __le32 size; /* exclude header size */
4398 u8 ver[4];
4399 __le16 aid; /* should match rtw89_hal::aid */
4400 __le16 rsvd0;
4401 __le32 rsvd1;
4402 __le32 rsvd2;
4403 union {
4404 struct {
4405 u8 priv[8];
4406 u8 contents[];
4407 } __packed common;
4408 struct {
4409 u8 idx;
4410 u8 rsvd[7];
4411 struct {
4412 __le32 addr;
4413 __le32 data;
4414 } __packed regs[];
4415 } __packed reg2;
4416 struct {
4417 u8 cv;
4418 u8 priv[7];
4419 u8 contents[];
4420 } __packed bbmcu;
4421 struct {
4422 __le32 bitmap; /* bitmap of enum rtw89_fw_txpwr_trk_type */
4423 __le32 rsvd;
4424 s8 contents[][DELTA_SWINGIDX_SIZE];
4425 } __packed txpwr_trk;
4426 struct {
4427 u8 nr;
4428 u8 rsvd[3];
4429 u8 rfk_id; /* enum rtw89_phy_c2h_rfk_log_func */
4430 u8 rsvd1[3];
4431 __le16 offset[];
4432 } __packed rfk_log_fmt;
4433 struct {
4434 u8 rsvd[8];
4435 struct rtw89_phy_afe_info {
4436 __le32 action; /* enum rtw89_fw_afe_action */
4437 __le32 cat; /* enum rtw89_fw_afe_cat */
4438 __le32 class; /* enum rtw89_fw_afe_class */
4439 __le32 addr;
4440 __le32 mask;
4441 __le32 val;
4442 } __packed infos[];
4443 } __packed afe;
4444 struct {
4445 __le32 rule_size;
4446 u8 rsvd[4];
4447 u8 rules_and_msgs[];
4448 } __packed diag_mac;
4449 struct __rtw89_fw_txpwr_element txpwr;
4450 struct __rtw89_fw_regd_element regd;
4451 } __packed u;
4452 } __packed;
4453
4454 struct fwcmd_hdr {
4455 __le32 hdr0;
4456 __le32 hdr1;
4457 };
4458
4459 union rtw89_compat_fw_hdr {
4460 struct rtw89_mfw_hdr mfw_hdr;
4461 struct rtw89_fw_hdr fw_hdr;
4462 };
4463
rtw89_compat_fw_hdr_ver_code(const void * fw_buf)4464 static inline u32 rtw89_compat_fw_hdr_ver_code(const void *fw_buf)
4465 {
4466 const union rtw89_compat_fw_hdr *compat = (typeof(compat))fw_buf;
4467
4468 if (compat->mfw_hdr.sig == RTW89_MFW_SIG)
4469 return RTW89_MFW_HDR_VER_CODE(&compat->mfw_hdr);
4470 else
4471 return RTW89_FW_HDR_VER_CODE(&compat->fw_hdr);
4472 }
4473
rtw89_fw_get_filename(char * buf,size_t size,const char * fw_basename,int fw_format)4474 static inline void rtw89_fw_get_filename(char *buf, size_t size,
4475 const char *fw_basename, int fw_format)
4476 {
4477 if (fw_format <= 0)
4478 snprintf(buf, size, "%s.bin", fw_basename);
4479 else
4480 snprintf(buf, size, "%s-%d.bin", fw_basename, fw_format);
4481 }
4482
4483 #define RTW89_H2C_RF_PAGE_SIZE 500
4484 #define RTW89_H2C_RF_PAGE_NUM 3
4485 struct rtw89_fw_h2c_rf_reg_info {
4486 enum rtw89_rf_path rf_path;
4487 __le32 rtw89_phy_config_rf_h2c[RTW89_H2C_RF_PAGE_NUM][RTW89_H2C_RF_PAGE_SIZE];
4488 u16 curr_idx;
4489 };
4490
4491 #define H2C_SEC_CAM_LEN 24
4492
4493 #define H2C_HEADER_LEN 8
4494 #define H2C_HDR_CAT GENMASK(1, 0)
4495 #define H2C_HDR_CLASS GENMASK(7, 2)
4496 #define H2C_HDR_FUNC GENMASK(15, 8)
4497 #define H2C_HDR_DEL_TYPE GENMASK(19, 16)
4498 #define H2C_HDR_H2C_SEQ GENMASK(31, 24)
4499 #define H2C_HDR_TOTAL_LEN GENMASK(13, 0)
4500 #define H2C_HDR_REC_ACK BIT(14)
4501 #define H2C_HDR_DONE_ACK BIT(15)
4502
4503 #define FWCMD_TYPE_H2C 0
4504
4505 #define H2C_CAT_TEST 0x0
4506
4507 /* CLASS 5 - FW STATUS TEST */
4508 #define H2C_CL_FW_STATUS_TEST 0x5
4509 #define H2C_FUNC_CPU_EXCEPTION 0x1
4510
4511 #define H2C_CAT_MAC 0x1
4512
4513 /* CLASS 0 - FW INFO */
4514 #define H2C_CL_FW_INFO 0x0
4515 #define H2C_FUNC_LOG_CFG 0x0
4516 #define H2C_FUNC_MAC_GENERAL_PKT 0x1
4517
4518 /* CLASS 1 - WOW */
4519 #define H2C_CL_MAC_WOW 0x1
4520 enum rtw89_wow_h2c_func {
4521 H2C_FUNC_KEEP_ALIVE = 0x0,
4522 H2C_FUNC_DISCONNECT_DETECT = 0x1,
4523 H2C_FUNC_WOW_GLOBAL = 0x2,
4524 H2C_FUNC_GTK_OFLD = 0x3,
4525 H2C_FUNC_ARP_OFLD = 0x4,
4526 H2C_FUNC_NLO = 0x7,
4527 H2C_FUNC_WAKEUP_CTRL = 0x8,
4528 H2C_FUNC_WOW_CAM_UPD = 0xC,
4529 H2C_FUNC_AOAC_REPORT_REQ = 0xD,
4530 H2C_FUNC_WOW_PLD_CAM_UPD = 0x12,
4531
4532 NUM_OF_RTW89_WOW_H2C_FUNC,
4533 };
4534
4535 #define RTW89_WOW_WAIT_COND(tag, func) \
4536 ((tag) * NUM_OF_RTW89_WOW_H2C_FUNC + (func))
4537
4538 #define RTW89_WOW_WAIT_COND_AOAC \
4539 RTW89_WOW_WAIT_COND(0 /* don't care */, H2C_FUNC_AOAC_REPORT_REQ)
4540
4541 /* CLASS 2 - PS */
4542 #define H2C_CL_MAC_PS 0x2
4543 enum rtw89_ps_h2c_func {
4544 H2C_FUNC_MAC_LPS_PARM = 0x0,
4545 H2C_FUNC_P2P_ACT = 0x1,
4546 H2C_FUNC_IPS_CFG = 0x3,
4547 H2C_FUNC_PS_POWER_LEVEL = 0x7,
4548 H2C_FUNC_TBTT_TUNING = 0xA,
4549
4550 NUM_OF_RTW89_PS_H2C_FUNC,
4551 };
4552
4553 #define RTW89_PS_WAIT_COND(tag, func) \
4554 ((tag) * NUM_OF_RTW89_PS_H2C_FUNC + (func))
4555
4556 #define RTW89_PS_WAIT_COND_IPS_CFG \
4557 RTW89_PS_WAIT_COND(0 /* don't care */, H2C_FUNC_IPS_CFG)
4558
4559 /* CLASS 3 - FW download */
4560 #define H2C_CL_MAC_FWDL 0x3
4561 #define H2C_FUNC_MAC_FWHDR_DL 0x0
4562
4563 /* CLASS 5 - Frame Exchange */
4564 #define H2C_CL_MAC_FR_EXCHG 0x5
4565 #define H2C_FUNC_MAC_CCTLINFO_UD 0x2
4566 #define H2C_FUNC_MAC_BCN_UPD 0x5
4567 #define H2C_FUNC_MAC_DCTLINFO_UD_V1 0x9
4568 #define H2C_FUNC_MAC_CCTLINFO_UD_V1 0xa
4569 #define H2C_FUNC_MAC_DCTLINFO_UD_V2 0xc
4570 #define H2C_FUNC_MAC_BCN_UPD_BE 0xd
4571 #define H2C_FUNC_MAC_DCTLINFO_UD_V3 0x10
4572 #define H2C_FUNC_MAC_CCTLINFO_UD_G7 0x11
4573
4574 /* CLASS 6 - Address CAM */
4575 #define H2C_CL_MAC_ADDR_CAM_UPDATE 0x6
4576 #define H2C_FUNC_MAC_ADDR_CAM_UPD 0x0
4577
4578 /* CLASS 8 - Media Status Report */
4579 #define H2C_CL_MAC_MEDIA_RPT 0x8
4580 #define H2C_FUNC_MAC_JOININFO 0x0
4581 #define H2C_FUNC_MAC_FWROLE_MAINTAIN 0x4
4582 #define H2C_FUNC_NOTIFY_DBCC 0x5
4583
4584 /* CLASS 9 - FW offload */
4585 #define H2C_CL_MAC_FW_OFLD 0x9
4586 enum rtw89_fw_ofld_h2c_func {
4587 H2C_FUNC_PACKET_OFLD = 0x1,
4588 H2C_FUNC_MAC_MACID_PAUSE = 0x8,
4589 H2C_FUNC_USR_EDCA = 0xF,
4590 H2C_FUNC_TSF32_TOGL = 0x10,
4591 H2C_FUNC_OFLD_CFG = 0x14,
4592 H2C_FUNC_ADD_SCANOFLD_CH = 0x16,
4593 H2C_FUNC_SCANOFLD = 0x17,
4594 H2C_FUNC_TX_DUTY = 0x18,
4595 H2C_FUNC_PKT_DROP = 0x1b,
4596 H2C_FUNC_CFG_BCNFLTR = 0x1e,
4597 H2C_FUNC_OFLD_RSSI = 0x1f,
4598 H2C_FUNC_OFLD_TP = 0x20,
4599 H2C_FUNC_MAC_MACID_PAUSE_SLEEP = 0x28,
4600 H2C_FUNC_SCANOFLD_BE = 0x2c,
4601
4602 NUM_OF_RTW89_FW_OFLD_H2C_FUNC,
4603 };
4604
4605 #define RTW89_FW_OFLD_WAIT_COND(tag, func) \
4606 ((tag) * NUM_OF_RTW89_FW_OFLD_H2C_FUNC + (func))
4607
4608 #define RTW89_FW_OFLD_WAIT_COND_PKT_OFLD(pkt_id, pkt_op) \
4609 RTW89_FW_OFLD_WAIT_COND(RTW89_PKT_OFLD_WAIT_TAG(pkt_id, pkt_op), \
4610 H2C_FUNC_PACKET_OFLD)
4611
4612 #define RTW89_SCANOFLD_WAIT_COND_ADD_CH RTW89_FW_OFLD_WAIT_COND(0, H2C_FUNC_ADD_SCANOFLD_CH)
4613
4614 #define RTW89_SCANOFLD_WAIT_COND_START RTW89_FW_OFLD_WAIT_COND(0, H2C_FUNC_SCANOFLD)
4615 #define RTW89_SCANOFLD_WAIT_COND_STOP RTW89_FW_OFLD_WAIT_COND(1, H2C_FUNC_SCANOFLD)
4616 #define RTW89_SCANOFLD_BE_WAIT_COND_START RTW89_FW_OFLD_WAIT_COND(0, H2C_FUNC_SCANOFLD_BE)
4617 #define RTW89_SCANOFLD_BE_WAIT_COND_STOP RTW89_FW_OFLD_WAIT_COND(1, H2C_FUNC_SCANOFLD_BE)
4618
4619
4620 /* CLASS 10 - Security CAM */
4621 #define H2C_CL_MAC_SEC_CAM 0xa
4622 #define H2C_FUNC_MAC_SEC_UPD 0x1
4623
4624 /* CLASS 12 - BA CAM */
4625 #define H2C_CL_BA_CAM 0xc
4626 #define H2C_FUNC_MAC_BA_CAM 0x0
4627 #define H2C_FUNC_MAC_BA_CAM_V1 0x1
4628 #define H2C_FUNC_MAC_BA_CAM_INIT 0x2
4629
4630 /* CLASS 14 - MCC */
4631 #define H2C_CL_MCC 0xe
4632 enum rtw89_mcc_h2c_func {
4633 H2C_FUNC_ADD_MCC = 0x0,
4634 H2C_FUNC_START_MCC = 0x1,
4635 H2C_FUNC_STOP_MCC = 0x2,
4636 H2C_FUNC_DEL_MCC_GROUP = 0x3,
4637 H2C_FUNC_RESET_MCC_GROUP = 0x4,
4638 H2C_FUNC_MCC_REQ_TSF = 0x5,
4639 H2C_FUNC_MCC_MACID_BITMAP = 0x6,
4640 H2C_FUNC_MCC_SYNC = 0x7,
4641 H2C_FUNC_MCC_SET_DURATION = 0x8,
4642
4643 NUM_OF_RTW89_MCC_H2C_FUNC,
4644 };
4645
4646 #define RTW89_MCC_WAIT_COND(group, func) \
4647 ((group) * NUM_OF_RTW89_MCC_H2C_FUNC + (func))
4648
4649 /* CLASS 20 - MLO */
4650 #define H2C_CL_MLO 0x14
4651 enum rtw89_mlo_h2c_func {
4652 H2C_FUNC_MLO_TBL_CFG = 0x0,
4653 H2C_FUNC_MLO_STA_CFG = 0x1,
4654 H2C_FUNC_MLO_TTLM = 0x2,
4655 H2C_FUNC_MLO_DM_CFG = 0x3,
4656 H2C_FUNC_MLO_EMLSR_STA_CFG = 0x4,
4657 H2C_FUNC_MLO_MCMLO_RELINK_DROP = 0x5,
4658 H2C_FUNC_MLO_MCMLO_SN_SYNC = 0x6,
4659 H2C_FUNC_MLO_RELINK = 0x7,
4660 H2C_FUNC_MLO_LINK_CFG = 0x8,
4661 H2C_FUNC_MLO_DM_DBG = 0x9,
4662
4663 NUM_OF_RTW89_MLO_H2C_FUNC,
4664 };
4665
4666 #define RTW89_MLO_WAIT_COND(macid, func) \
4667 ((macid) * NUM_OF_RTW89_MLO_H2C_FUNC + (func))
4668
4669 /* CLASS 24 - MRC */
4670 #define H2C_CL_MRC 0x18
4671 enum rtw89_mrc_h2c_func {
4672 H2C_FUNC_MRC_REQ_TSF = 0x0,
4673 H2C_FUNC_ADD_MRC = 0x1,
4674 H2C_FUNC_START_MRC = 0x2,
4675 H2C_FUNC_DEL_MRC = 0x3,
4676 H2C_FUNC_MRC_SYNC = 0x4,
4677 H2C_FUNC_MRC_UPD_DURATION = 0x5,
4678 H2C_FUNC_MRC_UPD_BITMAP = 0x6,
4679
4680 NUM_OF_RTW89_MRC_H2C_FUNC,
4681 };
4682
4683 /* can consider MRC's sch_idx as MCC's group */
4684 #define RTW89_MRC_WAIT_COND(sch_idx, func) \
4685 ((sch_idx) * NUM_OF_RTW89_MRC_H2C_FUNC + (func))
4686
4687 #define RTW89_MRC_WAIT_COND_REQ_TSF \
4688 RTW89_MRC_WAIT_COND(0 /* don't care */, H2C_FUNC_MRC_REQ_TSF)
4689
4690 /* CLASS 36 - AP */
4691 #define H2C_CL_AP 0x24
4692 #define H2C_FUNC_AP_INFO 0x0
4693
4694 #define H2C_CAT_OUTSRC 0x2
4695
4696 #define H2C_CL_OUTSRC_RA 0x1
4697 #define H2C_FUNC_OUTSRC_RA_MACIDCFG 0x0
4698
4699 #define H2C_CL_OUTSRC_DM 0x2
4700 #define H2C_FUNC_FW_MCC_DIG 0x6
4701 #define H2C_FUNC_FW_LPS_CH_INFO 0xb
4702 #define H2C_FUNC_FW_LPS_ML_CMN_INFO 0xe
4703
4704 #define H2C_CL_OUTSRC_RF_REG_A 0x8
4705 #define H2C_CL_OUTSRC_RF_REG_B 0x9
4706 #define H2C_CL_OUTSRC_RF_FW_NOTIFY 0xa
4707 #define H2C_FUNC_OUTSRC_RF_GET_MCCCH 0x2
4708 #define H2C_FUNC_OUTSRC_RF_MCC_INFO 0xf
4709 #define H2C_FUNC_OUTSRC_RF_PS_INFO 0x10
4710 #define H2C_CL_OUTSRC_RF_FW_RFK 0xb
4711
4712 enum rtw89_rfk_offload_h2c_func {
4713 H2C_FUNC_RFK_TSSI_OFFLOAD = 0x0,
4714 H2C_FUNC_RFK_IQK_OFFLOAD = 0x1,
4715 H2C_FUNC_RFK_DPK_OFFLOAD = 0x3,
4716 H2C_FUNC_RFK_TXGAPK_OFFLOAD = 0x4,
4717 H2C_FUNC_RFK_DACK_OFFLOAD = 0x5,
4718 H2C_FUNC_RFK_RXDCK_OFFLOAD = 0x6,
4719 H2C_FUNC_RFK_PRE_NOTIFY = 0x8,
4720 H2C_FUNC_RFK_TAS_OFFLOAD = 0x9,
4721 H2C_FUNC_RFK_TXIQK_OFFOAD = 0xc,
4722 H2C_FUNC_RFK_CIM3K_OFFOAD = 0xe,
4723 };
4724
4725 struct rtw89_fw_h2c_rf_get_mccch {
4726 __le32 ch_0_0;
4727 __le32 ch_0_1;
4728 __le32 ch_1_0;
4729 __le32 ch_1_1;
4730 __le32 current_channel;
4731 } __packed;
4732
4733 struct rtw89_fw_h2c_rf_get_mccch_v0 {
4734 __le32 ch_0;
4735 __le32 ch_1;
4736 __le32 band_0;
4737 __le32 band_1;
4738 __le32 current_channel;
4739 __le32 current_band_type;
4740 } __packed;
4741
4742 struct rtw89_h2c_mcc_dig {
4743 __le32 w0;
4744 __le32 w1;
4745 __le32 w2;
4746 } __packed;
4747
4748 #define RTW89_H2C_MCC_DIG_W0_REG_CNT GENMASK(7, 0)
4749 #define RTW89_H2C_MCC_DIG_W0_DM_EN BIT(8)
4750 #define RTW89_H2C_MCC_DIG_W0_IDX GENMASK(10, 9)
4751 #define RTW89_H2C_MCC_DIG_W0_SET BIT(11)
4752 #define RTW89_H2C_MCC_DIG_W0_PHY0_EN BIT(12)
4753 #define RTW89_H2C_MCC_DIG_W0_PHY1_EN BIT(13)
4754 #define RTW89_H2C_MCC_DIG_W0_CENTER_CH GENMASK(23, 16)
4755 #define RTW89_H2C_MCC_DIG_W0_BAND_TYPE GENMASK(31, 24)
4756 #define RTW89_H2C_MCC_DIG_W1_ADDR_LSB GENMASK(7, 0)
4757 #define RTW89_H2C_MCC_DIG_W1_ADDR_MSB GENMASK(15, 8)
4758 #define RTW89_H2C_MCC_DIG_W1_BMASK_LSB GENMASK(23, 16)
4759 #define RTW89_H2C_MCC_DIG_W1_BMASK_MSB GENMASK(31, 24)
4760 #define RTW89_H2C_MCC_DIG_W2_VAL_LSB GENMASK(7, 0)
4761 #define RTW89_H2C_MCC_DIG_W2_VAL_MSB GENMASK(15, 8)
4762
4763 #define NUM_OF_RTW89_FW_RFK_PATH 2
4764 #define NUM_OF_RTW89_FW_RFK_TBL 3
4765
4766 struct rtw89_h2c_rf_ps_info {
4767 __le32 rf18[NUM_OF_RTW89_FW_RFK_PATH];
4768 __le32 mlo_mode;
4769 u8 pri_ch[NUM_OF_RTW89_FW_RFK_PATH];
4770 } __packed;
4771
4772 struct rtw89_fw_h2c_rfk_pre_info_common {
4773 struct {
4774 __le32 ch[NUM_OF_RTW89_FW_RFK_PATH][NUM_OF_RTW89_FW_RFK_TBL];
4775 __le32 band[NUM_OF_RTW89_FW_RFK_PATH][NUM_OF_RTW89_FW_RFK_TBL];
4776 } __packed dbcc;
4777
4778 __le32 mlo_mode;
4779 struct {
4780 __le32 cur_ch[NUM_OF_RTW89_FW_RFK_PATH];
4781 __le32 cur_band[NUM_OF_RTW89_FW_RFK_PATH];
4782 } __packed tbl;
4783
4784 __le32 phy_idx;
4785 } __packed;
4786
4787 struct rtw89_fw_h2c_rfk_pre_info_v0 {
4788 struct rtw89_fw_h2c_rfk_pre_info_common common;
4789
4790 __le32 cur_band;
4791 __le32 cur_bw;
4792 __le32 cur_center_ch;
4793
4794 __le32 ktbl_sel0;
4795 __le32 ktbl_sel1;
4796 __le32 rfmod0;
4797 __le32 rfmod1;
4798
4799 __le32 mlo_1_1;
4800 __le32 rfe_type;
4801 __le32 drv_mode;
4802
4803 struct {
4804 __le32 ch[NUM_OF_RTW89_FW_RFK_PATH];
4805 __le32 band[NUM_OF_RTW89_FW_RFK_PATH];
4806 } __packed mlo;
4807 } __packed;
4808
4809 struct rtw89_fw_h2c_rfk_pre_info_v1 {
4810 struct rtw89_fw_h2c_rfk_pre_info_common common;
4811 __le32 mlo_1_1;
4812 } __packed;
4813
4814 struct rtw89_fw_h2c_rfk_pre_info_v2 {
4815 struct rtw89_fw_h2c_rfk_pre_info_v1 base_v1;
4816 __le32 cur_bandwidth[NUM_OF_RTW89_FW_RFK_PATH];
4817 } __packed;
4818
4819 struct rtw89_fw_h2c_rfk_pre_info {
4820 __le32 mlo_mode;
4821 __le32 phy_idx;
4822 __le32 mlo_1_1;
4823 } __packed;
4824
4825 struct rtw89_fw_h2c_rfk_pre_info_mcc_v0 {
4826 __le32 tbl_18[NUM_OF_RTW89_FW_RFK_TBL][NUM_OF_RTW89_FW_RFK_PATH];
4827 __le32 cur_18[NUM_OF_RTW89_FW_RFK_PATH];
4828 __le32 mlo_mode;
4829 } __packed;
4830
4831 struct rtw89_fw_h2c_rfk_pre_info_mcc_v1 {
4832 __le32 tbl_18[NUM_OF_RTW89_FW_RFK_TBL];
4833 __le32 cur_18[NUM_OF_RTW89_FW_RFK_PATH];
4834 __le32 mlo_mode;
4835 __le32 mlo_1_1;
4836 u8 phy_idx;
4837 u8 tbl_idx;
4838 } __packed;
4839
4840 struct rtw89_fw_h2c_rfk_pre_info_mcc {
4841 struct rtw89_fw_h2c_rfk_pre_info_mcc_v1 base;
4842 u8 rsvd[2];
4843 __le32 aid;
4844 } __packed;
4845
4846 struct rtw89_h2c_rf_tssi {
4847 __le16 len;
4848 u8 phy;
4849 u8 ch;
4850 u8 bw;
4851 u8 band;
4852 u8 hwtx_en;
4853 u8 cv;
4854 s8 curr_tssi_cck_de[2];
4855 s8 curr_tssi_cck_de_20m[2];
4856 s8 curr_tssi_cck_de_40m[2];
4857 s8 curr_tssi_efuse_cck_de[2];
4858 s8 curr_tssi_ofdm_de[2];
4859 s8 curr_tssi_ofdm_de_20m[2];
4860 s8 curr_tssi_ofdm_de_40m[2];
4861 s8 curr_tssi_ofdm_de_80m[2];
4862 s8 curr_tssi_ofdm_de_160m[2];
4863 s8 curr_tssi_ofdm_de_320m[2];
4864 s8 curr_tssi_efuse_ofdm_de[2];
4865 s8 curr_tssi_ofdm_de_diff_20m[2];
4866 s8 curr_tssi_ofdm_de_diff_80m[2];
4867 s8 curr_tssi_ofdm_de_diff_160m[2];
4868 s8 curr_tssi_ofdm_de_diff_320m[2];
4869 s8 curr_tssi_trim_de[2];
4870 u8 pg_thermal[2];
4871 u8 ftable[2][128];
4872 u8 tssi_mode;
4873 u8 rfe_type;
4874 } __packed;
4875
4876 struct rtw89_h2c_rf_iqk_v0 {
4877 __le32 phy_idx;
4878 __le32 dbcc;
4879 } __packed;
4880
4881 struct rtw89_h2c_rf_iqk {
4882 u8 len;
4883 u8 ktype;
4884 u8 phy;
4885 u8 kpath;
4886 u8 band;
4887 u8 bw;
4888 u8 ch;
4889 u8 cv;
4890 } __packed;
4891
4892 struct rtw89_h2c_rf_dpk {
4893 u8 len;
4894 u8 phy;
4895 u8 dpk_enable;
4896 u8 kpath;
4897 u8 cur_band;
4898 u8 cur_bw;
4899 u8 cur_ch;
4900 u8 dpk_dbg_en;
4901 } __packed;
4902
4903 struct rtw89_h2c_rf_txgapk {
4904 u8 len;
4905 u8 ktype;
4906 u8 phy;
4907 u8 kpath;
4908 u8 band;
4909 u8 bw;
4910 u8 ch;
4911 u8 cv;
4912 } __packed;
4913
4914 struct rtw89_h2c_rf_dack {
4915 u8 len;
4916 u8 phy;
4917 u8 type;
4918 } __packed;
4919
4920 struct rtw89_h2c_rf_rxdck_v0 {
4921 u8 len;
4922 u8 phy;
4923 u8 is_afe;
4924 u8 kpath;
4925 u8 cur_band;
4926 u8 cur_bw;
4927 u8 cur_ch;
4928 u8 rxdck_dbg_en;
4929 } __packed;
4930
4931 struct rtw89_h2c_rf_tas {
4932 __le32 enable;
4933 } __packed;
4934
4935 struct rtw89_h2c_rf_rxdck {
4936 struct rtw89_h2c_rf_rxdck_v0 v0;
4937 u8 is_chl_k;
4938 } __packed;
4939
4940 struct rtw89_h2c_rf_txiqk {
4941 u8 len;
4942 u8 phy;
4943 u8 txiqk_enable;
4944 u8 is_wb_txiqk;
4945 u8 kpath;
4946 u8 cur_band;
4947 u8 cur_bw;
4948 u8 cur_ch;
4949 u8 txiqk_dbg_en;
4950 } __packed;
4951
4952 struct rtw89_h2c_rf_cim3k {
4953 u8 len;
4954 u8 phy;
4955 u8 su_cim3k_enable[2];
4956 u8 ru_cim3k_enable[2];
4957 u8 kpath;
4958 u8 cur_band;
4959 u8 cur_bw;
4960 u8 cur_ch;
4961 u8 cim3k_dbg_en;
4962 } __packed;
4963
4964 enum rtw89_rf_log_type {
4965 RTW89_RF_RUN_LOG = 0,
4966 RTW89_RF_RPT_LOG = 1,
4967 };
4968
4969 struct rtw89_c2h_rf_log_hdr {
4970 u8 type; /* enum rtw89_rf_log_type */
4971 __le16 len;
4972 u8 content[];
4973 } __packed;
4974
4975 struct rtw89_c2h_rf_run_log {
4976 __le32 fmt_idx;
4977 __le32 arg[4];
4978 } __packed;
4979
4980 struct rtw89_c2h_rf_iqk_rpt_log {
4981 bool iqk_tx_fail[2];
4982 bool iqk_rx_fail[2];
4983 bool is_iqk_init;
4984 bool is_reload;
4985 bool is_wb_txiqk[2];
4986 bool is_wb_rxiqk[2];
4987 bool is_nbiqk;
4988 bool txiqk_en;
4989 bool rxiqk_en;
4990 bool lok_en;
4991 bool iqk_xym_en;
4992 bool iqk_sram_en;
4993 bool iqk_fft_en;
4994 bool is_fw_iqk;
4995 bool is_iqk_enable;
4996 bool iqk_cfir_en;
4997 bool thermal_rek_en;
4998 u8 iqk_band[2];
4999 u8 iqk_ch[2];
5000 u8 iqk_bw[2];
5001 u8 iqk_times;
5002 u8 version;
5003 u8 phy;
5004 u8 fwk_status;
5005 u8 rsvd;
5006 __le32 reload_cnt;
5007 __le32 iqk_fail_cnt;
5008 __le32 rf_0x18[2];
5009 __le32 lok_idac[2];
5010 __le32 lok_vbuf[2];
5011 __le32 rftxgain[2][6];
5012 __le32 rfrxgain[2][6];
5013 __le32 tx_xym[2][6];
5014 __le32 rx_xym[2][6];
5015 __le32 rx_wb_xym[2][32];
5016 bool is_radar;
5017 u8 rsvd1[3];
5018 } __packed;
5019
5020 struct rtw89_c2h_rf_dpk_rpt_log {
5021 u8 ver;
5022 u8 idx[2];
5023 u8 band[2];
5024 u8 bw[2];
5025 u8 ch[2];
5026 u8 path_ok[2];
5027 u8 txagc[2];
5028 u8 ther[2];
5029 u8 gs[2];
5030 u8 dc_i[4];
5031 u8 dc_q[4];
5032 u8 corr_val[2];
5033 u8 corr_idx[2];
5034 u8 is_timeout[2];
5035 u8 rxbb_ov[2];
5036 u8 rsvd;
5037 } __packed;
5038
5039 struct rtw89_c2h_rf_dack_rpt_log {
5040 u8 fwdack_ver;
5041 u8 fwdack_info_ver;
5042 u8 msbk_d[2][2][16];
5043 u8 dadck_d[2][2];
5044 u8 cdack_d[2][2][2];
5045 u8 addck2_hd[2][2][2];
5046 u8 addck2_ld[2][2][2];
5047 u8 adgaink_d[2][2];
5048 u8 biask_hd[2][2];
5049 u8 biask_ld[2][2];
5050 u8 addck_timeout;
5051 u8 cdack_timeout;
5052 u8 dadck_timeout;
5053 u8 msbk_timeout;
5054 u8 adgaink_timeout;
5055 u8 wbadcdck_timeout;
5056 u8 drck_timeout;
5057 u8 dack_fail;
5058 u8 wbdck_d[2];
5059 u8 rck_d;
5060 u8 adgaink_ex_d;
5061 } __packed;
5062
5063 struct rtw89_c2h_rf_rxdck_rpt_log {
5064 u8 ver;
5065 u8 band[2];
5066 u8 bw[2];
5067 u8 ch[2];
5068 u8 timeout[2];
5069 } __packed;
5070
5071 struct rtw89_c2h_rf_tssi_rpt_log {
5072 s8 alignment_power[2][2][4];
5073 u8 alignment_power_cw_h[2][2][4];
5074 u8 alignment_power_cw_l[2][2][4];
5075 u8 tssi_alimk_state[2][2];
5076 u8 default_txagc_offset[2][2];
5077 } __packed;
5078
5079 struct rtw89_c2h_rf_txgapk_rpt_log {
5080 __le32 r0x8010[2];
5081 __le32 chk_cnt;
5082 u8 track_d[2][17];
5083 u8 power_d[2][17];
5084 u8 is_txgapk_ok;
5085 u8 chk_id;
5086 u8 ver;
5087 u8 d_bnd_ok;
5088 __le32 stage[2];
5089 __le16 failcode[2];
5090 u8 rsvd[4];
5091 } __packed;
5092
5093 struct rtw89_c2h_rf_txiqk_rpt_log {
5094 u8 fw_txiqk_ver;
5095 u8 iqk_band[2];
5096 u8 iqk_ch[2];
5097 u8 iqk_bw[2];
5098 bool tx_iqk_fail[2];
5099 bool is_iqk_init;
5100 bool txiqk_en;
5101 bool lok_en;
5102 bool lok_fail[2];
5103 u8 rsvd[2];
5104 __le32 iqk_times;
5105 bool txiqk_nctldone[2];
5106 u8 rsvd2[2];
5107 __le32 txgain[2][6];
5108 __le32 tx_iqc[2][6];
5109 __le32 tx_xym[2][6][14];
5110 __le32 kidx[2];
5111 } __packed;
5112
5113 struct rtw89_c2h_rf_cim3k_rpt_log {
5114 u8 cim3k_band[2];
5115 u8 cim3k_ch[2];
5116 u8 cim3k_bw[2];
5117 u8 su_path_ok[2];
5118 u8 ru_path_ok[2];
5119 u8 txagc_cim3k[2];
5120 u8 ther_cim3k[2];
5121 u8 cim3k_gs[2];
5122 __le16 cim3k_pwsf[2];
5123 bool cim3k_nctldone[2];
5124 u8 rsvd[2];
5125 __le32 cim3k_rxiqc[2];
5126 __le32 cim3k_su_coef[2][3];
5127 __le16 dc_i[2];
5128 __le16 dc_q[2];
5129 u8 corr_val[2];
5130 u8 corr_idx[2];
5131 u8 rxbb_ov[2];
5132 u8 cim3k_txiqc[2];
5133 u8 kidx[2];
5134 u8 fw_cim3k_ver;
5135 bool su_cim3k_en[2];
5136 bool ru_cim3k_en[2];
5137 u8 rsvd1;
5138 } __packed;
5139
5140 struct rtw89_c2h_rfk_report {
5141 struct rtw89_c2h_hdr hdr;
5142 u8 state; /* enum rtw89_rfk_report_state */
5143 u8 version;
5144 } __packed;
5145
5146 struct rtw89_c2h_rf_tas_rpt_log {
5147 __le32 cur_idx;
5148 __le16 txpwr_history[20];
5149 } __packed;
5150
5151 struct rtw89_c2h_rf_tas_info {
5152 struct rtw89_c2h_hdr hdr;
5153 struct rtw89_c2h_rf_tas_rpt_log content;
5154 } __packed;
5155
5156 #define RTW89_FW_RSVD_PLE_SIZE 0x800
5157
5158 #define RTW89_FW_BACKTRACE_INFO_SIZE 8
5159 #define RTW89_VALID_FW_BACKTRACE_SIZE(_size) \
5160 ((_size) % RTW89_FW_BACKTRACE_INFO_SIZE == 0)
5161
5162 #define RTW89_FW_BACKTRACE_MAX_SIZE 512 /* 8 * 64 (entries) */
5163 #define RTW89_FW_BACKTRACE_KEY 0xBACEBACE
5164
5165 #define FWDL_WAIT_CNT 400000
5166 #define FWDL_WAIT_CNT_USB 3200
5167
5168 int rtw89_fw_check_rdy(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type);
5169 int rtw89_fw_recognize(struct rtw89_dev *rtwdev);
5170 int rtw89_fw_recognize_elements(struct rtw89_dev *rtwdev);
5171 const struct firmware *
5172 rtw89_early_fw_feature_recognize(struct device *device,
5173 const struct rtw89_chip_info *chip,
5174 struct rtw89_fw_info *early_fw,
5175 int *used_fw_format);
5176 int rtw89_fw_download(struct rtw89_dev *rtwdev, enum rtw89_fw_type type,
5177 bool include_bb);
5178 void rtw89_load_firmware_work(struct work_struct *work);
5179 void rtw89_unload_firmware(struct rtw89_dev *rtwdev);
5180 int rtw89_wait_firmware_completion(struct rtw89_dev *rtwdev);
5181 int rtw89_fw_log_prepare(struct rtw89_dev *rtwdev);
5182 void rtw89_fw_log_dump(struct rtw89_dev *rtwdev, u8 *buf, u32 len);
5183 void rtw89_h2c_pkt_set_hdr(struct rtw89_dev *rtwdev, struct sk_buff *skb,
5184 u8 type, u8 cat, u8 class, u8 func,
5185 bool rack, bool dack, u32 len);
5186 int rtw89_fw_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev,
5187 struct rtw89_vif_link *rtwvif_link,
5188 struct rtw89_sta_link *rtwsta_link);
5189 int rtw89_fw_h2c_default_cmac_tbl_g7(struct rtw89_dev *rtwdev,
5190 struct rtw89_vif_link *rtwvif_link,
5191 struct rtw89_sta_link *rtwsta_link);
5192 int rtw89_fw_h2c_default_cmac_tbl_be(struct rtw89_dev *rtwdev,
5193 struct rtw89_vif_link *rtwvif_link,
5194 struct rtw89_sta_link *rtwsta_link);
5195 int rtw89_fw_h2c_default_dmac_tbl_v2(struct rtw89_dev *rtwdev,
5196 struct rtw89_vif_link *rtwvif_link,
5197 struct rtw89_sta_link *rtwsta_link);
5198 int rtw89_fw_h2c_default_dmac_tbl_v3(struct rtw89_dev *rtwdev,
5199 struct rtw89_vif_link *rtwvif_link,
5200 struct rtw89_sta_link *rtwsta_link);
5201 int rtw89_fw_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev,
5202 struct rtw89_vif_link *rtwvif_link,
5203 struct rtw89_sta_link *rtwsta_link);
5204 int rtw89_fw_h2c_assoc_cmac_tbl_g7(struct rtw89_dev *rtwdev,
5205 struct rtw89_vif_link *rtwvif_link,
5206 struct rtw89_sta_link *rtwsta_link);
5207 int rtw89_fw_h2c_assoc_cmac_tbl_be(struct rtw89_dev *rtwdev,
5208 struct rtw89_vif_link *rtwvif_link,
5209 struct rtw89_sta_link *rtwsta_link);
5210 int rtw89_fw_h2c_ampdu_cmac_tbl_g7(struct rtw89_dev *rtwdev,
5211 struct rtw89_vif_link *rtwvif_link,
5212 struct rtw89_sta_link *rtwsta_link);
5213 int rtw89_fw_h2c_ampdu_cmac_tbl_be(struct rtw89_dev *rtwdev,
5214 struct rtw89_vif_link *rtwvif_link,
5215 struct rtw89_sta_link *rtwsta_link);
5216 int rtw89_fw_h2c_txtime_cmac_tbl(struct rtw89_dev *rtwdev,
5217 struct rtw89_sta_link *rtwsta_link);
5218 int rtw89_fw_h2c_txtime_cmac_tbl_g7(struct rtw89_dev *rtwdev,
5219 struct rtw89_sta_link *rtwsta_link);
5220 int rtw89_fw_h2c_txtime_cmac_tbl_be(struct rtw89_dev *rtwdev,
5221 struct rtw89_sta_link *rtwsta_link);
5222 int rtw89_fw_h2c_punctured_cmac_tbl_g7(struct rtw89_dev *rtwdev,
5223 struct rtw89_vif_link *rtwvif_link,
5224 u16 punctured);
5225 int rtw89_fw_h2c_punctured_cmac_tbl_be(struct rtw89_dev *rtwdev,
5226 struct rtw89_vif_link *rtwvif_link,
5227 u16 punctured);
5228 int rtw89_fw_h2c_txpath_cmac_tbl(struct rtw89_dev *rtwdev,
5229 struct rtw89_sta_link *rtwsta_link);
5230 int rtw89_fw_h2c_update_beacon(struct rtw89_dev *rtwdev,
5231 struct rtw89_vif_link *rtwvif_link);
5232 int rtw89_fw_h2c_update_beacon_be(struct rtw89_dev *rtwdev,
5233 struct rtw89_vif_link *rtwvif_link);
5234 int rtw89_fw_h2c_tbtt_tuning(struct rtw89_dev *rtwdev,
5235 struct rtw89_vif_link *rtwvif_link, u32 offset);
5236 int rtw89_fw_h2c_pwr_lvl(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link);
5237 int rtw89_fw_h2c_cam(struct rtw89_dev *rtwdev, struct rtw89_vif_link *vif,
5238 struct rtw89_sta_link *rtwsta_link, const u8 *scan_mac_addr,
5239 enum rtw89_upd_mode upd_mode);
5240 int rtw89_fw_h2c_dctl_sec_cam_v1(struct rtw89_dev *rtwdev,
5241 struct rtw89_vif_link *rtwvif_link,
5242 struct rtw89_sta_link *rtwsta_link);
5243 int rtw89_fw_h2c_dctl_sec_cam_v2(struct rtw89_dev *rtwdev,
5244 struct rtw89_vif_link *rtwvif_link,
5245 struct rtw89_sta_link *rtwsta_link);
5246 int rtw89_fw_h2c_dctl_sec_cam_v3(struct rtw89_dev *rtwdev,
5247 struct rtw89_vif_link *rtwvif_link,
5248 struct rtw89_sta_link *rtwsta_link);
5249 void rtw89_fw_c2h_irqsafe(struct rtw89_dev *rtwdev, struct sk_buff *c2h);
5250 void rtw89_fw_c2h_work(struct wiphy *wiphy, struct wiphy_work *work);
5251 void rtw89_fw_c2h_purge_obsoleted_scan_events(struct rtw89_dev *rtwdev);
5252 void rtw89_fw_c2h_dummy_handler(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len);
5253 int rtw89_fw_h2c_role_maintain(struct rtw89_dev *rtwdev,
5254 struct rtw89_vif_link *rtwvif_link,
5255 struct rtw89_sta_link *rtwsta_link,
5256 enum rtw89_upd_mode upd_mode);
5257 int rtw89_fw_h2c_join_info(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
5258 struct rtw89_sta_link *rtwsta_link, bool dis_conn);
5259 int rtw89_fw_h2c_notify_dbcc(struct rtw89_dev *rtwdev, bool en);
5260 int rtw89_fw_h2c_macid_pause(struct rtw89_dev *rtwdev, u8 sh, u8 grp,
5261 bool pause);
5262 int rtw89_fw_h2c_set_edca(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
5263 u8 ac, u32 val);
5264 int rtw89_fw_h2c_set_ofld_cfg(struct rtw89_dev *rtwdev);
5265 int rtw89_fw_h2c_tx_duty(struct rtw89_dev *rtwdev, u8 lv);
5266 int rtw89_fw_h2c_set_bcn_fltr_cfg(struct rtw89_dev *rtwdev,
5267 struct rtw89_vif_link *rtwvif_link,
5268 bool connect);
5269 int rtw89_fw_h2c_rssi_offload(struct rtw89_dev *rtwdev,
5270 struct rtw89_rx_phy_ppdu *phy_ppdu);
5271 int rtw89_fw_h2c_tp_offload(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link);
5272 int rtw89_fw_h2c_ra(struct rtw89_dev *rtwdev, struct rtw89_ra_info *ra, bool csi);
5273 int rtw89_fw_h2c_cxdrv_init(struct rtw89_dev *rtwdev, u8 type);
5274 int rtw89_fw_h2c_cxdrv_init_v7(struct rtw89_dev *rtwdev, u8 type);
5275 int rtw89_fw_h2c_cxdrv_role(struct rtw89_dev *rtwdev, u8 type);
5276 int rtw89_fw_h2c_cxdrv_role_v1(struct rtw89_dev *rtwdev, u8 type);
5277 int rtw89_fw_h2c_cxdrv_role_v2(struct rtw89_dev *rtwdev, u8 type);
5278 int rtw89_fw_h2c_cxdrv_role_v7(struct rtw89_dev *rtwdev, u8 type);
5279 int rtw89_fw_h2c_cxdrv_role_v8(struct rtw89_dev *rtwdev, u8 type);
5280 int rtw89_fw_h2c_cxdrv_osi_info(struct rtw89_dev *rtwdev, u8 type);
5281 int rtw89_fw_h2c_cxdrv_ctrl(struct rtw89_dev *rtwdev, u8 type);
5282 int rtw89_fw_h2c_cxdrv_ctrl_v7(struct rtw89_dev *rtwdev, u8 type);
5283 int rtw89_fw_h2c_cxdrv_trx(struct rtw89_dev *rtwdev, u8 type);
5284 int rtw89_fw_h2c_cxdrv_rfk(struct rtw89_dev *rtwdev, u8 type);
5285 int rtw89_fw_h2c_del_pkt_offload(struct rtw89_dev *rtwdev, u8 id);
5286 int rtw89_fw_h2c_add_pkt_offload(struct rtw89_dev *rtwdev, u8 *id,
5287 struct sk_buff *skb_ofld);
5288 int rtw89_fw_h2c_scan_offload_ax(struct rtw89_dev *rtwdev,
5289 struct rtw89_scan_option *opt,
5290 struct rtw89_vif_link *vif,
5291 bool wowlan);
5292 int rtw89_fw_h2c_scan_offload_be(struct rtw89_dev *rtwdev,
5293 struct rtw89_scan_option *opt,
5294 struct rtw89_vif_link *vif,
5295 bool wowlan);
5296 int rtw89_fw_h2c_rf_reg(struct rtw89_dev *rtwdev,
5297 struct rtw89_fw_h2c_rf_reg_info *info,
5298 u16 len, u8 page);
5299 int rtw89_fw_h2c_rf_ntfy_mcc(struct rtw89_dev *rtwdev);
5300 int rtw89_fw_h2c_rf_ps_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
5301 int rtw89_fw_h2c_rf_pre_ntfy(struct rtw89_dev *rtwdev,
5302 enum rtw89_phy_idx phy_idx);
5303 int rtw89_fw_h2c_rf_pre_ntfy_mcc(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
5304 int rtw89_fw_h2c_mcc_dig(struct rtw89_dev *rtwdev,
5305 enum rtw89_chanctx_idx chanctx_idx,
5306 u8 mcc_role_idx, u8 pd_val, bool en);
5307 int rtw89_fw_h2c_rf_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
5308 const struct rtw89_chan *chan, enum rtw89_tssi_mode tssi_mode);
5309 int rtw89_fw_h2c_rf_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
5310 const struct rtw89_chan *chan);
5311 int rtw89_fw_h2c_rf_dpk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
5312 const struct rtw89_chan *chan);
5313 int rtw89_fw_h2c_rf_txgapk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
5314 const struct rtw89_chan *chan);
5315 int rtw89_fw_h2c_rf_dack(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
5316 const struct rtw89_chan *chan);
5317 int rtw89_fw_h2c_rf_rxdck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
5318 const struct rtw89_chan *chan, bool is_chl_k);
5319 int rtw89_fw_h2c_rf_tas_trigger(struct rtw89_dev *rtwdev, bool enable);
5320 int rtw89_fw_h2c_rf_txiqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
5321 const struct rtw89_chan *chan);
5322 int rtw89_fw_h2c_rf_cim3k(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
5323 const struct rtw89_chan *chan);
5324 int rtw89_fw_h2c_raw_with_hdr(struct rtw89_dev *rtwdev,
5325 u8 h2c_class, u8 h2c_func, u8 *buf, u16 len,
5326 bool rack, bool dack);
5327 int rtw89_fw_h2c_raw(struct rtw89_dev *rtwdev, const u8 *buf, u16 len);
5328 void rtw89_fw_send_all_early_h2c(struct rtw89_dev *rtwdev);
5329 void __rtw89_fw_free_all_early_h2c(struct rtw89_dev *rtwdev);
5330 void rtw89_fw_free_all_early_h2c(struct rtw89_dev *rtwdev);
5331 int rtw89_fw_h2c_general_pkt(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
5332 u8 macid);
5333 void rtw89_fw_release_general_pkt_list_vif(struct rtw89_dev *rtwdev,
5334 struct rtw89_vif_link *rtwvif_link,
5335 bool notify_fw);
5336 void rtw89_fw_release_general_pkt_list(struct rtw89_dev *rtwdev, bool notify_fw);
5337 int rtw89_fw_h2c_ba_cam(struct rtw89_dev *rtwdev,
5338 struct rtw89_vif_link *rtwvif_link,
5339 struct rtw89_sta_link *rtwsta_link,
5340 bool valid, struct ieee80211_ampdu_params *params);
5341 int rtw89_fw_h2c_ba_cam_v1(struct rtw89_dev *rtwdev,
5342 struct rtw89_vif_link *rtwvif_link,
5343 struct rtw89_sta_link *rtwsta_link,
5344 bool valid, struct ieee80211_ampdu_params *params);
5345 void rtw89_fw_h2c_init_dynamic_ba_cam_v0_ext(struct rtw89_dev *rtwdev);
5346 int rtw89_fw_h2c_init_ba_cam_users(struct rtw89_dev *rtwdev, u8 users,
5347 u8 offset, u8 mac_idx);
5348
5349 int rtw89_fw_h2c_lps_parm(struct rtw89_dev *rtwdev,
5350 struct rtw89_lps_parm *lps_param);
5351 int rtw89_fw_h2c_lps_ch_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
5352 int rtw89_fw_h2c_lps_ml_cmn_info(struct rtw89_dev *rtwdev,
5353 struct rtw89_vif *rtwvif);
5354 void rtw89_bb_lps_cmn_info_rx_gain_fill(struct rtw89_dev *rtwdev,
5355 struct rtw89_bb_link_info_rx_gain *h2c_gain,
5356 const struct rtw89_chan *chan, u8 phy_idx);
5357 int rtw89_fw_h2c_lps_ml_cmn_info_v1(struct rtw89_dev *rtwdev,
5358 struct rtw89_vif *rtwvif);
5359 int rtw89_fw_h2c_fwips(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
5360 bool enable);
5361 struct sk_buff *rtw89_fw_h2c_alloc_skb_with_hdr(struct rtw89_dev *rtwdev, u32 len);
5362 struct sk_buff *rtw89_fw_h2c_alloc_skb_no_hdr(struct rtw89_dev *rtwdev, u32 len);
5363 int rtw89_fw_msg_reg(struct rtw89_dev *rtwdev,
5364 struct rtw89_mac_h2c_info *h2c_info,
5365 struct rtw89_mac_c2h_info *c2h_info);
5366 int rtw89_fw_h2c_fw_log(struct rtw89_dev *rtwdev, bool enable);
5367 void rtw89_fw_st_dbg_dump(struct rtw89_dev *rtwdev);
5368 int rtw89_hw_scan_start(struct rtw89_dev *rtwdev,
5369 struct rtw89_vif_link *rtwvif_link,
5370 struct ieee80211_scan_request *scan_req);
5371 void rtw89_hw_scan_complete(struct rtw89_dev *rtwdev,
5372 struct rtw89_vif_link *rtwvif_link,
5373 bool aborted);
5374 int rtw89_hw_scan_offload(struct rtw89_dev *rtwdev,
5375 struct rtw89_vif_link *rtwvif_link,
5376 bool enable);
5377 void rtw89_hw_scan_abort(struct rtw89_dev *rtwdev,
5378 struct rtw89_vif_link *rtwvif_link);
5379 int rtw89_hw_scan_prep_chan_list_ax(struct rtw89_dev *rtwdev,
5380 struct rtw89_vif_link *rtwvif_link);
5381 void rtw89_hw_scan_free_chan_list_ax(struct rtw89_dev *rtwdev);
5382 int rtw89_hw_scan_add_chan_list_ax(struct rtw89_dev *rtwdev,
5383 struct rtw89_vif_link *rtwvif_link);
5384 int rtw89_pno_scan_add_chan_list_ax(struct rtw89_dev *rtwdev,
5385 struct rtw89_vif_link *rtwvif_link);
5386 int rtw89_hw_scan_prep_chan_list_be(struct rtw89_dev *rtwdev,
5387 struct rtw89_vif_link *rtwvif_link);
5388 void rtw89_hw_scan_free_chan_list_be(struct rtw89_dev *rtwdev);
5389 int rtw89_hw_scan_add_chan_list_be(struct rtw89_dev *rtwdev,
5390 struct rtw89_vif_link *rtwvif_link);
5391 int rtw89_pno_scan_add_chan_list_be(struct rtw89_dev *rtwdev,
5392 struct rtw89_vif_link *rtwvif_link);
5393 int rtw89_fw_h2c_trigger_cpu_exception(struct rtw89_dev *rtwdev);
5394 int rtw89_fw_h2c_pkt_drop(struct rtw89_dev *rtwdev,
5395 const struct rtw89_pkt_drop_params *params);
5396 int rtw89_fw_h2c_p2p_act(struct rtw89_dev *rtwdev,
5397 struct rtw89_vif_link *rtwvif_link,
5398 struct ieee80211_p2p_noa_desc *desc,
5399 u8 act, u8 noa_id, u8 ctwindow_oppps);
5400 int rtw89_fw_h2c_tsf32_toggle(struct rtw89_dev *rtwdev,
5401 struct rtw89_vif_link *rtwvif_link,
5402 bool en);
5403 int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
5404 bool enable);
5405 int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev,
5406 struct rtw89_vif_link *rtwvif_link, bool enable);
5407 int rtw89_fw_h2c_cfg_pno(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
5408 bool enable);
5409 int rtw89_fw_h2c_keep_alive(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
5410 bool enable);
5411 int rtw89_fw_h2c_arp_offload(struct rtw89_dev *rtwdev,
5412 struct rtw89_vif_link *rtwvif_link, bool enable);
5413 int rtw89_fw_h2c_disconnect_detect(struct rtw89_dev *rtwdev,
5414 struct rtw89_vif_link *rtwvif_link, bool enable);
5415 int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
5416 bool enable);
5417 int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev,
5418 struct rtw89_vif_link *rtwvif_link, bool enable);
5419 int rtw89_fw_h2c_wow_cam_update(struct rtw89_dev *rtwdev,
5420 struct rtw89_wow_cam_info *cam_info);
5421 int rtw89_fw_h2c_wow_cam_update_v1(struct rtw89_dev *rtwdev,
5422 struct rtw89_wow_cam_info *cam_info);
5423 int rtw89_fw_h2c_wow_gtk_ofld(struct rtw89_dev *rtwdev,
5424 struct rtw89_vif_link *rtwvif_link,
5425 bool enable);
5426 int rtw89_fw_h2c_wow_request_aoac(struct rtw89_dev *rtwdev);
5427 int rtw89_fw_h2c_add_mcc(struct rtw89_dev *rtwdev,
5428 const struct rtw89_fw_mcc_add_req *p);
5429 int rtw89_fw_h2c_start_mcc(struct rtw89_dev *rtwdev,
5430 const struct rtw89_fw_mcc_start_req *p);
5431 int rtw89_fw_h2c_stop_mcc(struct rtw89_dev *rtwdev, u8 group, u8 macid,
5432 bool prev_groups);
5433 int rtw89_fw_h2c_del_mcc_group(struct rtw89_dev *rtwdev, u8 group,
5434 bool prev_groups);
5435 int rtw89_fw_h2c_reset_mcc_group(struct rtw89_dev *rtwdev, u8 group);
5436 int rtw89_fw_h2c_mcc_req_tsf(struct rtw89_dev *rtwdev,
5437 const struct rtw89_fw_mcc_tsf_req *req,
5438 struct rtw89_mac_mcc_tsf_rpt *rpt);
5439 int rtw89_fw_h2c_mcc_macid_bitmap(struct rtw89_dev *rtwdev, u8 group, u8 macid,
5440 u8 *bitmap);
5441 int rtw89_fw_h2c_mcc_sync(struct rtw89_dev *rtwdev, u8 group, u8 source,
5442 u8 target, u8 offset);
5443 int rtw89_fw_h2c_mcc_set_duration(struct rtw89_dev *rtwdev,
5444 const struct rtw89_fw_mcc_duration *p);
5445 int rtw89_fw_h2c_mrc_add(struct rtw89_dev *rtwdev,
5446 const struct rtw89_fw_mrc_add_arg *arg);
5447 int rtw89_fw_h2c_mrc_start(struct rtw89_dev *rtwdev,
5448 const struct rtw89_fw_mrc_start_arg *arg);
5449 int rtw89_fw_h2c_mrc_del(struct rtw89_dev *rtwdev, u8 sch_idx, u8 slot_idx);
5450 int rtw89_fw_h2c_mrc_req_tsf(struct rtw89_dev *rtwdev,
5451 const struct rtw89_fw_mrc_req_tsf_arg *arg,
5452 struct rtw89_mac_mrc_tsf_rpt *rpt);
5453 int rtw89_fw_h2c_mrc_upd_bitmap(struct rtw89_dev *rtwdev,
5454 const struct rtw89_fw_mrc_upd_bitmap_arg *arg);
5455 int rtw89_fw_h2c_mrc_sync(struct rtw89_dev *rtwdev,
5456 const struct rtw89_fw_mrc_sync_arg *arg);
5457 int rtw89_fw_h2c_mrc_upd_duration(struct rtw89_dev *rtwdev,
5458 const struct rtw89_fw_mrc_upd_duration_arg *arg);
5459 int rtw89_fw_h2c_ap_info_refcount(struct rtw89_dev *rtwdev, bool en);
5460 int rtw89_fw_h2c_mlo_link_cfg(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
5461 bool enable);
5462
rtw89_fw_h2c_init_ba_cam(struct rtw89_dev * rtwdev)5463 static inline void rtw89_fw_h2c_init_ba_cam(struct rtw89_dev *rtwdev)
5464 {
5465 const struct rtw89_chip_info *chip = rtwdev->chip;
5466
5467 if (chip->bacam_ver == RTW89_BACAM_V0_EXT)
5468 rtw89_fw_h2c_init_dynamic_ba_cam_v0_ext(rtwdev);
5469 }
5470
rtw89_chip_h2c_default_cmac_tbl(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)5471 static inline int rtw89_chip_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev,
5472 struct rtw89_vif_link *rtwvif_link,
5473 struct rtw89_sta_link *rtwsta_link)
5474 {
5475 const struct rtw89_chip_info *chip = rtwdev->chip;
5476
5477 return chip->ops->h2c_default_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
5478 }
5479
rtw89_chip_h2c_default_dmac_tbl(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)5480 static inline int rtw89_chip_h2c_default_dmac_tbl(struct rtw89_dev *rtwdev,
5481 struct rtw89_vif_link *rtwvif_link,
5482 struct rtw89_sta_link *rtwsta_link)
5483 {
5484 const struct rtw89_chip_info *chip = rtwdev->chip;
5485
5486 if (chip->ops->h2c_default_dmac_tbl)
5487 return chip->ops->h2c_default_dmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
5488
5489 return 0;
5490 }
5491
rtw89_chip_h2c_update_beacon(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)5492 static inline int rtw89_chip_h2c_update_beacon(struct rtw89_dev *rtwdev,
5493 struct rtw89_vif_link *rtwvif_link)
5494 {
5495 const struct rtw89_chip_info *chip = rtwdev->chip;
5496
5497 return chip->ops->h2c_update_beacon(rtwdev, rtwvif_link);
5498 }
5499
rtw89_chip_h2c_assoc_cmac_tbl(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)5500 static inline int rtw89_chip_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev,
5501 struct rtw89_vif_link *rtwvif_link,
5502 struct rtw89_sta_link *rtwsta_link)
5503 {
5504 const struct rtw89_chip_info *chip = rtwdev->chip;
5505
5506 return chip->ops->h2c_assoc_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
5507 }
5508
5509 static inline
rtw89_chip_h2c_ampdu_link_cmac_tbl(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)5510 int rtw89_chip_h2c_ampdu_link_cmac_tbl(struct rtw89_dev *rtwdev,
5511 struct rtw89_vif_link *rtwvif_link,
5512 struct rtw89_sta_link *rtwsta_link)
5513 {
5514 const struct rtw89_chip_info *chip = rtwdev->chip;
5515
5516 if (chip->ops->h2c_ampdu_cmac_tbl)
5517 return chip->ops->h2c_ampdu_cmac_tbl(rtwdev, rtwvif_link,
5518 rtwsta_link);
5519
5520 return 0;
5521 }
5522
rtw89_chip_h2c_ampdu_cmac_tbl(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,struct rtw89_sta * rtwsta)5523 static inline int rtw89_chip_h2c_ampdu_cmac_tbl(struct rtw89_dev *rtwdev,
5524 struct rtw89_vif *rtwvif,
5525 struct rtw89_sta *rtwsta)
5526 {
5527 struct rtw89_vif_link *rtwvif_link;
5528 struct rtw89_sta_link *rtwsta_link;
5529 unsigned int link_id;
5530 int ret;
5531
5532 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) {
5533 rtwvif_link = rtwsta_link->rtwvif_link;
5534 ret = rtw89_chip_h2c_ampdu_link_cmac_tbl(rtwdev, rtwvif_link,
5535 rtwsta_link);
5536 if (ret)
5537 return ret;
5538 }
5539
5540 return 0;
5541 }
5542
5543 static inline
rtw89_chip_h2c_txtime_cmac_tbl(struct rtw89_dev * rtwdev,struct rtw89_sta_link * rtwsta_link)5544 int rtw89_chip_h2c_txtime_cmac_tbl(struct rtw89_dev *rtwdev,
5545 struct rtw89_sta_link *rtwsta_link)
5546 {
5547 const struct rtw89_chip_info *chip = rtwdev->chip;
5548
5549 return chip->ops->h2c_txtime_cmac_tbl(rtwdev, rtwsta_link);
5550 }
5551
5552 static inline
rtw89_chip_h2c_punctured_cmac_tbl(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,u16 punctured)5553 int rtw89_chip_h2c_punctured_cmac_tbl(struct rtw89_dev *rtwdev,
5554 struct rtw89_vif_link *rtwvif_link,
5555 u16 punctured)
5556 {
5557 const struct rtw89_chip_info *chip = rtwdev->chip;
5558
5559 if (!chip->ops->h2c_punctured_cmac_tbl)
5560 return 0;
5561
5562 return chip->ops->h2c_punctured_cmac_tbl(rtwdev, rtwvif_link, punctured);
5563 }
5564
5565 static inline
rtw89_chip_h2c_ba_cam(struct rtw89_dev * rtwdev,struct rtw89_sta * rtwsta,bool valid,struct ieee80211_ampdu_params * params)5566 int rtw89_chip_h2c_ba_cam(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
5567 bool valid, struct ieee80211_ampdu_params *params)
5568 {
5569 const struct rtw89_chip_info *chip = rtwdev->chip;
5570 struct rtw89_vif_link *rtwvif_link;
5571 struct rtw89_sta_link *rtwsta_link;
5572 unsigned int link_id;
5573 int ret;
5574
5575 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) {
5576 rtwvif_link = rtwsta_link->rtwvif_link;
5577 ret = chip->ops->h2c_ba_cam(rtwdev, rtwvif_link, rtwsta_link,
5578 valid, params);
5579 if (ret)
5580 return ret;
5581 }
5582
5583 return 0;
5584 }
5585
5586 static inline
rtw89_chip_h2c_wow_cam_update(struct rtw89_dev * rtwdev,struct rtw89_wow_cam_info * cam_info)5587 int rtw89_chip_h2c_wow_cam_update(struct rtw89_dev *rtwdev,
5588 struct rtw89_wow_cam_info *cam_info)
5589 {
5590 const struct rtw89_chip_info *chip = rtwdev->chip;
5591
5592 return chip->ops->h2c_wow_cam_update(rtwdev, cam_info);
5593 }
5594
5595 /* Must consider compatibility; don't insert new in the mid.
5596 * Fill each field's default value in rtw89_regd_entcpy().
5597 */
5598 struct rtw89_fw_regd_entry {
5599 u8 alpha2_0;
5600 u8 alpha2_1;
5601 u8 rule_2ghz;
5602 u8 rule_5ghz;
5603 u8 rule_6ghz;
5604 __le32 fmap;
5605 } __packed;
5606
5607 /* must consider compatibility; don't insert new in the mid */
5608 struct rtw89_fw_txpwr_byrate_entry {
5609 u8 band;
5610 u8 nss;
5611 u8 rs;
5612 u8 shf;
5613 u8 len;
5614 __le32 data;
5615 u8 bw;
5616 u8 ofdma;
5617 } __packed;
5618
5619 /* must consider compatibility; don't insert new in the mid */
5620 struct rtw89_fw_txpwr_lmt_2ghz_entry {
5621 u8 bw;
5622 u8 nt;
5623 u8 rs;
5624 u8 bf;
5625 u8 regd;
5626 u8 ch_idx;
5627 s8 v;
5628 } __packed;
5629
5630 /* must consider compatibility; don't insert new in the mid */
5631 struct rtw89_fw_txpwr_lmt_5ghz_entry {
5632 u8 bw;
5633 u8 nt;
5634 u8 rs;
5635 u8 bf;
5636 u8 regd;
5637 u8 ch_idx;
5638 s8 v;
5639 } __packed;
5640
5641 /* must consider compatibility; don't insert new in the mid */
5642 struct rtw89_fw_txpwr_lmt_6ghz_entry {
5643 u8 bw;
5644 u8 nt;
5645 u8 rs;
5646 u8 bf;
5647 u8 regd;
5648 u8 reg_6ghz_power;
5649 u8 ch_idx;
5650 s8 v;
5651 } __packed;
5652
5653 /* must consider compatibility; don't insert new in the mid */
5654 struct rtw89_fw_txpwr_lmt_ru_2ghz_entry {
5655 u8 ru;
5656 u8 nt;
5657 u8 regd;
5658 u8 ch_idx;
5659 s8 v;
5660 } __packed;
5661
5662 /* must consider compatibility; don't insert new in the mid */
5663 struct rtw89_fw_txpwr_lmt_ru_5ghz_entry {
5664 u8 ru;
5665 u8 nt;
5666 u8 regd;
5667 u8 ch_idx;
5668 s8 v;
5669 } __packed;
5670
5671 /* must consider compatibility; don't insert new in the mid */
5672 struct rtw89_fw_txpwr_lmt_ru_6ghz_entry {
5673 u8 ru;
5674 u8 nt;
5675 u8 regd;
5676 u8 reg_6ghz_power;
5677 u8 ch_idx;
5678 s8 v;
5679 } __packed;
5680
5681 /* must consider compatibility; don't insert new in the mid */
5682 struct rtw89_fw_tx_shape_lmt_entry {
5683 u8 band;
5684 u8 tx_shape_rs;
5685 u8 regd;
5686 u8 v;
5687 } __packed;
5688
5689 /* must consider compatibility; don't insert new in the mid */
5690 struct rtw89_fw_tx_shape_lmt_ru_entry {
5691 u8 band;
5692 u8 regd;
5693 u8 v;
5694 } __packed;
5695
5696 const struct rtw89_rfe_parms *
5697 rtw89_load_rfe_data_from_fw(struct rtw89_dev *rtwdev,
5698 const struct rtw89_rfe_parms *init);
5699
5700 enum rtw89_wow_wakeup_ver {
5701 RTW89_WOW_REASON_V0,
5702 RTW89_WOW_REASON_V1,
5703 RTW89_WOW_REASON_NUM,
5704 };
5705
5706 #endif
5707