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Searched refs:tg (Results 1 – 25 of 116) sorted by relevance

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/linux/block/
H A Dblk-throttle.c54 static inline struct blkcg_gq *tg_to_blkg(struct throtl_grp *tg) in tg_to_blkg() argument
56 return pd_to_blkg(&tg->pd); in tg_to_blkg()
83 struct throtl_grp *tg = sq_to_tg(sq); in sq_to_td() local
85 if (tg) in sq_to_td()
86 return tg->td; in sq_to_td()
91 static uint64_t tg_bps_limit(struct throtl_grp *tg, int rw) in tg_bps_limit() argument
93 struct blkcg_gq *blkg = tg_to_blkg(tg); in tg_bps_limit()
98 return tg->bps[rw]; in tg_bps_limit()
101 static unsigned int tg_iops_limit(struct throtl_grp *tg, int rw) in tg_iops_limit() argument
103 struct blkcg_gq *blkg = tg_to_blkg(tg); in tg_iops_limit()
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H A Dblk-throttle.h34 struct throtl_grp *tg; /* tg this qnode belongs to */ member
170 struct throtl_grp *tg; in blk_should_throtl() local
176 tg = blkg_to_tg(bio->bi_blkg); in blk_should_throtl()
180 blkg_rwstat_add(&tg->stat_bytes, bio->bi_opf, in blk_should_throtl()
183 blkg_rwstat_add(&tg->stat_ios, bio->bi_opf, 1); in blk_should_throtl()
187 if (tg->has_rules_iops[rw]) in blk_should_throtl()
190 if (tg->has_rules_bps[rw] && !bio_flagged(bio, BIO_BPS_THROTTLED)) in blk_should_throtl()
/linux/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_timing_generator.h117 #define DCE110TG_FROM_TG(tg)\ argument
118 container_of(tg, struct dce110_timing_generator, base)
121 struct dce110_timing_generator *tg,
128 struct timing_generator *tg,
136 struct timing_generator *tg,
140 bool dce110_timing_generator_enable_crtc(struct timing_generator *tg);
141 bool dce110_timing_generator_disable_crtc(struct timing_generator *tg);
144 struct timing_generator *tg,
151 struct timing_generator *tg);
154 struct timing_generator *tg,
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H A Ddce110_timing_generator.c66 struct timing_generator *tg, in dce110_timing_generator_apply_front_porch_workaround() argument
92 struct timing_generator *tg) in dce110_timing_generator_is_in_vertical_blank() argument
97 struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); in dce110_timing_generator_is_in_vertical_blank()
100 value = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_is_in_vertical_blank()
106 struct timing_generator *tg, in dce110_timing_generator_set_early_control() argument
110 struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); in dce110_timing_generator_set_early_control()
113 regval = dm_read_reg(tg->ctx, address); in dce110_timing_generator_set_early_control()
116 dm_write_reg(tg->ctx, address, regval); in dce110_timing_generator_set_early_control()
123 bool dce110_timing_generator_enable_crtc(struct timing_generator *tg) in dce110_timing_generator_enable_crtc() argument
127 struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); in dce110_timing_generator_enable_crtc()
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H A Ddce110_timing_generator_v.c42 tg->ctx->logger
53 static bool dce110_timing_generator_v_enable_crtc(struct timing_generator *tg) in dce110_timing_generator_v_enable_crtc() argument
64 dm_write_reg(tg->ctx, in dce110_timing_generator_v_enable_crtc()
69 dm_write_reg(tg->ctx, mmCRTCV_MASTER_UPDATE_MODE, value); in dce110_timing_generator_v_enable_crtc()
74 dm_write_reg(tg->ctx, in dce110_timing_generator_v_enable_crtc()
80 static bool dce110_timing_generator_v_disable_crtc(struct timing_generator *tg) in dce110_timing_generator_v_disable_crtc() argument
84 value = dm_read_reg(tg->ctx, in dce110_timing_generator_v_disable_crtc()
90 dm_write_reg(tg->ctx, in dce110_timing_generator_v_disable_crtc()
99 static void dce110_timing_generator_v_blank_crtc(struct timing_generator *tg) in dce110_timing_generator_v_blank_crtc() argument
102 uint32_t value = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_v_blank_crtc()
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/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dtiming_generator.h199 bool (*validate_timing)(struct timing_generator *tg,
201 void (*program_timing)(struct timing_generator *tg,
222 bool (*enable_crtc)(struct timing_generator *tg);
223 bool (*disable_crtc)(struct timing_generator *tg);
224 void (*phantom_crtc_post_enable)(struct timing_generator *tg);
225 void (*disable_phantom_crtc)(struct timing_generator *tg);
226 bool (*immediate_disable_crtc)(struct timing_generator *tg);
227 bool (*is_counter_moving)(struct timing_generator *tg);
228 void (*get_position)(struct timing_generator *tg,
231 uint32_t (*get_frame_count)(struct timing_generator *tg);
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/linux/drivers/gpu/drm/amd/display/dc/dce120/
H A Ddce120_timing_generator.c86 struct timing_generator *tg) in dce120_timing_generator_is_in_vertical_blank() argument
89 struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); in dce120_timing_generator_is_in_vertical_blank()
91 tg->ctx, in dce120_timing_generator_is_in_vertical_blank()
102 struct timing_generator *tg, in dce120_timing_generator_validate_timing() argument
111 struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); in dce120_timing_generator_validate_timing()
114 tg, in dce120_timing_generator_validate_timing()
128 static bool dce120_tg_validate_timing(struct timing_generator *tg, in dce120_tg_validate_timing() argument
131 return dce120_timing_generator_validate_timing(tg, timing, SIGNAL_TYPE_NONE); in dce120_tg_validate_timing()
136 static bool dce120_timing_generator_enable_crtc(struct timing_generator *tg) in dce120_timing_generator_enable_crtc() argument
139 struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); in dce120_timing_generator_enable_crtc()
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/linux/kernel/sched/
H A Dautogroup.h16 struct task_group *tg; member
23 extern void autogroup_free(struct task_group *tg);
25 static inline bool task_group_is_autogroup(struct task_group *tg) in task_group_is_autogroup() argument
27 return !!tg->autogroup; in task_group_is_autogroup()
30 extern bool task_wants_autogroup(struct task_struct *p, struct task_group *tg);
33 autogroup_task_group(struct task_struct *p, struct task_group *tg) in autogroup_task_group() argument
38 if (enabled && task_wants_autogroup(p, tg)) in autogroup_task_group()
39 return p->signal->autogroup->tg; in autogroup_task_group()
41 return tg; in autogroup_task_group()
44 extern int autogroup_path(struct task_group *tg, char *buf, int buflen);
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H A Dautogroup.c37 autogroup_default.tg = &root_task_group; in autogroup_init()
44 void autogroup_free(struct task_group *tg) in autogroup_free() argument
46 kfree(tg->autogroup); in autogroup_free()
55 ag->tg->rt_se = NULL; in autogroup_destroy()
56 ag->tg->rt_rq = NULL; in autogroup_destroy()
58 sched_release_group(ag->tg); in autogroup_destroy()
59 sched_destroy_group(ag->tg); in autogroup_destroy()
90 struct task_group *tg; in autogroup_create() local
95 tg = sched_create_group(&root_task_group); in autogroup_create()
96 if (IS_ERR(tg)) in autogroup_create()
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H A Dext.h75 void scx_tg_init(struct task_group *tg);
76 int scx_tg_online(struct task_group *tg);
77 void scx_tg_offline(struct task_group *tg);
81 void scx_group_set_weight(struct task_group *tg, unsigned long cgrp_weight);
82 void scx_group_set_idle(struct task_group *tg, bool idle);
83 void scx_group_set_bandwidth(struct task_group *tg, u64 period_us, u64 quota_us, u64 burst_us);
85 static inline void scx_tg_init(struct task_group *tg) {} in scx_tg_init() argument
86 static inline int scx_tg_online(struct task_group *tg) { return 0; } in scx_tg_online() argument
87 static inline void scx_tg_offline(struct task_group *tg) {} in scx_tg_offline() argument
91 static inline void scx_group_set_weight(struct task_group *tg, unsigned long cgrp_weight) {} in scx_group_set_weight() argument
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H A Drt.c93 rt_rq->tg = &root_task_group; in init_rt_rq()
181 WARN_ON(!rt_group_sched_enabled() && rt_rq->tg != &root_task_group); in rq_of_rt_rq()
187 WARN_ON(!rt_group_sched_enabled() && rt_se->rt_rq->tg != &root_task_group); in rt_rq_of_se()
195 WARN_ON(!rt_group_sched_enabled() && rt_rq->tg != &root_task_group); in rq_of_rt_se()
199 void unregister_rt_sched_group(struct task_group *tg) in unregister_rt_sched_group() argument
204 if (tg->rt_se) in unregister_rt_sched_group()
205 destroy_rt_bandwidth(&tg->rt_bandwidth); in unregister_rt_sched_group()
208 void free_rt_sched_group(struct task_group *tg) in free_rt_sched_group() argument
216 if (tg->rt_rq) in free_rt_sched_group()
217 kfree(tg->rt_rq[i]); in free_rt_sched_group()
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/linux/drivers/gpu/drm/amd/display/dc/dce60/
H A Ddce60_timing_generator.c87 static void program_pix_dur(struct timing_generator *tg, uint32_t pix_clk_100hz) in program_pix_dur() argument
91 + DCE110TG_FROM_TG(tg)->offsets.dmif; in program_pix_dur()
92 uint32_t value = dm_read_reg(tg->ctx, addr); in program_pix_dur()
105 dm_write_reg(tg->ctx, addr, value); in program_pix_dur()
108 static void program_timing(struct timing_generator *tg, in program_timing() argument
119 program_pix_dur(tg, timing->pix_clk_100hz); in program_timing()
121 dce110_tg_program_timing(tg, timing, 0, 0, 0, 0, 0, 0, use_vbios); in program_timing()
125 struct timing_generator *tg, in dce60_timing_generator_enable_advanced_request() argument
129 struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); in dce60_timing_generator_enable_advanced_request()
131 uint32_t value = dm_read_reg(tg->ctx, addr); in dce60_timing_generator_enable_advanced_request()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
H A Ddcn10_hwseq.c111 !pipe_ctx->stream_res.tg || in dcn10_wait_for_pipe_update_if_needed()
122 struct timing_generator *tg = pipe_ctx->stream_res.tg; in dcn10_wait_for_pipe_update_if_needed() local
124 if (tg->funcs->is_tg_enabled && !tg->funcs->is_tg_enabled(tg)) in dcn10_wait_for_pipe_update_if_needed()
133 frame_count = tg->funcs->get_frame_count(tg); in dcn10_wait_for_pipe_update_if_needed()
184 !pipe_ctx->stream_res.tg || in dcn10_set_wait_for_update_needed_for_pipe()
194 struct timing_generator *tg = pipe_ctx->stream_res.tg; in dcn10_set_wait_for_update_needed_for_pipe() local
196 struct optc *optc1 = DCN10TG_FROM_TG(tg); in dcn10_set_wait_for_update_needed_for_pipe()
200 if (tg->funcs->is_tg_enabled && !tg->funcs->is_tg_enabled(tg)) in dcn10_set_wait_for_update_needed_for_pipe()
205 cur_frame = tg->funcs->get_frame_count(tg); in dcn10_set_wait_for_update_needed_for_pipe()
225 struct timing_generator *tg; in dcn10_lock_all_pipes() local
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/
H A Ddcn201_hwseq.c166 struct timing_generator *tg) in dcn201_init_blank() argument
180 tg->funcs->get_otg_active_size(tg, in dcn201_init_blank()
185 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1); in dcn201_init_blank()
273 struct timing_generator *tg = res_pool->timing_generators[i]; in dcn201_init_hw() local
275 if (tg->funcs->is_tg_enabled(tg)) { in dcn201_init_hw()
276 dcn201_init_blank(dc, tg); in dcn201_init_hw()
281 struct timing_generator *tg = res_pool->timing_generators[i]; in dcn201_init_hw() local
283 if (tg->funcs->is_tg_enabled(tg)) in dcn201_init_hw()
284 tg->funcs->lock(tg); in dcn201_init_hw()
305 struct timing_generator *tg = res_pool->timing_generators[i]; in dcn201_init_hw() local
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
H A Ddcn35_hwseq.c227 struct timing_generator *tg = dc->res_pool->timing_generators[i]; in dcn35_init_hw() local
231 if (tg) { in dcn35_init_hw()
232 if (tg->funcs->is_tg_enabled(tg) && tg->funcs->get_optc_source) { in dcn35_init_hw()
233 tg->funcs->get_optc_source(tg, &num_opps, in dcn35_init_hw()
347 DC_LOG_DSC("DSC is NULL for tg instance %d:", pipe_ctx->stream_res.tg->inst); in update_dsc_on_stream()
354 DC_LOG_DSC("DSC has been disabled for tg instance %d:", pipe_ctx->stream_res.tg->inst); in update_dsc_on_stream()
383 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst); in update_dsc_on_stream()
384 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, in update_dsc_on_stream()
390 pipe_ctx->stream_res.tg->funcs->set_dsc_config( in update_dsc_on_stream()
391 pipe_ctx->stream_res.tg, in update_dsc_on_stream()
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/linux/drivers/gpu/drm/amd/display/dc/dce80/
H A Ddce80_timing_generator.c87 static void program_pix_dur(struct timing_generator *tg, uint32_t pix_clk_100hz) in program_pix_dur() argument
91 + DCE110TG_FROM_TG(tg)->offsets.dmif; in program_pix_dur()
92 uint32_t value = dm_read_reg(tg->ctx, addr); in program_pix_dur()
105 dm_write_reg(tg->ctx, addr, value); in program_pix_dur()
108 static void dce80_timing_generator_program_timing(struct timing_generator *tg, in dce80_timing_generator_program_timing() argument
119 program_pix_dur(tg, timing->pix_clk_100hz); in dce80_timing_generator_program_timing()
121 dce110_tg_program_timing(tg, timing, 0, 0, 0, 0, 0, 0, use_vbios); in dce80_timing_generator_program_timing()
125 struct timing_generator *tg, in dce80_timing_generator_enable_advanced_request() argument
129 struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); in dce80_timing_generator_enable_advanced_request()
131 uint32_t value = dm_read_reg(tg->ctx, addr); in dce80_timing_generator_enable_advanced_request()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
H A Ddcn20_hwseq.c286 if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL) { in dcn20_setup_gsl_group_as_lock()
287 pipe_ctx->stream_res.tg->funcs->set_gsl( in dcn20_setup_gsl_group_as_lock()
288 pipe_ctx->stream_res.tg, in dcn20_setup_gsl_group_as_lock()
290 if (pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) in dcn20_setup_gsl_group_as_lock()
291 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select( in dcn20_setup_gsl_group_as_lock()
292 pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0); in dcn20_setup_gsl_group_as_lock()
407 struct timing_generator *tg) in dcn20_init_blank() argument
422 tg->funcs->get_otg_active_size(tg, in dcn20_init_blank()
427 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1); in dcn20_init_blank()
745 struct timing_generator *tg = is_phantom ? pipe_ctx->stream_res.tg : NULL; in dcn20_disable_plane() local
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dce/
H A Ddce_hwseq.c56 if (lock && pipe->stream_res.tg->funcs->is_blanked && in dce_pipe_control_lock()
57 pipe->stream_res.tg->funcs->is_blanked(pipe->stream_res.tg)) in dce_pipe_control_lock()
60 val = REG_GET_4(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], in dce_pipe_control_lock()
71 REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val, in dce_pipe_control_lock()
76 REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val, in dce_pipe_control_lock()
82 uint32_t value = REG_READ(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst]); in dce_pipe_control_lock()
83 REG_WRITE(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst], value); in dce_pipe_control_lock()
/linux/drivers/gpu/drm/amd/display/dc/link/accessories/
H A Dlink_dp_cts.c99 pipes[i]->stream_res.tg->funcs->disable_crtc(pipes[i]->stream_res.tg); in dp_retrain_link_dp_test()
141 pipes[i]->stream_res.tg->funcs->enable_crtc(pipes[i]->stream_res.tg); in dp_retrain_link_dp_test()
508 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern) { in set_crtc_test_pattern()
510 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg, in set_crtc_test_pattern()
547 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern) { in set_crtc_test_pattern()
549 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg, in set_crtc_test_pattern()
879 if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable) { in dp_set_test_pattern()
885 inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst; in dp_set_test_pattern()
892 pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable( in dp_set_test_pattern()
893 pipe_ctx->stream_res.tg); in dp_set_test_pattern()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/
H A Ddce110_hwseq.c672 struct timing_generator *tg = pipe_ctx->stream_res.tg; in dce110_enable_stream() local
691 tg->funcs->set_early_control(tg, early_control); in dce110_enable_stream()
1156 struct timing_generator *tg = pipe_ctx->stream_res.tg; in dce110_disable_stream() local
1184 dto_params.otg_inst = tg->inst; in dce110_disable_stream()
1189 dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst, dp_hpo_inst); in dce110_disable_stream()
1467 pipe_ctx->stream_res.tg->inst + 1); in build_audio_output()
1501 if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) { in program_scaler()
1510 pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color( in program_scaler()
1511 pipe_ctx->stream_res.tg, in program_scaler()
1534 pipe_ctx->stream_res.tg->funcs->set_blank_color( in dce110_enable_stream_timing()
[all …]
/linux/drivers/iio/chemical/
H A Dsgp40.c172 struct sgp40_tg_measure tg = {.command = {0x26, 0x0F}}; in sgp40_measure_resistance_raw() local
179 tg.rht_ticks = cpu_to_be16(ticks16); in sgp40_measure_resistance_raw()
180 tg.rht_crc = crc8(sgp40_crc8_table, (u8 *)&tg.rht_ticks, 2, SGP40_CRC8_INIT); in sgp40_measure_resistance_raw()
184 tg.temp_ticks = cpu_to_be16(ticks16); in sgp40_measure_resistance_raw()
185 tg.temp_crc = crc8(sgp40_crc8_table, (u8 *)&tg.temp_ticks, 2, SGP40_CRC8_INIT); in sgp40_measure_resistance_raw()
189 ret = i2c_master_send(client, (const char *)&tg, sizeof(tg)); in sgp40_measure_resistance_raw()
190 if (ret != sizeof(tg)) { in sgp40_measure_resistance_raw()
191 dev_warn(data->dev, "i2c_master_send ret: %d sizeof: %zu\n", ret, sizeof(tg)); in sgp40_measure_resistance_raw()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn314/
H A Ddcn314_hwseq.c90 DC_LOG_DSC("DSC is NULL for tg instance %d:", pipe_ctx->stream_res.tg->inst); in update_dsc_on_stream()
97 DC_LOG_DSC("DSC has been disabled for tg instance %d:", pipe_ctx->stream_res.tg->inst); in update_dsc_on_stream()
127 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst); in update_dsc_on_stream()
128 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, in update_dsc_on_stream()
134 pipe_ctx->stream_res.tg->funcs->set_dsc_config( in update_dsc_on_stream()
135 pipe_ctx->stream_res.tg, in update_dsc_on_stream()
185 pipe_ctx->stream_res.tg->funcs->set_odm_combine( in dcn314_update_odm()
186 pipe_ctx->stream_res.tg, in dcn314_update_odm()
190 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( in dcn314_update_odm()
191 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); in dcn314_update_odm()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn31/
H A Ddcn31_hwseq.c195 struct timing_generator *tg = dc->res_pool->timing_generators[i]; in dcn31_init_hw() local
199 if (tg) { in dcn31_init_hw()
200 if (tg->funcs->is_tg_enabled(tg) && tg->funcs->get_optc_source) { in dcn31_init_hw()
201 tg->funcs->get_optc_source(tg, &num_opps, in dcn31_init_hw()
539 pipe_ctx->stream_res.tg->funcs->set_dsc_config( in dcn31_reset_back_end_for_pipe()
540 pipe_ctx->stream_res.tg, in dcn31_reset_back_end_for_pipe()
543 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); in dcn31_reset_back_end_for_pipe()
545 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); in dcn31_reset_back_end_for_pipe()
546 if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass) in dcn31_reset_back_end_for_pipe()
547 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( in dcn31_reset_back_end_for_pipe()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.c777 dc->res_pool->dccg, pipe_ctx->stream_res.tg->inst, in dcn401_enable_stream_timing()
786 pipe_ctx->stream_res.tg->funcs->set_odm_combine( in dcn401_enable_stream_timing()
787 pipe_ctx->stream_res.tg, in dcn401_enable_stream_timing()
795 …s_pool->dccg->funcs->set_dtbclk_p_src(dc->res_pool->dccg, DPREFCLK, pipe_ctx->stream_res.tg->inst); in dcn401_enable_stream_timing()
802 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true); in dcn401_enable_stream_timing()
823 pipe_ctx->stream_res.tg->funcs->program_timing( in dcn401_enable_stream_timing()
824 pipe_ctx->stream_res.tg, in dcn401_enable_stream_timing()
851 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) { in dcn401_enable_stream_timing()
863 if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control) in dcn401_enable_stream_timing()
864 pipe_ctx->stream_res.tg->funcs->set_static_screen_control( in dcn401_enable_stream_timing()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
H A Ddcn30_hwseq.c840 if (enable && pipe_ctx->stream_res.tg->funcs->is_tg_enabled(pipe_ctx->stream_res.tg)) { in dcn30_set_avmute()
841 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE); in dcn30_set_avmute()
842 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK); in dcn30_set_avmute()
843 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE); in dcn30_set_avmute()
844 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK); in dcn30_set_avmute()
845 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE); in dcn30_set_avmute()
1207 struct timing_generator *tg = pipe_ctx->stream_res.tg; in dcn30_wait_for_all_pending_updates() local
1211 if (tg && tg->funcs->is_tg_enabled(tg)) { in dcn30_wait_for_all_pending_updates()
1215 if (tg->funcs->get_optc_double_buffer_pending) in dcn30_wait_for_all_pending_updates()
1216 pending_updates |= tg->funcs->get_optc_double_buffer_pending(tg); in dcn30_wait_for_all_pending_updates()
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