| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn35/ |
| H A D | dcn35_dpp.c | 31 #define REG(reg) dpp->tf_regs->reg
131 uint32_t inst, const struct dcn3_dpp_registers *tf_regs, in dpp35_construct() argument
135 bool ret = dpp32_construct(dpp, ctx, inst, tf_regs, in dpp35_construct()
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| H A D | dcn35_dpp.h | 58 uint32_t inst, const struct dcn3_dpp_registers *tf_regs,
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn201/ |
| H A D | dcn201_dpp.h | 60 const struct dcn201_dpp_registers *tf_regs; member
79 const struct dcn201_dpp_registers *tf_regs,
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| H A D | dcn201_dpp.c | 35 dpp->tf_regs->reg
301 const struct dcn201_dpp_registers *tf_regs, in dpp201_construct() argument
311 dpp->tf_regs = tf_regs; in dpp201_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn32/ |
| H A D | dcn32_dpp.c | 151 const struct dcn3_dpp_registers *tf_regs, in dpp32_construct() argument
161 dpp->tf_regs = tf_regs; in dpp32_construct()
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| H A D | dcn32_dpp.h | 34 const struct dcn3_dpp_registers *tf_regs,
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn401/ |
| H A D | dcn401_dpp.c | 36 dpp->tf_regs->reg
266 const struct dcn401_dpp_registers *tf_regs, in dpp401_construct() argument
276 dpp->tf_regs = tf_regs; in dpp401_construct()
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| H A D | dcn401_dpp_cm.c | 43 dpp->tf_regs->reg
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn20/ |
| H A D | dcn20_dpp.c | 42 dpp->tf_regs->reg
410 const struct dcn2_dpp_registers *tf_regs, in dpp2_construct() argument
420 dpp->tf_regs = tf_regs; in dpp2_construct()
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| H A D | dcn20_dpp.h | 680 const struct dcn2_dpp_registers *tf_regs; member
778 const struct dcn2_dpp_registers *tf_regs,
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| H A D | dcn20_dpp_cm.c | 37 dpp->tf_regs->reg
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn10/ |
| H A D | dcn10_dpp.c | 42 dpp->tf_regs->reg
585 const struct dcn_dpp_registers *tf_regs, in dpp1_construct() argument
595 dpp->tf_regs = tf_regs; in dpp1_construct()
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| H A D | dcn10_dpp_dscl.c | 44 dpp->tf_regs->reg
163 if (dpp->tf_regs->DSCL_MEM_PWR_CTRL) { in dpp1_power_on_dscl()
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| H A D | dcn10_dpp_cm.c | 43 dpp->tf_regs->reg
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn201/ |
| H A D | dcn201_resource.c | 464 #define tf_regs(id)\ macro
469 static const struct dcn201_dpp_registers tf_regs[] = { variable
470 tf_regs(0),
471 tf_regs(1),
472 tf_regs(2),
473 tf_regs(3),
642 &tf_regs[inst], &tf_shift, &tf_mask)) in dcn201_dpp_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn21/ |
| H A D | dcn21_resource.c | 449 #define tf_regs(id)\ macro
455 static const struct dcn2_dpp_registers tf_regs[] = { variable
456 tf_regs(0),
457 tf_regs(1),
458 tf_regs(2),
459 tf_regs(3),
530 &tf_regs[inst], &tf_shift, &tf_mask)) in dcn21_dpp_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn10/ |
| H A D | dcn10_resource.c | 349 #define tf_regs(id)\ macro
354 static const struct dcn_dpp_registers tf_regs[] = { variable
355 tf_regs(0),
356 tf_regs(1),
357 tf_regs(2),
358 tf_regs(3),
611 &tf_regs[inst], &tf_shift, &tf_mask); in dcn10_dpp_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| H A D | dcn20_resource.c | 414 #define tf_regs(id)\ macro
420 static const struct dcn2_dpp_registers tf_regs[] = { variable
421 tf_regs(0),
422 tf_regs(1),
423 tf_regs(2),
424 tf_regs(3),
425 tf_regs(4),
426 tf_regs(5),
773 &tf_regs[inst], &tf_shift, &tf_mask)) in dcn20_dpp_create()
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn30/ |
| H A D | dcn30_dpp.c | 34 dpp->tf_regs->reg
1527 const struct dcn3_dpp_registers *tf_regs, in dpp3_construct() argument
1537 dpp->tf_regs = tf_regs; in dpp3_construct()
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| H A D | dcn30_dpp.h | 563 const struct dcn3_dpp_registers *tf_regs; member
583 const struct dcn3_dpp_registers *tf_regs,
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| H A D | dcn30_dpp_cm.c | 34 dpp->tf_regs->reg
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