| /linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_dkl_phy_regs.h | 31 #define _DKL_REG_PHY_BASE(tc_port) _PORT(tc_port, \ argument
41 #define _DKL_REG(tc_port, phy_offset) \ argument
43 .reg = _DKL_REG_PHY_BASE(tc_port) + \
48 #define _DKL_REG_LN(tc_port, ln_idx, ln0_offs, ln1_offs) \ argument
49 _DKL_REG(tc_port, (ln0_offs) + (ln_idx) * ((ln1_offs) - (ln0_offs)))
53 #define DKL_PCS_DW5(tc_port, ln) _DKL_REG_LN(tc_port, ln, \ argument
59 #define DKL_PLL_DIV0(tc_port) _DKL_REG(tc_port, \ argument
78 #define DKL_PLL_DIV1(tc_port) _DKL_REG(tc_port, \ argument
86 #define DKL_PLL_SSC(tc_port) _DKL_REG(tc_port, \ argument
97 #define DKL_PLL_BIAS(tc_port) _DKL_REG(tc_port, \ argument
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| H A D | intel_mg_phy_regs.h | 11 #define MG_PHY_PORT_LN(ln, tc_port, ln0p1, ln0p2, ln1p1) \ argument
12 _MMIO(_PORT(tc_port, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
18 #define MG_TX1_LINK_PARAMS(ln, tc_port) \ argument
19 MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
27 #define MG_TX2_LINK_PARAMS(ln, tc_port) \ argument
28 MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
37 #define MG_TX1_PISO_READLOAD(ln, tc_port) \ argument
38 MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
46 #define MG_TX2_PISO_READLOAD(ln, tc_port) \ argument
47 MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
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| H A D | intel_dkl_phy.c | 26 enum tc_port tc_port = DKL_REG_TC_PORT(reg); in dkl_phy_set_hip_idx() local
29 tc_port < TC_PORT_1 || tc_port >= I915_MAX_TC_PORTS)) in dkl_phy_set_hip_idx()
33 HIP_INDEX_REG(tc_port), in dkl_phy_set_hip_idx()
34 HIP_INDEX_VAL(tc_port, reg.bank_idx)); in dkl_phy_set_hip_idx()
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| H A D | intel_tc.c | 252 enum tc_port tc_port = intel_encoder_to_tc(&tc->dig_port->base); in tc_port_power_domain() local
254 if (tc_port == TC_PORT_NONE) in tc_port_power_domain()
257 return POWER_DOMAIN_PORT_DDI_LANES_TC1 + tc_port - TC_PORT_1; in tc_port_power_domain()
296 enum tc_port tc_port = intel_encoder_to_tc(&tc->dig_port->base); in get_pin_assignment() local
306 reg = TCSS_DDI_STATUS(tc_port); in get_pin_assignment()
492 enum tc_port tc_port = intel_encoder_to_tc(&tc->dig_port->base); in tc_phy_load_fia_params() local
499 tc->phy_fia = tc_port / 2; in tc_phy_load_fia_params()
500 tc->phy_fia_idx = tc_port % 2; in tc_phy_load_fia_params()
503 tc->phy_fia_idx = tc_port; in tc_phy_load_fia_params()
848 enum tc_port tc_port = intel_encoder_to_tc(&tc->dig_port->base); in adlp_tc_phy_is_ready() local
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| H A D | intel_display_power_well.c | 573 enum tc_port tc_port; in icl_tc_phy_aux_power_well_enable() local
575 tc_port = TGL_AUX_PW_TO_TC_PORT(i915_power_well_instance(power_well)->hsw.idx); in icl_tc_phy_aux_power_well_enable()
577 ret = poll_timeout_us(val = intel_dkl_phy_read(display, DKL_CMN_UC_DW_27(tc_port)), in icl_tc_phy_aux_power_well_enable()
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| H A D | intel_display.c | 1876 enum tc_port intel_port_to_tc(struct intel_display *display, enum port port) in intel_port_to_tc()
1889 enum tc_port intel_tc_phy_port_to_tc(struct intel_display *display, enum port port) in intel_tc_phy_port_to_tc()
1929 enum tc_port intel_encoder_to_tc(struct intel_encoder *encoder) in intel_encoder_to_tc()
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| /linux/drivers/platform/chrome/ |
| H A D | cros_ec_typec.c | 47 static int cros_typec_enter_usb_mode(struct typec_port *tc_port, enum usb_mode mode) in cros_typec_enter_usb_mode() argument
49 struct cros_typec_port *port = typec_get_drvdata(tc_port); in cros_typec_enter_usb_mode()
61 static int cros_typec_perform_role_swap(struct typec_port *tc_port, int target_role, u8 swap_type) in cros_typec_perform_role_swap() argument
63 struct cros_typec_port *port = typec_get_drvdata(tc_port); in cros_typec_perform_role_swap()
114 typec_set_data_role(tc_port, target_role); in cros_typec_perform_role_swap()
122 typec_set_pwr_role(tc_port, target_role); in cros_typec_perform_role_swap()
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