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Searched refs:subop (Results 1 – 24 of 24) sorted by relevance

/linux/drivers/net/ethernet/fungible/funcore/
H A Dfun_hci.h151 __u8 subop; member
159 .subop = (_subop), .flags = cpu_to_be16(_flags), \
185 __u8 subop; member
215 __u8 subop; member
242 __u8 subop; member
259 .subop = (_subop), .flags = cpu_to_be16(_flags), \
276 .subop = (_subop), .flags = cpu_to_be16(_flags), \
297 __u8 subop; member
334 .subop = (_subop), .flags = cpu_to_be16(_flags), \
472 __u8 subop; /* see fun_data_subop enum */ member
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/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvpe_6_1_fw_if.h59 #define VPE_CMD_HEADER(op, subop) \ argument
60 (((subop << VPE_HEADER_SUB_OPCODE__SHIFT) & VPE_HEADER_SUB_OPCODE_MASK) | \
142 #define VPE_PLANE_CFG_CMD_HEADER(subop, nps0, npd0, nps1, npd1) \ argument
143 (VPE_CMD_HEADER(VPE_CMD_OPCODE_PLANE_CFG, subop) | \
163 #define VPE_DIR_CFG_CMD_HEADER(subop, arr_sz) \ argument
164 (VPE_CMD_HEADER(VPE_CMD_OPCODE_VPEP_CFG, subop) | \
179 #define VPE_IND_CFG_CMD_HEADER(subop, num_dst) \ argument
180 (VPE_CMD_HEADER(VPE_CMD_OPCODE_VPEP_CFG, subop) | \
/linux/arch/parisc/math-emu/
H A Dfpudispatch.c184 u_int class, subop; in fpudispatch() local
197 subop = get_subop1_PA2_0(ir); in fpudispatch()
199 subop = get_subop1_PA1_1(ir); in fpudispatch()
202 subop = get_subop(ir); in fpudispatch()
204 if (FPUDEBUG) printk("class %d subop %d\n", class, subop); in fpudispatch()
209 return(decode_0c(ir,class,subop,fpregs)); in fpudispatch()
211 return(decode_0e(ir,class,subop,fpregs)); in fpudispatch()
239 u_int class, subop, major; in emfpudispatch() local
251 subop = get_subop1_PA2_0(ir); in emfpudispatch()
253 subop = get_subop1_PA1_1(ir); in emfpudispatch()
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/linux/drivers/mtd/nand/raw/
H A Darasan-nand-controller.c596 const struct nand_subop *subop, in anfc_parse_instructions() argument
610 for (op_id = 0; op_id < subop->ninstrs; op_id++) { in anfc_parse_instructions()
615 instr = &subop->instrs[op_id]; in anfc_parse_instructions()
628 offset = nand_subop_get_addr_start_off(subop, op_id); in anfc_parse_instructions()
629 naddrs = nand_subop_get_num_addr_cyc(subop, op_id); in anfc_parse_instructions()
645 offset = nand_subop_get_data_start_off(subop, op_id); in anfc_parse_instructions()
648 nfc_op->len = nand_subop_get_data_len(subop, op_id); in anfc_parse_instructions()
724 const struct nand_subop *subop, in anfc_misc_data_type_exec() argument
731 ret = anfc_parse_instructions(chip, subop, &nfc_op); in anfc_misc_data_type_exec()
748 const struct nand_subop *subop) in anfc_param_read_type_exec() argument
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H A Dvf610_nfc.c348 vf610_get_next_instr(const struct nand_subop *subop, int *op_id) in vf610_get_next_instr() argument
350 if (*op_id + 1 >= subop->ninstrs) in vf610_get_next_instr()
355 return &subop->instrs[*op_id]; in vf610_get_next_instr()
359 const struct nand_subop *subop) in vf610_nfc_cmd() argument
373 instr = vf610_get_next_instr(subop, &op_id); in vf610_nfc_cmd()
381 instr = vf610_get_next_instr(subop, &op_id); in vf610_nfc_cmd()
385 int naddrs = nand_subop_get_num_addr_cyc(subop, op_id); in vf610_nfc_cmd()
386 int i = nand_subop_get_addr_start_off(subop, op_id); in vf610_nfc_cmd()
398 instr = vf610_get_next_instr(subop, &op_id); in vf610_nfc_cmd()
402 trfr_sz = nand_subop_get_data_len(subop, op_id); in vf610_nfc_cmd()
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H A Dloongson-nand-controller.c201 static int loongson_nand_parse_instructions(struct nand_chip *chip, const struct nand_subop *subop, in loongson_nand_parse_instructions() argument
207 for (op_id = 0; op_id < subop->ninstrs; op_id++) { in loongson_nand_parse_instructions()
208 const struct nand_op_instr *instr = &subop->instrs[op_id]; in loongson_nand_parse_instructions()
220 naddrs = nand_subop_get_num_addr_cyc(subop, op_id); in loongson_nand_parse_instructions()
224 offset = nand_subop_get_addr_start_off(subop, op_id); in loongson_nand_parse_instructions()
230 offset = nand_subop_get_data_start_off(subop, op_id); in loongson_nand_parse_instructions()
231 op->orig_len = nand_subop_get_data_len(subop, op_id); in loongson_nand_parse_instructions()
472 static int loongson_nand_data_type_exec(struct nand_chip *chip, const struct nand_subop *subop) in loongson_nand_data_type_exec() argument
478 ret = loongson_nand_parse_instructions(chip, subop, &op); in loongson_nand_data_type_exec()
491 static int loongson_nand_misc_type_exec(struct nand_chip *chip, const struct nand_subop *subop, in loongson_nand_misc_type_exec() argument
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H A Dnand_base.c2306 struct nand_subop subop; member
2380 unsigned int instr_offset = ctx->subop.first_instr_start_off; in nand_op_parser_match_pat()
2382 const struct nand_op_instr *instr = ctx->subop.instrs; in nand_op_parser_match_pat()
2443 ctx->subop.ninstrs = ninstrs; in nand_op_parser_match_pat()
2444 ctx->subop.last_instr_end_off = instr_offset; in nand_op_parser_match_pat()
2456 pr_debug("executing subop (CS%d):\n", ctx->subop.cs); in nand_op_parser_trace()
2461 if (instr == &ctx->subop.instrs[0]) in nand_op_parser_trace()
2466 if (instr == &ctx->subop.instrs[ctx->subop.ninstrs - 1]) in nand_op_parser_trace()
2480 if (a->subop.ninstrs < b->subop.ninstrs) in nand_op_parser_cmp_ctx()
2482 else if (a->subop.ninstrs > b->subop.ninstrs) in nand_op_parser_cmp_ctx()
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H A Dmarvell_nand.c1713 const struct nand_subop *subop, in marvell_nfc_parse_instructions() argument
1725 for (op_id = 0; op_id < subop->ninstrs; op_id++) { in marvell_nfc_parse_instructions()
1730 instr = &subop->instrs[op_id]; in marvell_nfc_parse_instructions()
1747 offset = nand_subop_get_addr_start_off(subop, op_id); in marvell_nfc_parse_instructions()
1748 naddrs = nand_subop_get_num_addr_cyc(subop, op_id); in marvell_nfc_parse_instructions()
1774 len = nand_subop_get_data_len(subop, op_id); in marvell_nfc_parse_instructions()
1788 len = nand_subop_get_data_len(subop, op_id); in marvell_nfc_parse_instructions()
1803 const struct nand_subop *subop, in marvell_nfc_xfer_data_pio() argument
1809 unsigned int len = nand_subop_get_data_len(subop, op_id); in marvell_nfc_xfer_data_pio()
1810 unsigned int offset = nand_subop_get_data_start_off(subop, op_id); in marvell_nfc_xfer_data_pio()
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H A Dqcom_nandc.c1601 const struct nand_subop *subop, in qcom_parse_instructions() argument
1608 for (op_id = 0; op_id < subop->ninstrs; op_id++) { in qcom_parse_instructions()
1612 instr = &subop->instrs[op_id]; in qcom_parse_instructions()
1625 offset = nand_subop_get_addr_start_off(subop, op_id); in qcom_parse_instructions()
1626 naddrs = nand_subop_get_num_addr_cyc(subop, op_id); in qcom_parse_instructions()
1689 const struct nand_subop *subop) in qcom_read_status_exec() argument
1703 ret = qcom_parse_instructions(chip, subop, &q_op); in qcom_read_status_exec()
1746 len = nand_subop_get_data_len(subop, op_id); in qcom_read_status_exec()
1753 static int qcom_read_id_type_exec(struct nand_chip *chip, const struct nand_subop *subop) in qcom_read_id_type_exec() argument
1763 ret = qcom_parse_instructions(chip, subop, &q_op); in qcom_read_id_type_exec()
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H A Dtegra_nand.c351 const struct nand_subop *subop) in tegra_nand_cmd() argument
361 for (op_id = 0; op_id < subop->ninstrs; op_id++) { in tegra_nand_cmd()
366 instr = &subop->instrs[op_id]; in tegra_nand_cmd()
383 offset = nand_subop_get_addr_start_off(subop, op_id); in tegra_nand_cmd()
384 naddrs = nand_subop_get_num_addr_cyc(subop, op_id); in tegra_nand_cmd()
399 size = nand_subop_get_data_len(subop, op_id); in tegra_nand_cmd()
400 offset = nand_subop_get_data_start_off(subop, op_id); in tegra_nand_cmd()
409 size = nand_subop_get_data_len(subop, op_id); in tegra_nand_cmd()
410 offset = nand_subop_get_data_start_off(subop, op_id); in tegra_nand_cmd()
H A Dcadence-nand-controller.c2092 const struct nand_subop *subop) in cadence_nand_cmd_opcode() argument
2101 instr = &subop->instrs[op_id]; in cadence_nand_cmd_opcode()
2122 const struct nand_subop *subop) in cadence_nand_cmd_address() argument
2135 instr = &subop->instrs[op_id]; in cadence_nand_cmd_address()
2143 offset = nand_subop_get_addr_start_off(subop, op_id); in cadence_nand_cmd_address()
2144 naddrs = nand_subop_get_num_addr_cyc(subop, op_id); in cadence_nand_cmd_address()
2165 const struct nand_subop *subop) in cadence_nand_cmd_erase() argument
2169 if (subop->instrs[0].ctx.cmd.opcode == NAND_CMD_ERASE1) { in cadence_nand_cmd_erase()
2176 instr = &subop->instrs[1]; in cadence_nand_cmd_erase()
2177 offset = nand_subop_get_addr_start_off(subop, 1); in cadence_nand_cmd_erase()
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H A Dpl35x-nand-controller.c663 const struct nand_subop *subop) in pl35x_nand_exec_op() argument
675 for (op_id = 0; op_id < subop->ninstrs; op_id++) { in pl35x_nand_exec_op()
676 instr = &subop->instrs[op_id]; in pl35x_nand_exec_op()
691 offset = nand_subop_get_addr_start_off(subop, op_id); in pl35x_nand_exec_op()
692 naddrs = nand_subop_get_num_addr_cyc(subop, op_id); in pl35x_nand_exec_op()
707 len = nand_subop_get_data_len(subop, op_id); in pl35x_nand_exec_op()
H A Drockchip-nand-controller.c332 const struct nand_subop *subop) in rk_nfc_cmd() argument
342 for (i = 0; i < subop->ninstrs; i++) { in rk_nfc_cmd()
343 const struct nand_op_instr *instr = &subop->instrs[i]; in rk_nfc_cmd()
352 remaining = nand_subop_get_num_addr_cyc(subop, i); in rk_nfc_cmd()
353 start = nand_subop_get_addr_start_off(subop, i); in rk_nfc_cmd()
362 start = nand_subop_get_data_start_off(subop, i); in rk_nfc_cmd()
363 cnt = nand_subop_get_data_len(subop, i); in rk_nfc_cmd()
H A Dsunxi_nand.c1944 const struct nand_subop *subop) in sunxi_nfc_exec_subop() argument
1952 for (i = 0; i < subop->ninstrs; i++) { in sunxi_nfc_exec_subop()
1953 const struct nand_op_instr *instr = &subop->instrs[i]; in sunxi_nfc_exec_subop()
1970 remaining = nand_subop_get_num_addr_cyc(subop, i); in sunxi_nfc_exec_subop()
1971 start = nand_subop_get_addr_start_off(subop, i); in sunxi_nfc_exec_subop()
1985 start = nand_subop_get_data_start_off(subop, i); in sunxi_nfc_exec_subop()
1986 remaining = nand_subop_get_data_len(subop, i); in sunxi_nfc_exec_subop()
2040 const struct nand_subop *subop) in sunxi_nfc_soft_waitrdy() argument
2043 subop->instrs[0].ctx.waitrdy.timeout_ms); in sunxi_nfc_soft_waitrdy()
/linux/drivers/acpi/acpica/
H A Dpsargs.c745 u32 subop; in acpi_ps_get_next_arg() local
843 subop = acpi_ps_peek_opcode(parser_state); in acpi_ps_get_next_arg()
844 if (subop == 0 || in acpi_ps_get_next_arg()
845 acpi_ps_is_leading_char(subop) || in acpi_ps_get_next_arg()
846 ACPI_IS_ROOT_PREFIX(subop) || in acpi_ps_get_next_arg()
847 ACPI_IS_PARENT_PREFIX(subop)) { in acpi_ps_get_next_arg()
881 subop = acpi_ps_peek_opcode(parser_state); in acpi_ps_get_next_arg()
882 if (subop == 0 || in acpi_ps_get_next_arg()
883 acpi_ps_is_leading_char(subop) || in acpi_ps_get_next_arg()
884 ACPI_IS_ROOT_PREFIX(subop) || in acpi_ps_get_next_arg()
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/linux/drivers/gpu/host1x/hw/
H A Ddebug_hw.c44 unsigned int mask, subop, num, opcode; in show_channel_command() local
142 subop = val >> 24 & 0xf; in show_channel_command()
143 if (subop == HOST1X_OPCODE_EXTEND_ACQUIRE_MLOCK) in show_channel_command()
146 else if (subop == HOST1X_OPCODE_EXTEND_RELEASE_MLOCK) in show_channel_command()
/linux/drivers/net/ethernet/fungible/funeth/
H A Dfuneth_ktls.c11 .subop = FUN_ADMIN_SUBOP_CREATE, in fun_admin_ktls_create()
27 .subop = FUN_ADMIN_SUBOP_MODIFY, in fun_ktls_add()
86 req.subop = FUN_ADMIN_SUBOP_MODIFY; in fun_ktls_del()
110 req.subop = FUN_ADMIN_SUBOP_MODIFY; in fun_ktls_resync()
H A Dfuneth_main.c159 .u.write.subop = FUN_ADMIN_SUBOP_WRITE, in fun_adi_write()
1908 if (rsp->subop == FUN_ADMIN_SUBOP_NOTIFY) { in fun_event_cb()
1910 } else if (rsp->subop == FUN_ADMIN_SUBOP_RES_COUNT) { in fun_event_cb()
1920 op, rsp->subop); in fun_event_cb()
/linux/drivers/scsi/csiostor/
H A Dcsio_isr.c151 uint8_t subop; in csio_process_scsi_cmpl() local
158 subop = FW_SCSI_ABRT_CLS_WR_SUB_OPCODE_GET( in csio_process_scsi_cmpl()
163 subop ? "Close" : "Abort", in csio_process_scsi_cmpl()
167 if (subop) in csio_process_scsi_cmpl()
/linux/include/linux/mtd/
H A Drawnand.h869 unsigned int nand_subop_get_addr_start_off(const struct nand_subop *subop,
871 unsigned int nand_subop_get_num_addr_cyc(const struct nand_subop *subop,
873 unsigned int nand_subop_get_data_start_off(const struct nand_subop *subop,
875 unsigned int nand_subop_get_data_len(const struct nand_subop *subop,
966 int (*exec)(struct nand_chip *chip, const struct nand_subop *subop);
/linux/drivers/mtd/nand/raw/atmel/
H A Dnand-controller.c633 const struct nand_subop *subop) in atmel_hsmc_exec_cmd_addr() argument
642 for (i = 0; i < subop->ninstrs; i++) { in atmel_hsmc_exec_cmd_addr()
643 const struct nand_op_instr *instr = &subop->instrs[i]; in atmel_hsmc_exec_cmd_addr()
650 for (j = nand_subop_get_addr_start_off(subop, i); in atmel_hsmc_exec_cmd_addr()
651 j < nand_subop_get_num_addr_cyc(subop, i); j++) { in atmel_hsmc_exec_cmd_addr()
661 const struct nand_subop *subop) in atmel_hsmc_exec_rw() argument
663 const struct nand_op_instr *instr = subop->instrs; in atmel_hsmc_exec_rw()
679 const struct nand_subop *subop) in atmel_hsmc_exec_waitrdy() argument
681 const struct nand_op_instr *instr = subop->instrs; in atmel_hsmc_exec_waitrdy()
/linux/drivers/gpu/drm/xe/
H A Dxe_vm_types.h448 enum xe_vma_subop subop; member
H A Dxe_pt.c1473 if (op->subop == XE_VMA_SUBOP_MAP_RANGE) { in op_check_svm_userptr()
2244 if (op->subop == XE_VMA_SUBOP_MAP_RANGE) { in op_prepare()
2250 } else if (op->subop == XE_VMA_SUBOP_UNMAP_RANGE) { in op_prepare()
2467 if (op->subop == XE_VMA_SUBOP_MAP_RANGE) in op_commit()
2469 else if (op->subop == XE_VMA_SUBOP_UNMAP_RANGE) in op_commit()
H A Dxe_vm.c793 op->subop = XE_VMA_SUBOP_MAP_RANGE; in xe_vm_populate_range_rebind()
882 op->subop = XE_VMA_SUBOP_UNMAP_RANGE; in xe_vm_populate_range_unbind()