Searched refs:state_array (Results 1 – 13 of 13) sorted by relevance
89 while (net_bw_of_new_state > calculate_net_bw_in_mbytes_sec(socbb, &table->state_array[index])) { in insert_entry_into_table_sorted()96 table->state_array[i] = table->state_array[i - 1]; in insert_entry_into_table_sorted()101 table->state_array[index] = *entry; in insert_entry_into_table_sorted()102 table->state_array[index].dcfclk_mhz = (int)entry->dcfclk_mhz; in insert_entry_into_table_sorted()103 table->state_array[index].fabricclk_mhz = (int)entry->fabricclk_mhz; in insert_entry_into_table_sorted()104 table->state_array[index].dram_speed_mts = (int)entry->dram_speed_mts; in insert_entry_into_table_sorted()117 table->state_array[i] = table->state_array[i + 1]; in remove_entry_from_table_at_index()119 memset(&table->state_array[--table->num_states], 0, sizeof(struct soc_state_bounding_box_st)); in remove_entry_from_table_at_index()126 unsigned int min_fclk_mhz = p->in_states->state_array[0].fabricclk_mhz; in dml2_policy_build_synthetic_soc_states()127 unsigned int min_dcfclk_mhz = p->in_states->state_array[0].dcfclk_mhz; in dml2_policy_build_synthetic_soc_states()[all …]
360 p->in_states->state_array[0].socclk_mhz = 620.0; in dml2_init_soc_states()361 p->in_states->state_array[0].dscclk_mhz = 716.667; in dml2_init_soc_states()362 p->in_states->state_array[0].phyclk_mhz = 810; in dml2_init_soc_states()363 p->in_states->state_array[0].phyclk_d18_mhz = 667; in dml2_init_soc_states()364 p->in_states->state_array[0].phyclk_d32_mhz = 625; in dml2_init_soc_states()365 p->in_states->state_array[0].dtbclk_mhz = 1564.0; in dml2_init_soc_states()366 p->in_states->state_array[0].fabricclk_mhz = 450.0; in dml2_init_soc_states()367 p->in_states->state_array[0].dcfclk_mhz = 300.0; in dml2_init_soc_states()368 p->in_states->state_array[0].dispclk_mhz = 2150.0; in dml2_init_soc_states()369 p->in_states->state_array[0].dppclk_mhz = 2150.0; in dml2_init_soc_states()[all …]
364 …context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = in_ctx->v20.dml_core_ctx.states.state_array[… in dml2_calculate_rq_and_dlg_params()366 …context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = in_ctx->v20.dml_core_ctx.states.state_array… in dml2_calculate_rq_and_dlg_params()
1268 …struct soc_state_bounding_box_st state_array[__DML_MAX_STATE_ARRAY_SIZE__]; /// <brief fixed size … member
10054 return (states->state_array[state_idx]); in dml_get_soc_state_bounding_box()
1688 struct _StateArray *state_array; in trinity_parse_power_table() local1703 state_array = (struct _StateArray *) in trinity_parse_power_table()1714 state_array->ucNumEntries); in trinity_parse_power_table()1717 power_state_offset = (u8 *)state_array->states; in trinity_parse_power_table()1718 for (i = 0; i < state_array->ucNumEntries; i++) { in trinity_parse_power_table()1755 rdev->pm.dpm.num_ps = state_array->ucNumEntries; in trinity_parse_power_table()
1457 struct _StateArray *state_array; in sumo_parse_power_table() local1472 state_array = (struct _StateArray *) in sumo_parse_power_table()1483 state_array->ucNumEntries); in sumo_parse_power_table()1486 power_state_offset = (u8 *)state_array->states; in sumo_parse_power_table()1487 for (i = 0; i < state_array->ucNumEntries; i++) { in sumo_parse_power_table()1523 rdev->pm.dpm.num_ps = state_array->ucNumEntries; in sumo_parse_power_table()
2435 struct _StateArray *state_array; in kv_parse_power_table() local2450 state_array = (struct _StateArray *) in kv_parse_power_table()2461 state_array->ucNumEntries); in kv_parse_power_table()2464 power_state_offset = (u8 *)state_array->states; in kv_parse_power_table()2465 for (i = 0; i < state_array->ucNumEntries; i++) { in kv_parse_power_table()2500 rdev->pm.dpm.num_ps = state_array->ucNumEntries; in kv_parse_power_table()
2665 struct _StateArray *state_array; in radeon_atombios_parse_power_table_6() local2681 state_array = (struct _StateArray *) in radeon_atombios_parse_power_table_6()2690 if (state_array->ucNumEntries == 0) in radeon_atombios_parse_power_table_6()2693 state_array->ucNumEntries); in radeon_atombios_parse_power_table_6()2696 power_state_offset = (u8 *)state_array->states; in radeon_atombios_parse_power_table_6()2697 for (i = 0; i < state_array->ucNumEntries; i++) { in radeon_atombios_parse_power_table_6()
6758 struct _StateArray *state_array; in si_parse_power_table() local6773 state_array = (struct _StateArray *) in si_parse_power_table()6784 state_array->ucNumEntries); in si_parse_power_table()6787 power_state_offset = (u8 *)state_array->states; in si_parse_power_table()6788 for (i = 0; i < state_array->ucNumEntries; i++) { in si_parse_power_table()6823 rdev->pm.dpm.num_ps = state_array->ucNumEntries; in si_parse_power_table()
5494 struct _StateArray *state_array; in ci_parse_power_table() local5510 state_array = (struct _StateArray *) in ci_parse_power_table()5521 state_array->ucNumEntries); in ci_parse_power_table()5524 power_state_offset = (u8 *)state_array->states; in ci_parse_power_table()5526 for (i = 0; i < state_array->ucNumEntries; i++) { in ci_parse_power_table()
2700 struct _StateArray *state_array; in kv_parse_power_table() local2717 state_array = (struct _StateArray *) in kv_parse_power_table()2728 state_array->ucNumEntries); in kv_parse_power_table()2731 power_state_offset = (u8 *)state_array->states; in kv_parse_power_table()2732 for (i = 0; i < state_array->ucNumEntries; i++) { in kv_parse_power_table()2763 adev->pm.dpm.num_ps = state_array->ucNumEntries; in kv_parse_power_table()
7319 struct _StateArray *state_array; in si_parse_power_table() local7336 state_array = (struct _StateArray *) in si_parse_power_table()7347 state_array->ucNumEntries); in si_parse_power_table()7350 power_state_offset = (u8 *)state_array->states; in si_parse_power_table()7351 for (adev->pm.dpm.num_ps = 0, i = 0; i < state_array->ucNumEntries; i++) { in si_parse_power_table()