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/linux/drivers/gpu/drm/msm/
H A Dmsm_gem_shrinker.c175 } stages[] = { in msm_gem_shrinker_scan() local
186 for (unsigned i = 0; (nr > 0) && (i < ARRAY_SIZE(stages)); i++) { in msm_gem_shrinker_scan()
187 if (!stages[i].cond) in msm_gem_shrinker_scan()
189 stages[i].freed = in msm_gem_shrinker_scan()
190 drm_gem_lru_scan(stages[i].lru, nr, in msm_gem_shrinker_scan()
191 &stages[i].remaining, in msm_gem_shrinker_scan()
192 stages[i].shrink, in msm_gem_shrinker_scan()
194 nr -= stages[i].freed; in msm_gem_shrinker_scan()
195 freed += stages[i].freed; in msm_gem_shrinker_scan()
196 remaining += stages[i].remaining; in msm_gem_shrinker_scan()
[all …]
/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_lm.c204 int op_mode, stages, stage_off, i; in dpu_hw_lm_setup_color3_v12() local
206 stages = ctx->cap->sblk->maxblendstages; in dpu_hw_lm_setup_color3_v12()
207 if (stages <= 0) in dpu_hw_lm_setup_color3_v12()
210 for (i = DPU_STAGE_0; i <= stages; i++) { in dpu_hw_lm_setup_color3_v12()
284 int i, ret, stages, stage_off, pipes_per_stage; in dpu_hw_lm_setup_blendstage() local
287 stages = ctx->cap->sblk->maxblendstages; in dpu_hw_lm_setup_blendstage()
288 if (stages <= 0) in dpu_hw_lm_setup_blendstage()
304 for (i = DPU_STAGE_0; i <= stages; i++) { in dpu_hw_lm_setup_blendstage()
322 int i, stages, stage_off; in dpu_hw_lm_clear_all_blendstages() local
324 stages = ctx->cap->sblk->maxblendstages; in dpu_hw_lm_clear_all_blendstages()
[all …]
/linux/drivers/staging/media/atomisp/pci/runtime/pipeline/src/
H A Dpipeline.c236 s = pipeline->stages; in ia_css_pipeline_clean()
272 last = pipeline->stages; in ia_css_pipeline_create_and_add_stage()
314 pipeline->stages = new_stage; in ia_css_pipeline_create_and_add_stage()
332 for (stage = pipeline->stages; stage; stage = stage->next) { in ia_css_pipeline_finalize_stages()
352 for (s = pipeline->stages; s; s = s->next) { in ia_css_pipeline_get_stage()
371 for (s = pipeline->stages; s; s = s->next) { in ia_css_pipeline_get_stage_from_fw()
391 for (s = pipeline->stages; s; s = s->next) { in ia_css_pipeline_get_fw_from_stage()
414 for (s = pipeline->stages; s; s = s->next) { in ia_css_pipeline_get_output_stage()
664 pipeline->stages = NULL; in pipeline_init_defaults()
/linux/Documentation/ABI/testing/
H A Dsysfs-bus-iio-health-afe440x6 Get measured values from the ADC for these stages. Y is the
30 stages. The values are expressed in 5-bit sign-magnitude.
H A Dsysfs-bus-platform-devices-ampere-smpro282 (RO) Contains the boot stages information in hex as format below::
288 - ``AA`` : The boot stages
308 - ``CCCCCCCC``: Boot status information defined for each boot stages
/linux/tools/testing/selftests/tc-testing/
H A DREADME78 A test case has four stages:
85 The setup and teardown stages can run zero or more commands. The setup
88 can be run next. These two stages require any commands run to return
91 The execute and verify stages each run one command. The execute stage
156 adjust-command (runs in all stages and receives the stage name)
168 The stages are identified by the following strings:
/linux/Documentation/devicetree/bindings/sound/
H A Dti,tas5086.txt28 stages connected to the PWM output pins work. Not all
29 power stages are compatible to Mid-Z - please refer
/linux/Documentation/arch/arm/sa1100/
H A Dlart.rst11 is under development, with plenty of others in different stages of
/linux/Documentation/leds/
H A Dleds-sc27xx.rst11 LED controller, it only supports 4 stages to make a single
/linux/drivers/staging/media/atomisp/pci/runtime/pipeline/interface/
H A Dia_css_pipeline.h37 struct ia_css_pipeline_stage *stages; member
/linux/Documentation/devicetree/bindings/firmware/
H A Dnvidia,tegra210-bpmp.txt4 in Tegra210 SoC. It is designed to handle the early stages of the boot
/linux/drivers/staging/media/atomisp/pci/
H A Dsh_css_sp.c1183 if (!me->stages) { in sh_css_sp_init_pipeline()
1189 first_binary = me->stages->binary; in sh_css_sp_init_pipeline()
1207 for (stage = me->stages, num = 0; stage; stage = stage->next, num++) { in sh_css_sp_init_pipeline()
1221 me->stages->sp_func == IA_CSS_PIPELINE_ISYS_COPY) in sh_css_sp_init_pipeline()
1282 for (stage = me->stages, num = 0; stage; stage = stage->next, num++) { in sh_css_sp_init_pipeline()
H A Dsh_css.c470 if (pipe->pipeline.stages) in sh_css_config_input_network_2400()
471 binary = pipe->pipeline.stages->binary; in sh_css_config_input_network_2400()
920 if (pipe->pipeline.stages) in sh_css_config_input_network_2401()
921 if (pipe->pipeline.stages->binary) in sh_css_config_input_network_2401()
922 binary = pipe->pipeline.stages->binary; in sh_css_config_input_network_2401()
1188 stage = me->pipeline.stages; in start_pipe()
3088 in_frame = me->stages->args.out_frame[0]; in create_host_video_pipeline()
3258 in_frame = me->stages->args.out_frame[0]; in create_host_preview_pipeline()
3553 for (stage = pipeline->stages; stage; stage = stage->next) { in ia_css_pipe_enqueue_buffer()
7285 for (stage = me->stages; stage; stage = stage->next) in ia_css_pipeline_uses_params()
/linux/tools/testing/selftests/resctrl/
H A DREADME59 A test case has four stages:
/linux/drivers/gpu/drm/msm/disp/mdp4/
H A Dmdp4_crtc.c148 static const enum mdp_mixer_stage_id stages[] = { in setup_mixer() enum
160 pipe_id, stages[idx]); in setup_mixer()
/linux/Documentation/fb/
H A Ddeferred_io.rst31 the final image rather than the intermediate stages which is why it's okay
/linux/tools/testing/selftests/tc-testing/creating-plugins/
H A DAddingPlugins.txt75 The stages are represented by the following strings:
/linux/arch/powerpc/platforms/ps3/
H A DKconfig106 in the repository for later boot stages.
/linux/arch/mips/
H A DKconfig.debug144 debug information from the early stages of core startup.
/linux/Documentation/core-api/real-time/
H A Dtheory.rst90 With forced threading, interrupt handling is split into two stages. The first
/linux/Documentation/arch/arm64/
H A Dtagged-address-abi.rst43 The AArch64 Tagged Address ABI has two stages of relaxation depending on
/linux/Documentation/admin-guide/media/
H A Dipu3.rst445 IPU3 pipeline has a number of image processing stages, each of which takes a
446 set of parameters as input. The major stages of pipelines are shown here:
577 A few stages of the pipeline will be executed by firmware running on the ISP
/linux/arch/m68k/q40/
H A DREADME54 went wrong during earliest setup stages of head.S.
/linux/Documentation/userspace-api/media/dvb/
H A Dfrontend-property-terrestrial-systems.rst54 DVB-T2 support is currently in the early stages of development, so
/linux/Documentation/kbuild/
H A Dkconfig-macro-language.rst13 There is clear distinction between the two language stages. For example, you

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