Home
last modified time | relevance | path

Searched refs:spx5_wr (Results 1 – 18 of 18) sorted by relevance

/linux/drivers/net/ethernet/microchip/sparx5/ !
H A Dsparx5_vlan.c18 spx5_wr(mask[0], sparx5, ANA_L3_VLAN_MASK_CFG(vid)); in sparx5_vlant_set_mask()
20 spx5_wr(mask[1], sparx5, ANA_L3_VLAN_MASK_CFG1(vid)); in sparx5_vlant_set_mask()
21 spx5_wr(mask[2], sparx5, ANA_L3_VLAN_MASK_CFG2(vid)); in sparx5_vlant_set_mask()
145 spx5_wr(0, spx5, ANA_AC_PGID_CFG(pgid)); in sparx5_pgid_clear()
147 spx5_wr(0, spx5, ANA_AC_PGID_CFG1(pgid)); in sparx5_pgid_clear()
148 spx5_wr(0, spx5, ANA_AC_PGID_CFG2(pgid)); in sparx5_pgid_clear()
177 spx5_wr(mask[0], sparx5, ANA_AC_SRC_CFG(port)); in sparx5_update_fwd()
179 spx5_wr(mask[1], sparx5, ANA_AC_SRC_CFG1(port)); in sparx5_update_fwd()
180 spx5_wr(mask[2], sparx5, ANA_AC_SRC_CFG2(port)); in sparx5_update_fwd()
183 spx5_wr(0, sparx5, ANA_AC_SRC_CFG(port)); in sparx5_update_fwd()
[all …]
H A Dsparx5_fdma.c56 spx5_wr(((u64)fdma->dma) & GENMASK(31, 0), sparx5, in sparx5_fdma_rx_activate()
58 spx5_wr(((u64)fdma->dma) >> 32, sparx5, in sparx5_fdma_rx_activate()
62 spx5_wr(FDMA_CH_CFG_CH_DCB_DB_CNT_SET(fdma->n_dbs) | in sparx5_fdma_rx_activate()
82 spx5_wr(BIT(fdma->channel_id), sparx5, FDMA_CH_ACTIVATE); in sparx5_fdma_rx_activate()
107 spx5_wr(((u64)fdma->dma) & GENMASK(31, 0), sparx5, in sparx5_fdma_tx_activate()
109 spx5_wr(((u64)fdma->dma) >> 32, sparx5, in sparx5_fdma_tx_activate()
113 spx5_wr(FDMA_CH_CFG_CH_DCB_DB_CNT_SET(fdma->n_dbs) | in sparx5_fdma_tx_activate()
123 spx5_wr(BIT(fdma->channel_id), sparx5, FDMA_CH_ACTIVATE); in sparx5_fdma_tx_activate()
136 spx5_wr(BIT(fdma->channel_id), sparx5, FDMA_CH_RELOAD); in sparx5_fdma_reload()
324 spx5_wr(0, sparx5, FDMA_INTR_DB_ENA); in sparx5_fdma_handler()
[all …]
H A Dsparx5_vcap_impl.c200 spx5_wr(VCAP_SUPER_CFG_MV_NUM_POS_SET(0) | in _sparx5_vcap_range_init()
203 spx5_wr(VCAP_SUPER_CTRL_UPDATE_CMD_SET(VCAP_CMD_INITIALIZE) | in _sparx5_vcap_range_init()
214 spx5_wr(VCAP_ES0_CFG_MV_NUM_POS_SET(0) | in _sparx5_vcap_range_init()
217 spx5_wr(VCAP_ES0_CTRL_UPDATE_CMD_SET(VCAP_CMD_INITIALIZE) | in _sparx5_vcap_range_init()
228 spx5_wr(VCAP_ES2_CFG_MV_NUM_POS_SET(0) | in _sparx5_vcap_range_init()
231 spx5_wr(VCAP_ES2_CTRL_UPDATE_CMD_SET(VCAP_CMD_INITIALIZE) | in _sparx5_vcap_range_init()
919 spx5_wr(keystr[idx] & mskstr[idx], sparx5, in sparx5_vcap_is0_cache_write()
921 spx5_wr(~mskstr[idx], sparx5, in sparx5_vcap_is0_cache_write()
927 spx5_wr(actstr[idx], sparx5, in sparx5_vcap_is0_cache_write()
939 spx5_wr(admin->cache.counter, sparx5, in sparx5_vcap_is0_cache_write()
[all …]
H A Dsparx5_psfp.c109 spx5_wr(ANA_AC_SG_ACCESS_CTRL_SGID_SET(id), sparx5, in sparx5_psfp_sg_config_change()
112 spx5_wr(ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE_SET(1) | in sparx5_psfp_sg_config_change()
147 spx5_wr(ANA_AC_SG_ACCESS_CTRL_SGID_SET(id), sparx5, in sparx5_psfp_sg_set()
151 spx5_wr(sg->basetime.tv_nsec, sparx5, ANA_AC_SG_CONFIG_REG_1); in sparx5_psfp_sg_set()
152 spx5_wr(base_lsb, sparx5, ANA_AC_SG_CONFIG_REG_2); in sparx5_psfp_sg_set()
166 spx5_wr(sg->cycletime, sparx5, ANA_AC_SG_CONFIG_REG_4); in sparx5_psfp_sg_set()
167 spx5_wr(sg->cycletimeext, sparx5, ANA_AC_SG_CONFIG_REG_5); in sparx5_psfp_sg_set()
176 spx5_wr(ANA_AC_SG_GCL_GS_CONFIG_IPS_SET(ips) | in sparx5_psfp_sg_set()
181 spx5_wr(accum_time_interval, sparx5, in sparx5_psfp_sg_set()
185 spx5_wr(gce->maxoctets, sparx5, ANA_AC_SG_GCL_OCT_CONFIG(i)); in sparx5_psfp_sg_set()
[all …]
H A Dsparx5_packet.c26 spx5_wr(QS_XTR_FLUSH_FLUSH_SET(BIT(grp)), sparx5, QS_XTR_FLUSH); in sparx5_xtr_flush()
32 spx5_wr(0, sparx5, QS_XTR_FLUSH); in sparx5_xtr_flush()
184 spx5_wr(QS_INJ_CTRL_SOF_SET(1) | in sparx5_inject()
190 spx5_wr(ifh[w], sparx5, QS_INJ_WR(grp)); in sparx5_inject()
197 spx5_wr(val, sparx5, QS_INJ_WR(grp)); in sparx5_inject()
202 spx5_wr(0, sparx5, QS_INJ_WR(grp)); in sparx5_inject()
207 spx5_wr(QS_INJ_CTRL_GAP_SIZE_SET(1) | in sparx5_inject()
213 spx5_wr(0, sparx5, QS_INJ_WR(grp)); in sparx5_inject()
324 spx5_wr(QS_XTR_GRP_CFG_MODE_SET(1) | in sparx5_manual_injection_mode()
328 spx5_wr(QS_INJ_GRP_CFG_MODE_SET(1) | in sparx5_manual_injection_mode()
[all …]
H A Dsparx5_mactable.c76 spx5_wr(mach, sparx5, LRN_MAC_ACCESS_CFG_0); in sparx5_mact_select()
77 spx5_wr(macl, sparx5, LRN_MAC_ACCESS_CFG_1); in sparx5_mact_select()
100 spx5_wr(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_SET(addr) | in sparx5_mact_learn()
105 spx5_wr(0, sparx5, LRN_MAC_ACCESS_CFG_3); in sparx5_mact_learn()
108 spx5_wr(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_SET(MAC_CMD_LEARN) | in sparx5_mact_learn()
171 spx5_wr(LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA_SET(1) | in sparx5_mact_getnext()
174 spx5_wr(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_SET in sparx5_mact_getnext()
202 spx5_wr(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_SET(MAC_CMD_LOOKUP) | in sparx5_mact_find()
230 spx5_wr(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_SET(MAC_CMD_UNLEARN) | in sparx5_mact_forget()
445 spx5_wr(LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA_SET(1), in sparx5_mact_pull_work()
[all …]
H A Dsparx5_main.c471 spx5_wr(ANA_AC_STAT_RESET_RESET_SET(1), sparx5, ANA_AC_STAT_RESET); in sparx5_init_switchcore()
472 spx5_wr(ASM_STAT_CFG_STAT_CNT_CLR_SHOT_SET(1), sparx5, ASM_STAT_CFG); in sparx5_init_switchcore()
475 spx5_wr(HSCH_RESET_CFG_CORE_ENA_SET(1), sparx5, HSCH_RESET_CFG); in sparx5_init_switchcore()
640 spx5_wr(0xFFF, sparx5, in sparx5_qlim_set()
646 spx5_wr(0xFFF, sparx5, in sparx5_qlim_set()
653 spx5_wr(qlim_wm(sparx5, 80), sparx5, XQS_QLIMIT_SHR_QLIM_CFG(0)); in sparx5_qlim_set()
654 spx5_wr(qlim_wm(sparx5, 90), sparx5, XQS_QLIMIT_SHR_CTOP_CFG(0)); in sparx5_qlim_set()
655 spx5_wr(qlim_wm(sparx5, 95), sparx5, XQS_QLIMIT_SHR_ATOP_CFG(0)); in sparx5_qlim_set()
656 spx5_wr(qlim_wm(sparx5, 100), sparx5, XQS_QLIMIT_SHR_TOP_CFG(0)); in sparx5_qlim_set()
681 spx5_wr(sparx5->ports[idx]->conf.sd_sgpio, in sparx5_board_init()
[all …]
H A Dsparx5_ptp.c429 spx5_wr((u32)tod_inc & 0xFFFFFFFF, sparx5, in sparx5_ptp_adjfine()
431 spx5_wr((u32)(tod_inc >> 32), sparx5, in sparx5_ptp_adjfine()
465 spx5_wr(PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB_SET(upper_32_bits(ts->tv_sec)), in sparx5_ptp_settime64()
467 spx5_wr(lower_32_bits(ts->tv_sec), in sparx5_ptp_settime64()
469 spx5_wr(ts->tv_nsec, sparx5, PTP_PTP_TOD_NSEC(consts->tod_pin)); in sparx5_ptp_settime64()
547 spx5_wr(PTP_PTP_TOD_NSEC_PTP_TOD_NSEC_SET(delta), in sparx5_ptp_adjtime()
626 spx5_wr(PTP_PTP_DOM_CFG_PTP_ENA_SET(0), sparx5, PTP_PTP_DOM_CFG); in sparx5_ptp_init()
634 spx5_wr((u32)tod_adj & 0xFFFFFFFF, sparx5, in sparx5_ptp_init()
636 spx5_wr((u32)(tod_adj >> 32), sparx5, in sparx5_ptp_init()
645 spx5_wr(PTP_PTP_DOM_CFG_PTP_ENA_SET(0x7), sparx5, PTP_PTP_DOM_CFG); in sparx5_ptp_init()
H A Dsparx5_sdlb.c246 spx5_wr(ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT_SET(next) | in sparx5_sdlb_group_link()
251 spx5_wr(ANA_AC_SDLB_XLB_START_LBSET_START_SET(first), sparx5, in sparx5_sdlb_group_link()
330 spx5_wr(ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL_SET(group->pup_interval), in sparx5_sdlb_group_init()
333 spx5_wr(ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS_SET(frame_size), in sparx5_sdlb_group_init()
336 spx5_wr(ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT_SET(thres_shift), sparx5, in sparx5_sdlb_group_init()
H A Dsparx5_port.c90 spx5_wr(value, sparx5, DEV2G5_PCS1G_STICKY(portno)); in sparx5_get_dev2g5_status()
586 spx5_wr(DEV2G5_MAC_TAGS_CFG_TAG_ID_SET(etype) | in sparx5_port_max_tags_set()
771 spx5_wr(DEV2G5_PCS1G_CFG_PCS_ENA_SET(1), in sparx5_port_pcs_low_set()
779 spx5_wr(DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_SET(abil) | in sparx5_port_pcs_low_set()
786 spx5_wr(0, sparx5, DEV2G5_PCS1G_ANEG_CFG(port->portno)); in sparx5_port_pcs_low_set()
908 spx5_wr(DEV2G5_MAC_IFG_CFG_TX_IFG_SET(tx_gap) | in sparx5_port_config_low_set()
921 spx5_wr(DEV2G5_MAC_ENA_CFG_RX_ENA | in sparx5_port_config_low_set()
1097 spx5_wr(QSYS_ATOP_ATOP_SET(atop), in sparx5_port_init()
1102 spx5_wr(PAUSE_DISCARD, sparx5, ANA_CL_CAPTURE_BPDU_CFG(port->portno)); in sparx5_port_init()
1124 spx5_wr(DEV2G5_PCS1G_SD_CFG_SD_POL_SET(sd_pol) | in sparx5_port_init()
[all …]
H A Dsparx5_police.c30 spx5_wr(ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS_SET(pup_tokens), sparx5, in sparx5_policer_service_conf_set()
H A Dsparx5_qos.c95 spx5_wr(HSCH_HSCH_TIMER_CFG_LEAK_TIME_SET(leak_time), sparx5, in sparx5_lg_set_leak_time()
257 spx5_wr(HSCH_SE_CONNECT_SE_LEAK_LINK_SET(idx_next), sparx5, in sparx5_lg_conf_set()
351 spx5_wr(HSCH_CIR_CFG_CIR_RATE_SET(sh->rate) | in sparx5_shaper_conf_set()
H A Dsparx5_vcap_debugfs.c282 spx5_wr(value, sparx5, ANA_ACL_SEC_LOOKUP_STICKY(lookup)); in sparx5_vcap_is2_port_stickies()
433 spx5_wr(value, sparx5, EACL_SEC_LOOKUP_STICKY(lookup)); in sparx5_vcap_es2_port_stickies()
H A Dsparx5_calendar.c213 spx5_wr(cal[idx], sparx5, QSYS_CAL_AUTO(idx)); in sparx5_config_auto_calendar()
225 spx5_wr(HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA_SET(12), in sparx5_config_auto_calendar()
H A Dsparx5_ethtool.c210 spx5_wr(XQS_STAT_CFG_STAT_VIEW_SET(portno), sparx5, XQS_STAT_CFG); in sparx5_get_queue_sys_stats()
1171 spx5_wr(XQS_STAT_CFG_STAT_VIEW_SET(portno) | in sparx5_config_port_stats()
H A Dsparx5_main.h804 static inline void spx5_wr(u32 val, struct sparx5 *sparx5, in spx5_wr() function
/linux/drivers/net/ethernet/microchip/sparx5/lan969x/ !
H A Dlan969x_rgmii.c121 spx5_wr(DEVRGMII_MAC_ENA_CFG_RX_ENA_SET(1) | in lan969x_rgmii_port_device_config()
126 spx5_wr(DEVRGMII_MAC_IFG_CFG_TX_IFG_SET(LAN969X_RGMII_IFG_TX) | in lan969x_rgmii_port_device_config()
132 spx5_wr(DEVRGMII_DEV_RST_CTRL_SPEED_SEL_SET(speed_sel), in lan969x_rgmii_port_device_config()
136 spx5_wr(DEVRGMII_MAC_TAGS_CFG_TAG_ID_SET(etype) | in lan969x_rgmii_port_device_config()
206 spx5_wr(HSIO_WRAP_XMII_CFG_GPIO_XMII_CFG_SET(1), port->sparx5, in lan969x_rgmii_gpio_config()
H A Dlan969x_fdma.c293 spx5_wr(0xff, sparx5, FDMA_INTR_DB_ENA); in lan969x_fdma_napi_poll()
386 spx5_wr(FDMA_CTRL_NRESET_SET(0), sparx5, FDMA_CTRL); in lan969x_fdma_init()
387 spx5_wr(FDMA_CTRL_NRESET_SET(1), sparx5, FDMA_CTRL); in lan969x_fdma_init()