Home
last modified time | relevance | path

Searched refs:spx5_rmw (Results 1 – 19 of 19) sorted by relevance

/linux/drivers/net/ethernet/microchip/sparx5/
H A Dsparx5_port.c364 spx5_rmw(0, in sparx5_port_disable()
370 spx5_rmw(HSCH_PORT_MODE_DEQUEUE_DIS, in sparx5_port_disable()
376 spx5_rmw(QSYS_PAUSE_CFG_PAUSE_STOP_SET(0xFFF - 1), in sparx5_port_disable()
386 spx5_rmw(HSCH_FLUSH_CTRL_FLUSH_PORT_SET(port->portno) | in sparx5_port_disable()
398 spx5_rmw(0, in sparx5_port_disable()
434 spx5_rmw(HSCH_FLUSH_CTRL_FLUSH_PORT_SET(port->portno) | in sparx5_port_disable()
453 spx5_rmw(DEV25G_PCS25G_CFG_PCS25G_ENA_SET(0), in sparx5_port_disable()
459 spx5_rmw(DEV2G5_PCS1G_CFG_PCS_ENA_SET(0), in sparx5_port_disable()
543 spx5_rmw(BIT(inst), in sparx5_port_mux_set()
550 spx5_rmw(PORT_CONF_USGMII_CFG_BYPASS_SCRAM_SET(1) | in sparx5_port_mux_set()
[all …]
H A Dsparx5_fdma.c68 spx5_rmw(FDMA_XTR_CFG_XTR_FIFO_WM_SET(31), FDMA_XTR_CFG_XTR_FIFO_WM, in sparx5_fdma_rx_activate()
73 spx5_rmw(FDMA_PORT_CTRL_XTR_STOP_SET(0), FDMA_PORT_CTRL_XTR_STOP, in sparx5_fdma_rx_activate()
77 spx5_rmw(BIT(fdma->channel_id), in sparx5_fdma_rx_activate()
90 spx5_rmw(0, BIT(fdma->channel_id) & FDMA_CH_ACTIVATE_CH_ACTIVATE, in sparx5_fdma_rx_deactivate()
94 spx5_rmw(0, BIT(fdma->channel_id) & FDMA_INTR_DB_ENA_INTR_DB_ENA, in sparx5_fdma_rx_deactivate()
98 spx5_rmw(FDMA_PORT_CTRL_XTR_STOP_SET(1), FDMA_PORT_CTRL_XTR_STOP, in sparx5_fdma_rx_deactivate()
119 spx5_rmw(FDMA_PORT_CTRL_INJ_STOP_SET(0), FDMA_PORT_CTRL_INJ_STOP, in sparx5_fdma_tx_activate()
129 spx5_rmw(0, BIT(tx->fdma.channel_id) & FDMA_CH_ACTIVATE_CH_ACTIVATE, in sparx5_fdma_tx_deactivate()
204 spx5_rmw(BIT(fdma->channel_id), in sparx5_fdma_napi_callback()
366 spx5_rmw(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_SET(1), in sparx5_fdma_injection_mode()
[all …]
H A Dsparx5_vlan.c31 spx5_rmw(ANA_L3_VLAN_CTRL_VLAN_ENA_SET(1), in sparx5_vlan_init()
38 spx5_rmw(ANA_L3_VLAN_CFG_VLAN_FID_SET(vid), in sparx5_vlan_init()
49 spx5_rmw(ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_SET(0) | in sparx5_vlan_port_setup()
129 spx5_rmw(val, mask, sparx5, ANA_AC_PGID_CFG(pgid)); in sparx5_pgid_update_mask()
133 spx5_rmw(val, mask, sparx5, ANA_AC_PGID_CFG1(pgid)); in sparx5_pgid_update_mask()
137 spx5_rmw(val, mask, sparx5, ANA_AC_PGID_CFG2(pgid)); in sparx5_pgid_update_mask()
239 spx5_rmw(REW_PORT_VLAN_CFG_PORT_VID_SET(port->vid), in sparx5_vlan_port_apply()
H A Dsparx5_ptp.c287 spx5_rmw(PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(PTP_PIN_ACTION_SAVE) | in sparx5_get_hwtimestamp()
345 spx5_rmw(REW_PTP_TWOSTEP_CTRL_PTP_NXT_SET(1), in sparx5_ptp_irq_handler()
372 spx5_rmw(REW_PTP_TWOSTEP_CTRL_PTP_NXT_SET(1), in sparx5_ptp_irq_handler()
425 spx5_rmw(PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_SET(1 << BIT(phc->index)), in sparx5_ptp_adjfine()
434 spx5_rmw(PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_SET(0), in sparx5_ptp_adjfine()
456 spx5_rmw(PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(PTP_PIN_ACTION_IDLE) | in sparx5_ptp_settime64()
472 spx5_rmw(PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(PTP_PIN_ACTION_LOAD) | in sparx5_ptp_settime64()
498 spx5_rmw(PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(PTP_PIN_ACTION_SAVE) | in sparx5_ptp_gettime64()
539 spx5_rmw(PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(PTP_PIN_ACTION_IDLE) | in sparx5_ptp_adjtime()
551 spx5_rmw(PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(PTP_PIN_ACTION_DELTA) | in sparx5_ptp_adjtime()
[all …]
H A Dsparx5_mirror.c45 return spx5_rmw(val, val, sparx5, ANA_AC_PROBE_PORT_CFG(idx)); in sparx5_mirror_port_add()
47 return spx5_rmw(val, val, sparx5, ANA_AC_PROBE_PORT_CFG1(idx)); in sparx5_mirror_port_add()
59 return spx5_rmw(0, val, sparx5, ANA_AC_PROBE_PORT_CFG(idx)); in sparx5_mirror_port_del()
61 return spx5_rmw(0, val, sparx5, ANA_AC_PROBE_PORT_CFG1(idx)); in sparx5_mirror_port_del()
87 spx5_rmw(ANA_AC_PROBE_CFG_PROBE_DIRECTION_SET(dir), in sparx5_mirror_dir_set()
96 spx5_rmw(QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL_SET(portno), in sparx5_mirror_monitor_set()
H A Dsparx5_calendar.c207 spx5_rmw(QSYS_CAL_CTRL_CAL_MODE_SET(10), in sparx5_config_auto_calendar()
218 spx5_rmw(QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE_SET(671), /* 672->671 */ in sparx5_config_auto_calendar()
230 spx5_rmw(QSYS_CAL_CTRL_CAL_MODE_SET(8), in sparx5_config_auto_calendar()
540 spx5_rmw(DSM_TAXI_CAL_CFG_CAL_PGM_SEL_SET(!act), in sparx5_dsm_calendar_update()
545 spx5_rmw(DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(1), in sparx5_dsm_calendar_update()
550 spx5_rmw(DSM_TAXI_CAL_CFG_CAL_IDX_SET(idx), in sparx5_dsm_calendar_update()
554 spx5_rmw(DSM_TAXI_CAL_CFG_CAL_PGM_VAL_SET(data->schedule[idx]), in sparx5_dsm_calendar_update()
559 spx5_rmw(DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(0), in sparx5_dsm_calendar_update()
569 spx5_rmw(DSM_TAXI_CAL_CFG_CAL_SWITCH_SET(1), in sparx5_dsm_calendar_update()
H A Dsparx5_main.c452 spx5_rmw(EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(1), in sparx5_init_switchcore()
457 spx5_rmw(EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(0), in sparx5_init_switchcore()
565 spx5_rmw(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_SET(clk_div) | in sparx5_init_coreclock()
587 spx5_rmw(HSCH_SYS_CLK_PER_100PS_SET(clk_period / 100), in sparx5_init_coreclock()
592 spx5_rmw(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_SET(clk_period / 100), in sparx5_init_coreclock()
597 spx5_rmw(ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_SET(clk_period / 100), in sparx5_init_coreclock()
602 spx5_rmw(LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_SET(clk_period / 100), in sparx5_init_coreclock()
608 spx5_rmw(GCB_SIO_CLOCK_SYS_CLK_PERIOD_SET(clk_period / 100), in sparx5_init_coreclock()
613 spx5_rmw(HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_SET in sparx5_init_coreclock()
619 spx5_rmw(ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_SET(pol_upd_int), in sparx5_init_coreclock()
[all …]
H A Dsparx5_qos.c253 spx5_rmw(HSCH_HSCH_CFG_CFG_HSCH_LAYER_SET(layer), in sparx5_lg_conf_set()
261 spx5_rmw(HSCH_HSCH_LEAK_CFG_LEAK_FIRST_SET(se_first), in sparx5_lg_conf_set()
343 spx5_rmw(HSCH_HSCH_CFG_CFG_HSCH_LAYER_SET(layer), in sparx5_shaper_conf_set()
347 spx5_rmw(HSCH_SE_CFG_SE_FRM_MODE_SET(sh->mode), HSCH_SE_CFG_SE_FRM_MODE, in sparx5_shaper_conf_set()
373 spx5_rmw(HSCH_HSCH_CFG_CFG_HSCH_LAYER_SET(layer) | in sparx5_dwrr_conf_set()
379 spx5_rmw(HSCH_SE_CFG_SE_DWRR_CNT_SET(dwrr->count), in sparx5_dwrr_conf_set()
384 spx5_rmw(HSCH_DWRR_ENTRY_DWRR_COST_SET(dwrr->cost[i]), in sparx5_dwrr_conf_set()
H A Dsparx5_psfp.c79 spx5_rmw(ANA_L2_TSN_CFG_TSN_SFID_SET(sfid), ANA_L2_TSN_CFG_TSN_SFID, in sparx5_isdx_conf_set()
82 spx5_rmw(ANA_L2_DLB_CFG_DLB_IDX_SET(fmid), ANA_L2_DLB_CFG_DLB_IDX, in sparx5_isdx_conf_set()
125 spx5_rmw(ANA_AC_TSN_SF_CFG_TSN_SGID_SET(sf->sgid) | in sparx5_psfp_sf_set()
154 spx5_rmw(ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB_SET(base_msb) | in sparx5_psfp_sg_set()
335 spx5_rmw(ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA_SET(1), in sparx5_psfp_init()
H A Dsparx5_vcap_impl.c1530 spx5_rmw(ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL_SET(value), in sparx5_vcap_is0_set_port_keyset()
1537 spx5_rmw(ANA_CL_ADV_CL_CFG_IP6_CLM_KEY_SEL_SET(value), in sparx5_vcap_is0_set_port_keyset()
1544 spx5_rmw(ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL_SET(value), in sparx5_vcap_is0_set_port_keyset()
1619 spx5_rmw(ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL_SET(value), in sparx5_vcap_is2_set_port_keyset()
1626 spx5_rmw(ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL_SET(value), in sparx5_vcap_is2_set_port_keyset()
1630 spx5_rmw(ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL_SET(value), in sparx5_vcap_is2_set_port_keyset()
1637 spx5_rmw(ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL_SET(value), in sparx5_vcap_is2_set_port_keyset()
1642 spx5_rmw(ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL_SET(value), in sparx5_vcap_is2_set_port_keyset()
1649 spx5_rmw(ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL_SET(value), in sparx5_vcap_is2_set_port_keyset()
1712 spx5_rmw(EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL_SET(value), in sparx5_vcap_es2_set_port_keyset()
[all …]
H A Dsparx5_police.c33 spx5_rmw(ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX_SET(max_pup_tokens), in sparx5_policer_service_conf_set()
37 spx5_rmw(ANA_AC_SDLB_THRES_THRES_SET(thres), ANA_AC_SDLB_THRES_THRES, in sparx5_policer_service_conf_set()
H A Dsparx5_packet.c309 spx5_rmw(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_SET(1), in sparx5_injection_timeout()
343 spx5_rmw(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_SET(1), in sparx5_manual_injection_mode()
349 spx5_rmw(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_SET(0), in sparx5_manual_injection_mode()
356 spx5_rmw(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS_SET(0), in sparx5_manual_injection_mode()
H A Dsparx5_sdlb.c62 spx5_rmw(ANA_AC_SDLB_PUP_CTRL_PUP_ENA_SET(0), in sparx5_sdlb_group_disable()
69 spx5_rmw(ANA_AC_SDLB_PUP_CTRL_PUP_ENA_SET(1), in sparx5_sdlb_group_enable()
H A Dsparx5_mactable.c484 spx5_rmw(LRN_AUTOAGE_CFG_UNIT_SIZE_SET(2) | /* 10 ms */ in sparx5_set_ageing()
H A Dsparx5_ethtool.c1162 spx5_rmw(ANA_AC_PORT_SGE_CFG_MASK_SET(0xf0f0), in sparx5_config_stats()
1176 spx5_rmw(ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE_SET(1) | in sparx5_config_port_stats()
H A Dsparx5_switchdev.c533 spx5_rmw(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(enable), in sparx5_cpu_copy_ena()
H A Dsparx5_main.h824 static inline void spx5_rmw(u32 val, u32 mask, struct sparx5 *sparx5, in spx5_rmw() function
/linux/drivers/net/ethernet/microchip/sparx5/lan969x/
H A Dlan969x_rgmii.c95 spx5_rmw(HSIO_WRAP_RGMII_CFG_TX_CLK_CFG_SET(clk_sel) | in lan969x_rgmii_tx_clk_config()
176 spx5_rmw(HSIO_WRAP_DLL_CFG_DLL_RST_SET(0) | in lan969x_rgmii_delay_config()
187 spx5_rmw(HSIO_WRAP_DLL_CFG_DLL_RST_SET(0) | in lan969x_rgmii_delay_config()
H A Dlan969x.c199 spx5_rmw(BIT(inst), BIT(inst), sparx5, PORT_CONF_QSGMII_ENA); in lan969x_port_mux_set()
245 spx5_rmw(PTP_TWOSTEP_CTRL_PTP_NXT_SET(1), in lan969x_ptp_irq_handler()
272 spx5_rmw(PTP_TWOSTEP_CTRL_PTP_NXT_SET(1), in lan969x_ptp_irq_handler()