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Searched refs:soc_data (Results 1 – 25 of 73) sorted by relevance

123

/linux/drivers/devfreq/
H A Dmtk-cci-devfreq.c35 const struct mtk_ccifreq_platform_data *soc_data; member
41 const struct mtk_ccifreq_platform_data *soc_data = drv->soc_data; in mtk_ccifreq_set_voltage() local
48 drv->soc_data->proc_max_volt); in mtk_ccifreq_set_voltage()
64 new_vsram = clamp(new_voltage + soc_data->min_volt_shift, in mtk_ccifreq_set_voltage()
65 soc_data->sram_min_volt, soc_data->sram_max_volt); in mtk_ccifreq_set_voltage()
69 vsram = clamp(pre_voltage + soc_data->max_volt_shift, in mtk_ccifreq_set_voltage()
70 soc_data->sram_min_volt, new_vsram); in mtk_ccifreq_set_voltage()
72 soc_data->sram_max_volt); in mtk_ccifreq_set_voltage()
76 if (vsram == soc_data->sram_max_volt || in mtk_ccifreq_set_voltage()
77 new_vsram == soc_data->sram_min_volt) in mtk_ccifreq_set_voltage()
[all …]
/linux/drivers/phy/ti/
H A Dphy-gmii-sel.c61 const struct phy_gmii_sel_soc_data *soc_data; member
74 const struct phy_gmii_sel_soc_data *soc_data = if_phy->priv->soc_data; in phy_gmii_sel_mode() local
105 if (!(soc_data->extra_modes & BIT(PHY_INTERFACE_MODE_QSGMII))) in phy_gmii_sel_mode()
114 if (!(soc_data->extra_modes & BIT(PHY_INTERFACE_MODE_SGMII))) in phy_gmii_sel_mode()
121 if (!(soc_data->extra_modes & BIT(PHY_INTERFACE_MODE_USXGMII))) in phy_gmii_sel_mode()
132 if (soc_data->features & BIT(PHY_GMII_SEL_FIXED_TX_DELAY) && in phy_gmii_sel_mode()
149 if (soc_data->features & BIT(PHY_GMII_SEL_RGMII_ID_MODE) && in phy_gmii_sel_mode()
157 if (soc_data->features & BIT(PHY_GMII_SEL_RMII_IO_CLK_EN) && in phy_gmii_sel_mode()
341 if (priv->soc_data->features & BIT(PHY_GMII_SEL_RMII_IO_CLK_EN) && in phy_gmii_sel_of_xlate()
350 if (priv->soc_data->features & BIT(PHY_GMII_SEL_RMII_IO_CLK_EN)) in phy_gmii_sel_of_xlate()
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/linux/drivers/cpufreq/
H A Dmediatek-cpufreq.c57 const struct mtk_cpufreq_platform_data *soc_data; member
81 const struct mtk_cpufreq_platform_data *soc_data = info->soc_data; in mtk_cpufreq_voltage_tracking() local
100 new_vsram = clamp(new_vproc + soc_data->min_volt_shift, in mtk_cpufreq_voltage_tracking()
101 soc_data->sram_min_volt, soc_data->sram_max_volt); in mtk_cpufreq_voltage_tracking()
105 vsram = clamp(pre_vproc + soc_data->max_volt_shift, in mtk_cpufreq_voltage_tracking()
106 soc_data->sram_min_volt, new_vsram); in mtk_cpufreq_voltage_tracking()
108 soc_data->sram_max_volt); in mtk_cpufreq_voltage_tracking()
113 if (vsram == soc_data->sram_max_volt || in mtk_cpufreq_voltage_tracking()
114 new_vsram == soc_data->sram_min_volt) in mtk_cpufreq_voltage_tracking()
117 vproc = vsram - soc_data->min_volt_shift; in mtk_cpufreq_voltage_tracking()
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H A Dqcom-cpufreq-hw.c66 const struct qcom_cpufreq_soc_data *soc_data; member
117 const struct qcom_cpufreq_soc_data *soc_data = qcom_cpufreq.soc_data; in qcom_cpufreq_hw_target_index() local
121 writel_relaxed(index, data->base + soc_data->reg_perf_state); in qcom_cpufreq_hw_target_index()
125 writel_relaxed(index, data->base + soc_data->reg_perf_state + i * 4); in qcom_cpufreq_hw_target_index()
137 if (qcom_cpufreq.soc_data->reg_current_vote) in qcom_lmh_get_throttle_freq()
138 lval = readl_relaxed(data->base + qcom_cpufreq.soc_data->reg_current_vote) & 0x3ff; in qcom_lmh_get_throttle_freq()
140 lval = readl_relaxed(data->base + qcom_cpufreq.soc_data->reg_domain_state) & 0xff; in qcom_lmh_get_throttle_freq()
149 const struct qcom_cpufreq_soc_data *soc_data; in qcom_cpufreq_get_freq() local
156 soc_data = qcom_cpufreq.soc_data; in qcom_cpufreq_get_freq()
158 index = readl_relaxed(data->base + soc_data->reg_perf_state); in qcom_cpufreq_get_freq()
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H A Dti-cpufreq.c113 const struct ti_cpufreq_soc_data *soc_data; member
120 efuse = opp_data->soc_data->efuse_fallback; in amx3_efuse_xlate()
391 ret = regmap_read(opp_data->syscon, opp_data->soc_data->efuse_offset, in ti_cpufreq_get_efuse()
394 if (opp_data->soc_data->quirks & TI_QUIRK_SYSCON_IS_SINGLE_REG && ret == -EIO) in ti_cpufreq_get_efuse()
397 if (opp_data->soc_data->quirks & TI_QUIRK_SYSCON_MAY_BE_MISSING && ret == -EIO) { in ti_cpufreq_get_efuse()
400 opp_data->soc_data->efuse_offset, 4); in ti_cpufreq_get_efuse()
414 efuse = (efuse & opp_data->soc_data->efuse_mask); in ti_cpufreq_get_efuse()
415 efuse >>= opp_data->soc_data->efuse_shift; in ti_cpufreq_get_efuse()
417 *efuse_value = opp_data->soc_data->efuse_xlate(opp_data, efuse); in ti_cpufreq_get_efuse()
446 ret = regmap_read(opp_data->syscon, opp_data->soc_data->rev_offset, in ti_cpufreq_get_rev()
[all …]
/linux/drivers/net/ethernet/arc/
H A Demac_rockchip.c30 const struct emac_rockchip_soc_data *soc_data; member
39 u32 speed_offset = emac->soc_data->grf_speed_offset; in emac_rockchip_set_mac_speed()
55 err = regmap_write(emac->grf, emac->soc_data->grf_offset, data); in emac_rockchip_set_mac_speed()
137 priv->soc_data = match->data; in emac_rockchip_probe()
181 data = (1 << (priv->soc_data->grf_speed_offset + 16)) | in emac_rockchip_probe()
182 (1 << priv->soc_data->grf_speed_offset); in emac_rockchip_probe()
184 data |= (1 << (priv->soc_data->grf_mode_offset + 16)) | in emac_rockchip_probe()
185 (0 << priv->soc_data->grf_mode_offset); in emac_rockchip_probe()
187 err = regmap_write(priv->grf, priv->soc_data->grf_offset, data); in emac_rockchip_probe()
202 if (priv->soc_data->need_div_macclk) { in emac_rockchip_probe()
[all …]
/linux/sound/soc/tegra/
H A Dtegra210_i2s.c56 regmap_write(i2s->regmap, TEGRA210_I2S_SLOT_CTRL + i2s->soc_data->i2s_ctrl_offset, in tegra210_i2s_set_slot_ctrl()
58 regmap_write(i2s->regmap, TEGRA210_I2S_TX_SLOT_CTRL + i2s->soc_data->tx_offset, in tegra210_i2s_set_slot_ctrl()
70 regmap_read(i2s->regmap, TEGRA210_I2S_CTRL + i2s->soc_data->i2s_ctrl_offset, &val); in tegra210_i2s_set_clock_rate()
117 reset_reg = TEGRA210_I2S_TX_SOFT_RESET + i2s->soc_data->tx_offset; in tegra210_i2s_sw_reset()
118 cif_reg = TEGRA210_I2S_TX_CIF_CTRL + i2s->soc_data->tx_offset; in tegra210_i2s_sw_reset()
119 stream_reg = TEGRA210_I2S_TX_CTRL + i2s->soc_data->tx_offset; in tegra210_i2s_sw_reset()
125 regmap_read(i2s->regmap, TEGRA210_I2S_CTRL + i2s->soc_data->i2s_ctrl_offset, &i2s_ctrl); in tegra210_i2s_sw_reset()
142 regmap_write(i2s->regmap, TEGRA210_I2S_CTRL + i2s->soc_data->i2s_ctrl_offset, i2s_ctrl); in tegra210_i2s_sw_reset()
160 } else if (w->reg == (TEGRA210_I2S_TX_ENABLE + i2s->soc_data->tx_offset)) { in tegra210_i2s_init()
162 status_reg = TEGRA210_I2S_TX_STATUS + i2s->soc_data in tegra210_i2s_init()
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H A Dtegra210_adx.c53 adx->soc_data->cya_offset, in tegra210_adx_write_map_ram()
58 for (i = 0; i < adx->soc_data->ram_depth; i++) in tegra210_adx_write_map_ram()
60 adx->soc_data->cya_offset, in tegra210_adx_write_map_ram()
63 for (i = 0; i < adx->soc_data->byte_mask_size; i++) in tegra210_adx_write_map_ram()
137 if (channels < 1 || channels > adx->soc_data->max_ch) in tegra210_adx_set_audio_cif()
160 if (adx->soc_data->max_ch == 32) in tegra210_adx_set_audio_cif()
497 if (adx->soc_data->num_controls) { in tegra210_adx_component_probe()
498 err = snd_soc_add_component_controls(component, adx->soc_data->controls, in tegra210_adx_component_probe()
499 adx->soc_data->num_controls); in tegra210_adx_component_probe()
676 struct tegra210_adx_soc_data *soc_data; in tegra210_adx_platform_probe()
674 struct tegra210_adx_soc_data *soc_data; tegra210_adx_platform_probe() local
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H A Dtegra210_admaif.c24 #define CH_TX_REG(reg, id) CH_REG(admaif->soc_data->tx_base, reg, id)
26 #define CH_RX_REG(reg, id) CH_REG(admaif->soc_data->rx_base, reg, id)
122 unsigned int num_ch = admaif->soc_data->num_ch; in tegra_admaif_wr_reg()
123 unsigned int rx_base = admaif->soc_data->rx_base; in tegra_admaif_wr_reg()
124 unsigned int tx_base = admaif->soc_data->tx_base; in tegra_admaif_wr_reg()
125 unsigned int global_base = admaif->soc_data->global_base; in tegra_admaif_wr_reg()
126 unsigned int reg_max = admaif->soc_data->regmap_conf->max_register; in tegra_admaif_wr_reg()
156 unsigned int num_ch = admaif->soc_data->num_ch; in tegra_admaif_rd_reg()
157 unsigned int rx_base = admaif->soc_data->rx_base; in tegra_admaif_rd_reg()
158 unsigned int tx_base = admaif->soc_data in tegra_admaif_rd_reg()
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H A Dtegra210_amx.c65 regmap_write(amx->regmap, TEGRA210_AMX_CFG_RAM_CTRL + amx->soc_data->reg_offset, in tegra210_amx_write_map_ram()
70 for (i = 0; i < amx->soc_data->ram_depth; i++) in tegra210_amx_write_map_ram()
71 regmap_write(amx->regmap, TEGRA210_AMX_CFG_RAM_DATA + amx->soc_data->reg_offset, in tegra210_amx_write_map_ram()
74 for (i = 0; i < amx->soc_data->byte_mask_size; i++) in tegra210_amx_write_map_ram()
174 if (amx->soc_data->max_ch == TEGRA264_AMX_MAX_CHANNEL) in tegra210_amx_set_audio_cif()
188 if (amx->soc_data->auto_disable) { in tegra210_amx_in_hw_params()
191 amx->soc_data->reg_offset), in tegra210_amx_in_hw_params()
193 regmap_write(amx->regmap, TEGRA210_AMX_CYA + amx->soc_data->reg_offset, 1); in tegra210_amx_in_hw_params()
508 if (amx->soc_data->num_controls) { in tegra210_amx_component_probe()
509 err = snd_soc_add_component_controls(component, amx->soc_data in tegra210_amx_component_probe()
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/linux/drivers/soc/renesas/
H A Drz-sysc.c33 const struct rz_sysc_soc_id_init_data *soc_data = sysc_data->soc_id_init_data; in rz_sysc_soc_init() local
52 soc_dev_attr->family = devm_kstrdup(sysc->dev, soc_data->family, GFP_KERNEL); in rz_sysc_soc_init()
60 val = readl(sysc->base + soc_data->devid_offset); in rz_sysc_soc_init()
61 revision = field_get(soc_data->revision_mask, val); in rz_sysc_soc_init()
62 specific_id = field_get(soc_data->specific_id_mask, val); in rz_sysc_soc_init()
67 if (soc_data->id && specific_id != soc_data->id) { in rz_sysc_soc_init()
73 if (soc_data->print_id) { in rz_sysc_soc_init()
74 soc_data->print_id(sysc->dev, sysc->base, soc_dev_attr); in rz_sysc_soc_init()
/linux/drivers/mmc/host/
H A Dsdhci-tegra.c162 const struct sdhci_tegra_soc_data *soc_data; member
192 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; in tegra_sdhci_readw() local
194 if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) && in tegra_sdhci_readw()
228 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; in tegra_sdhci_writel() local
239 if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) && in tegra_sdhci_writel()
316 if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL)) in tegra_sdhci_is_pad_and_regulator_valid()
339 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; in tegra_sdhci_set_tap() local
349 if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP) in tegra_sdhci_set_tap()
357 if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP && in tegra_sdhci_set_tap()
369 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; in tegra_sdhci_reset() local
[all …]
H A Dsdhci-of-at91.c45 const struct sdhci_at91_soc_data *soc_data; member
182 if (priv->soc_data->baseclk_is_generated_internally) in sdhci_at91_set_clks_presets()
183 clk_base_rate = gck_rate / priv->soc_data->divider_for_baseclk; in sdhci_at91_set_clks_presets()
310 const struct sdhci_at91_soc_data *soc_data; in sdhci_at91_probe() local
316 soc_data = of_device_get_match_data(&pdev->dev); in sdhci_at91_probe()
317 if (!soc_data) in sdhci_at91_probe()
320 host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*priv)); in sdhci_at91_probe()
326 priv->soc_data = soc_data; in sdhci_at91_probe()
330 if (soc_data->baseclk_is_generated_internally) in sdhci_at91_probe()
/linux/drivers/nvmem/
H A Dqfprom.c80 const struct qfprom_soc_data *soc_data; member
188 int qfprom_blow_uV = priv->soc_data->qfprom_blow_uV; in qfprom_enable_fuse_blowing()
197 ret = clk_set_rate(priv->secclk, priv->soc_data->qfprom_blow_set_freq); in qfprom_enable_fuse_blowing()
229 writel(priv->soc_data->qfprom_blow_timer_value, in qfprom_enable_fuse_blowing()
231 writel(priv->soc_data->accel_value, in qfprom_enable_fuse_blowing()
383 const struct qfprom_soc_compatible_data *soc_data; in qfprom_probe() local
401 soc_data = device_get_match_data(dev); in qfprom_probe()
402 if (soc_data) { in qfprom_probe()
403 econfig.keepout = soc_data->keepout; in qfprom_probe()
404 econfig.nkeepout = soc_data->nkeepout; in qfprom_probe()
[all …]
/linux/arch/arm/mach-imx/
H A Dpm-imx5.c324 static int __init imx5_suspend_init(const struct imx5_pm_data *soc_data) in imx5_suspend_init() argument
329 void (*suspend_asm)(void __iomem *) = soc_data->suspend_asm; in imx5_suspend_init()
334 if (!soc_data->suspend_asm_sz || !*soc_data->suspend_asm_sz) in imx5_suspend_init()
338 *soc_data->suspend_asm_sz + sizeof(*suspend_info), in imx5_suspend_init()
345 suspend_info->io_count = soc_data->suspend_io_count; in imx5_suspend_init()
346 memcpy(suspend_info->io_state, soc_data->suspend_io_config, in imx5_suspend_init()
347 sizeof(*suspend_info->io_state) * soc_data->suspend_io_count); in imx5_suspend_init()
349 suspend_info->m4if_base = ioremap(soc_data->m4if_addr, SZ_16K); in imx5_suspend_init()
355 suspend_info->iomuxc_base = ioremap(soc_data->iomuxc_addr, SZ_16K); in imx5_suspend_init()
364 *soc_data->suspend_asm_sz); in imx5_suspend_init()
/linux/drivers/reset/
H A Dreset-intel-gw.c32 const struct intel_reset_soc *soc_data; member
56 if (data->soc_data->legacy) in id_to_reg_and_bit_offsets()
61 if (data->soc_data->legacy && *rst_req == RCU_RST_REQ) in id_to_reg_and_bit_offsets()
146 if (data->soc_data->legacy) { in intel_reset_xlate()
180 data->soc_data = of_device_get_match_data(dev); in intel_reset_probe()
181 if (!data->soc_data) in intel_reset_probe()
196 data->soc_data->reset_cell_count); in intel_reset_probe()
207 data->rcdev.of_reset_n_cells = data->soc_data->reset_cell_count; in intel_reset_probe()
215 if (data->soc_data->legacy) in intel_reset_probe()
/linux/sound/soc/fsl/
H A Dfsl_sai.c90 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_isr()
224 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_set_dai_sysclk_tr()
309 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_set_dai_fmt_tr()
448 unsigned int reg, ofs = sai->soc_data->reg_offset; in fsl_sai_set_bclk()
465 id = sai->soc_data->mclk0_is_mclk1 ? 1 : 0; in fsl_sai_set_bclk()
559 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_hw_params()
703 watermark = tx ? (sai->soc_data->fifo_depth - dma_params->maxburst) : in fsl_sai_hw_params()
706 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), in fsl_sai_hw_params()
711 for (i = 0; i < sai->soc_data->pins; i++) { in fsl_sai_hw_params()
730 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output && in fsl_sai_hw_params()
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H A Dfsl_xcvr.c38 const struct fsl_xcvr_soc_data *soc_data; member
338 if (!xcvr->soc_data->use_phy) in fsl_xcvr_en_phy_pll()
361 switch (xcvr->soc_data->pll_ver) { in fsl_xcvr_en_phy_pll()
415 dev_err(dev, "Error for PLL version %d\n", xcvr->soc_data->pll_ver); in fsl_xcvr_en_phy_pll()
450 freq = xcvr->soc_data->spdif_only ? freq / 5 : freq; in fsl_xcvr_en_aud_pll()
465 if (!xcvr->soc_data->use_phy) in fsl_xcvr_en_aud_pll()
508 if (xcvr->soc_data->spdif_only && tx) { in fsl_xcvr_prepare()
637 if (xcvr->soc_data->use_edma) in fsl_xcvr_startup()
646 if (xcvr->soc_data->spdif_only && tx) in fsl_xcvr_startup()
663 if (!xcvr->soc_data->spdif_only) { in fsl_xcvr_startup()
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/linux/drivers/iio/adc/
H A Dingenic-adc.c110 const struct ingenic_adc_soc_data *soc_data; member
251 if (!adc->soc_data->battery_vref_mode) in ingenic_adc_write_raw()
618 *length = adc->soc_data->battery_raw_avail_size; in ingenic_adc_read_avail()
619 *vals = adc->soc_data->battery_raw_avail; in ingenic_adc_read_avail()
623 *length = adc->soc_data->battery_scale_avail_size; in ingenic_adc_read_avail()
624 *vals = adc->soc_data->battery_scale_avail; in ingenic_adc_read_avail()
647 if (adc->soc_data->has_aux_md && engine == 0) { in ingenic_adc_read_chan_info_raw()
710 *val = adc->soc_data->battery_high_vref; in ingenic_adc_read_raw()
711 *val2 = adc->soc_data->battery_high_vref_bits; in ingenic_adc_read_raw()
825 const struct ingenic_adc_soc_data *soc_data; in ingenic_adc_probe() local
[all …]
/linux/drivers/dma/
H A Ddma-jz4780.c154 const struct jz4780_dma_soc_data *soc_data; member
210 if (jzdma->soc_data->flags & JZ_SOC_DATA_PER_CHAN_PM) { in jz4780_dma_chan_enable()
213 if (jzdma->soc_data->flags & JZ_SOC_DATA_NO_DCKES_DCKEC) in jz4780_dma_chan_enable()
225 if ((jzdma->soc_data->flags & JZ_SOC_DATA_PER_CHAN_PM) && in jz4780_dma_chan_disable()
226 !(jzdma->soc_data->flags & JZ_SOC_DATA_NO_DCKES_DCKEC)) in jz4780_dma_chan_disable()
286 else if (ord > jzdma->soc_data->transfer_ord_max) in jz4780_dma_transfer_size()
287 ord = jzdma->soc_data->transfer_ord_max; in jz4780_dma_transfer_size()
389 !(jzdma->soc_data->flags & JZ_SOC_DATA_BREAK_LINKS)) { in jz4780_dma_prep_slave_sg()
679 const unsigned int soc_flags = jzdma->soc_data->flags; in jz4780_dma_chan_irq()
736 unsigned int nb_channels = jzdma->soc_data->nb_channels; in jz4780_dma_irq_handler()
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/linux/drivers/thermal/
H A Dimx_thermal.c222 const struct thermal_soc_data *soc_data = data->socdata; in imx_set_panic_temp() local
228 regmap_write(map, soc_data->panic_alarm_ctrl + REG_CLR, in imx_set_panic_temp()
229 soc_data->panic_alarm_mask); in imx_set_panic_temp()
230 regmap_write(map, soc_data->panic_alarm_ctrl + REG_SET, in imx_set_panic_temp()
231 critical_value << soc_data->panic_alarm_shift); in imx_set_panic_temp()
238 const struct thermal_soc_data *soc_data = data->socdata; in imx_set_alarm_temp() local
248 regmap_write(map, soc_data->high_alarm_ctrl + REG_CLR, in imx_set_alarm_temp()
249 soc_data->high_alarm_mask); in imx_set_alarm_temp()
250 regmap_write(map, soc_data->high_alarm_ctrl + REG_SET, in imx_set_alarm_temp()
251 alarm_value << soc_data->high_alarm_shift); in imx_set_alarm_temp()
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/linux/drivers/clk/imx/
H A Dclk-imx8-acm.c74 const struct imx8_acm_soc_data *soc_data; member
352 priv->soc_data = of_device_get_match_data(dev); in imx8_acm_clk_probe()
370 sels = priv->soc_data->sels; in imx8_acm_clk_probe()
371 for (i = 0; i < priv->soc_data->num_sels; i++) { in imx8_acm_clk_probe()
390 priv->soc_data->mclk_sels[ACM_AUD_CLK0_SEL_INDEX].hw = in imx8_acm_clk_probe()
393 priv->soc_data->mclk_sels[ACM_AUD_CLK1_SEL_INDEX].hw = in imx8_acm_clk_probe()
455 sels = priv->soc_data->sels; in imx8_acm_runtime_suspend()
457 for (i = 0; i < priv->soc_data->num_sels; i++) in imx8_acm_runtime_suspend()
469 sels = priv->soc_data->sels; in imx8_acm_runtime_resume()
471 for (i = 0; i < priv->soc_data->num_sels; i++) in imx8_acm_runtime_resume()
/linux/drivers/char/hw_random/
H A Drockchip-rng.c129 const struct rk_rng_soc_data *soc_data; member
396 rk_rng->soc_data = of_device_get_match_data(dev); in rk_rng_probe()
406 if (rk_rng->soc_data->reset_optional) in rk_rng_probe()
424 rk_rng->rng.init = rk_rng->soc_data->rk_rng_init; in rk_rng_probe()
425 rk_rng->rng.cleanup = rk_rng->soc_data->rk_rng_cleanup; in rk_rng_probe()
427 rk_rng->rng.read = rk_rng->soc_data->rk_rng_read; in rk_rng_probe()
429 rk_rng->rng.quality = rk_rng->soc_data->quality; in rk_rng_probe()
448 rk_rng->soc_data->rk_rng_cleanup(&rk_rng->rng); in rk_rng_runtime_suspend()
457 return rk_rng->soc_data->rk_rng_init(&rk_rng->rng); in rk_rng_runtime_resume()
/linux/drivers/soc/fsl/
H A Dguts.c186 const struct fsl_soc_data *soc_data; in fsl_guts_init() local
199 soc_data = match->data; in fsl_guts_init()
247 if (soc_data) in fsl_guts_init()
248 soc_uid = fsl_guts_get_soc_uid(soc_data->sfp_compat, in fsl_guts_init()
249 soc_data->uid_offset); in fsl_guts_init()
/linux/drivers/pinctrl/nxp/
H A Dpinctrl-s32cc.c114 unsigned int mem_regions = ipctl->info->soc_data->mem_regions; in s32_get_region()
708 for (i = 0; i < info->soc_data->npins; i++) { in s32_pinctrl_suspend()
709 pin = &info->soc_data->pins[i]; in s32_pinctrl_suspend()
733 for (i = 0; i < info->soc_data->npins; i++) { in s32_pinctrl_resume()
734 pin = &info->soc_data->pins[i]; in s32_pinctrl_resume()
847 unsigned int mem_regions = info->soc_data->mem_regions; in s32_pinctrl_probe_dt()
885 ipctl->regions[i].pin_range = &info->soc_data->mem_pin_ranges[i]; in s32_pinctrl_probe_dt()
920 const struct s32_pinctrl_soc_data *soc_data) in s32_pinctrl_probe() argument
930 if (!soc_data || !soc_data->pins || !soc_data->npins) { in s32_pinctrl_probe()
939 info->soc_data = soc_data; in s32_pinctrl_probe()
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