| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| H A D | dcn30_clk_mgr_smu_msg.c | 46 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); } macro
116 smu_print("SMU Test message: %d\n", input); in dcn30_smu_test_message()
128 smu_print("SMU Get SMU version\n"); in dcn30_smu_get_smu_version()
133 smu_print("SMU version: %d\n", *version); in dcn30_smu_get_smu_version()
146 smu_print("SMU Check driver if version\n"); in dcn30_smu_check_driver_if_version()
151 smu_print("SMU driver if version: %d\n", response); in dcn30_smu_check_driver_if_version()
165 smu_print("SMU Check msg header version\n"); in dcn30_smu_check_msg_header_version()
170 smu_print("SMU msg header version: %d\n", response); in dcn30_smu_check_msg_header_version()
181 smu_print("SMU Set DRAM addr high: %d\n", addr_high); in dcn30_smu_set_dram_addr_high()
189 smu_print("SMU Set DRAM addr low: %d\n", addr_low); in dcn30_smu_set_dram_addr_low()
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| H A D | dcn30m_clk_mgr_smu_msg.c | 45 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); } macro
112 smu_print("SMU Set SmartMux Switch: switch_dgpu = %d\n", pins_to_set); in dcn30m_smu_set_smart_mux_switch()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/ |
| H A D | dcn401_clk_mgr_smu_msg.c | 22 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); } macro
148 smu_print("SMU Get SMU version\n"); in dcn401_smu_get_smu_version()
153 smu_print("SMU version: %d\n", *version); in dcn401_smu_get_smu_version()
166 smu_print("SMU Check driver if version\n"); in dcn401_smu_check_driver_if_version()
171 smu_print("SMU driver if version: %d\n", response); in dcn401_smu_check_driver_if_version()
185 smu_print("SMU Check msg header version\n"); in dcn401_smu_check_msg_header_version()
190 smu_print("SMU msg header version: %d\n", response); in dcn401_smu_check_msg_header_version()
201 smu_print("FCLK P-state support value is : %d\n", support); in dcn401_smu_send_fclk_pstate_message()
209 smu_print("UCLK P-state support value is : %d\n", support); in dcn401_smu_send_uclk_pstate_message()
220 smu_print("Numways for SubVP : %d\n", num_ways); in dcn401_smu_send_cab_for_uclk_message()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| H A D | dcn35_smu.c | 62 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); } macro
206 …smu_print("requested_dispclk_khz = %d, actual_dispclk_set_mhz: %d\n", requested_dispclk_khz, actua… in dcn35_smu_set_dispclk()
239 …smu_print("requested_dcfclk_khz = %d, actual_dcfclk_set_mhz: %d\n", requested_dcfclk_khz, actual_d… in dcn35_smu_set_hard_min_dcfclk()
256 …smu_print("requested_min_ds_dcfclk_khz = %d, actual_min_ds_dcfclk_mhz: %d\n", requested_min_ds_dcf… in dcn35_smu_set_min_deep_sleep_dcfclk()
273 …smu_print("requested_dpp_khz = %d, actual_dppclk_set_mhz: %d\n", requested_dpp_khz, actual_dppclk_… in dcn35_smu_set_dppclk()
291 smu_print("%s: VBIOSSMC_MSG_SetDisplayIdleOptimizations idle_info = %x\n", __func__, idle_info); in dcn35_smu_set_display_idle_optimization()
310 smu_print("%s smu_enable_phy_refclk_pwrdwn = %d\n", __func__, enable ? 1 : 0); in dcn35_smu_enable_phy_refclk_pwrdwn()
322 smu_print("%s: SMC_MSG_UpdatePmeRestore\n", __func__); in dcn35_smu_enable_pme_wa()
373 smu_print("%s: SMC_MSG_AllowZstatesEntry msg = ALLOW, param = 0x%x\n", __func__, param); in dcn35_smu_set_zstate_support()
379 smu_print("%s: SMC_MSG_AllowZstatesEntry msg_id = DISALLOW, param = 0x%x\n", __func__, param); in dcn35_smu_set_zstate_support()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| H A D | dcn32_clk_mgr_smu_msg.c | 42 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); } macro
163 smu_print("FCLK P-state support value is : %d\n", enable); in dcn32_smu_send_fclk_pstate_message()
174 smu_print("Numways for SubVP : %d\n", num_ways); in dcn32_smu_send_cab_for_uclk_message()
179 smu_print("SMU Transfer WM table DRAM 2 SMU\n"); in dcn32_smu_transfer_wm_table_dram_2_smu()
187 smu_print("SMU Set PME workaround\n"); in dcn32_smu_set_pme_workaround()
220 smu_print("SMU Get hard min status: no_timeout %d delay %d us clk bits %x\n", in dcn32_smu_get_hard_min_status()
264 smu_print("SMU Wait get hard min status: %d timeouts\n", cur_wait_get_hard_min_max_timeouts); in dcn32_smu_wait_get_hard_min_status()
274 …smu_print("SMU Wait get hard min status: no_timeout %d, delay %d us, max %d us, read %x, check %x\… in dcn32_smu_wait_get_hard_min_status()
289 smu_print("SMU Set hard min by freq: clk = %d, freq_mhz = %d MHz\n", clk, freq_mhz); in dcn32_smu_set_hard_min_by_freq()
296 smu_print("SMU Frequency set = %d KHz hard_min_done %d\n", response, hard_min_done); in dcn32_smu_set_hard_min_by_freq()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
| H A D | dcn315_smu.c | 70 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); } macro
143 smu_print("SMU Response was not OK. SMU response after wait received is: %d\n", result); in dcn315_smu_send_msg_with_param()
164 smu_print("SMU msg id write fail %x times. \n", i + 1); in dcn315_smu_send_msg_with_param()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| H A D | rn_clk_mgr_vbios_smu.c | 50 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); } macro
108 smu_print("SMU Response was not OK. SMU response after wait received is: %d\n", result); in rn_vbios_smu_send_msg_with_param()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| H A D | dcn301_smu.c | 49 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); } macro
107 smu_print("SMU Response was not OK. SMU response after wait received is: %d\n", result); in dcn301_smu_send_msg_with_param()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| H A D | dcn316_smu.c | 63 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); } macro
127 smu_print("SMU Response was not OK. SMU response after wait received is: %d\n", result); in dcn316_smu_send_msg_with_param()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| H A D | dcn314_smu.c | 62 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); } macro
128 smu_print("SMU Response was not OK. SMU response after wait received is: %d\n", in dcn314_smu_send_msg_with_param()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| H A D | dcn31_smu.c | 46 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); } macro
112 smu_print("SMU Response was not OK. SMU response after wait received is: %d\n", result); in dcn31_smu_send_msg_with_param()
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