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Searched refs:slice_mask (Results 1 – 20 of 20) sorted by relevance

/linux/arch/powerpc/mm/book3s64/
H A Dslice.c34 static void slice_print_mask(const char *label, const struct slice_mask *mask) in slice_print_mask()
48 static void slice_print_mask(const char *label, const struct slice_mask *mask) {} in slice_print_mask()
61 struct slice_mask *ret) in slice_range_to_mask()
117 static void slice_mask_for_free(struct mm_struct *mm, struct slice_mask *ret, in slice_mask_for_free()
139 const struct slice_mask *available, in slice_check_range_fits()
188 const struct slice_mask *mask, int psize) in slice_convert()
193 struct slice_mask *psize_mask, *old_mask; in slice_convert()
264 const struct slice_mask *available, in slice_scan_available()
282 const struct slice_mask *available, in slice_find_area_bottomup()
324 const struct slice_mask *available, in slice_find_area_topdown()
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/linux/drivers/gpu/drm/i915/gt/
H A Dintel_sseu.c158 sseu->slice_mask |= BIT(0); in gen11_compute_sseu_info()
174 sseu->slice_mask |= BIT(0); in xehp_compute_sseu_info()
336 sseu->slice_mask = BIT(0); in cherryview_sseu_info_init()
387 sseu->slice_mask = REG_FIELD_GET(GEN8_F2_S_ENA_MASK, fuse2); in gen9_sseu_info_init()
405 if (!(sseu->slice_mask & BIT(s))) in gen9_sseu_info_init()
460 !IS_GEN9_LP(i915) && hweight8(sseu->slice_mask) > 1; in gen9_sseu_info_init()
491 sseu->slice_mask = REG_FIELD_GET(GEN8_F2_S_ENA_MASK, fuse2); in bdw_sseu_info_init()
517 if (!(sseu->slice_mask & BIT(s))) in bdw_sseu_info_init()
562 sseu->has_slice_pg = hweight8(sseu->slice_mask) > 1; in bdw_sseu_info_init()
584 sseu->slice_mask = BIT(0); in hsw_sseu_info_init()
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H A Dintel_sseu.h69 u8 slice_mask; member
102 u8 slice_mask; member
112 .slice_mask = sseu->slice_mask, in intel_sseu_from_device_info()
H A Dintel_workarounds.c1159 slice = ffs(sseu->slice_mask) - 1; in gen9_wa_init_mcr()
1308 GEM_BUG_ON(hweight8(sseu->slice_mask) > 1); in icl_wa_init_mcr()
1336 unsigned long slice, subslice = 0, slice_mask = 0; in xehp_init_mcr() local
1367 slice_mask = intel_slicemask_from_xehp_dssmask(sseu->subslice_mask, in xehp_init_mcr()
1381 if (slice_mask & lncf_mask) { in xehp_init_mcr()
1382 slice_mask &= lncf_mask; in xehp_init_mcr()
1387 if (slice_mask & gt->info.mslice_mask) { in xehp_init_mcr()
1388 slice_mask &= gt->info.mslice_mask; in xehp_init_mcr()
1392 slice = __ffs(slice_mask); in xehp_init_mcr()
/linux/drivers/gpu/drm/msm/adreno/
H A Da8xx_gpu.c90 u32 slice_mask; in a8xx_gpu_get_slice_info() local
95 if (a6xx_gpu->slice_mask) in a8xx_gpu_get_slice_info()
98 slice_mask = GENMASK(info->max_slices - 1, 0); in a8xx_gpu_get_slice_info()
102 a6xx_gpu->slice_mask = slice_mask; in a8xx_gpu_get_slice_info()
106 slice_mask &= a6xx_llc_read(a6xx_gpu, in a8xx_gpu_get_slice_info()
109 a6xx_gpu->slice_mask = slice_mask; in a8xx_gpu_get_slice_info()
112 adreno_gpu->chip_id |= FIELD_PREP(GENMASK(7, 4), hweight32(slice_mask)); in a8xx_gpu_get_slice_info()
117 return ffs(a6xx_gpu->slice_mask) - 1; in a8xx_get_first_slice()
H A Da6xx_gpu.h114 u32 slice_mask; member
/linux/arch/powerpc/include/asm/book3s/64/
H A Dmmu-hash.h707 struct slice_mask { struct
720 struct slice_mask mask_64k; argument
722 struct slice_mask mask_4k;
724 struct slice_mask mask_16m;
725 struct slice_mask mask_16g;
H A Dmmu.h169 static inline struct slice_mask *slice_mask_for_size(mm_context_t *ctx, int psize) in slice_mask_for_size()
/linux/drivers/gpu/drm/i915/gem/
H A Di915_gem_context.c1000 if (sseu.slice_mask && !WARN_ON(ce->engine->class != RENDER_CLASS)) in intel_context_set_gem()
1915 if (!user->slice_mask || !user->subslice_mask || in i915_gem_user_to_context_sseu()
1927 if (overflows_type(user->slice_mask, context->slice_mask) || in i915_gem_user_to_context_sseu()
1936 if (user->slice_mask & ~device->slice_mask) in i915_gem_user_to_context_sseu()
1945 context->slice_mask = user->slice_mask; in i915_gem_user_to_context_sseu()
1952 unsigned int hw_s = hweight8(device->slice_mask); in i915_gem_user_to_context_sseu()
1954 unsigned int req_s = hweight8(context->slice_mask); in i915_gem_user_to_context_sseu()
2509 user_sseu.slice_mask = ce->sseu.slice_mask; in get_sseu()
/linux/drivers/crypto/intel/qat/qat_common/
H A Dicp_qat_fw_loader_handle.h19 unsigned int slice_mask; member
H A Dqat_hal.c801 handle->hal_handle->slice_mask = hw_data->accel_mask; in qat_hal_chip_init()
/linux/drivers/gpu/drm/i915/
H A Di915_query.c44 BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask)); in fill_topology_info()
49 slice_length = sizeof(sseu->slice_mask); in fill_topology_info()
75 &sseu->slice_mask, slice_length)) in fill_topology_info()
H A Di915_getparam.c175 value = sseu->slice_mask; in i915_getparam_ioctl()
H A Di915_perf.c3172 out_sseu->slice_mask = 0x1; in get_default_sseu_config()
/linux/drivers/gpu/drm/i915/display/
H A Dskl_watermark.c410 hweight8(DISPLAY_INFO(display)->dbuf.slice_mask); in intel_dbuf_slice_size()
414 skl_ddb_entry_for_slices(struct intel_display *display, u8 slice_mask, in skl_ddb_entry_for_slices() argument
419 if (!slice_mask) { in skl_ddb_entry_for_slices()
425 ddb->start = (ffs(slice_mask) - 1) * slice_size; in skl_ddb_entry_for_slices()
426 ddb->end = fls(slice_mask) * slice_size; in skl_ddb_entry_for_slices()
432 static unsigned int mbus_ddb_offset(struct intel_display *display, u8 slice_mask) in mbus_ddb_offset() argument
436 if (slice_mask & (BIT(DBUF_S1) | BIT(DBUF_S2))) in mbus_ddb_offset()
437 slice_mask = BIT(DBUF_S1); in mbus_ddb_offset()
438 else if (slice_mask & (BIT(DBUF_S3) | BIT(DBUF_S4))) in mbus_ddb_offset()
439 slice_mask = BIT(DBUF_S3); in mbus_ddb_offset()
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H A Dintel_display_device.c663 .dbuf.slice_mask = BIT(DBUF_S1),
813 .dbuf.slice_mask = BIT(DBUF_S1), \
872 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
962 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
1129 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
1307 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
/linux/drivers/gpu/drm/i915/gem/selftests/
H A Di915_gem_context.c1170 unsigned int slices = hweight32(ce->engine->sseu.slice_mask); in __sseu_finish()
1227 hweight32(sseu.slice_mask), spin); in __sseu_test()
1272 if (hweight32(engine->sseu.slice_mask) < 2) in __igt_ctx_sseu()
1283 pg_sseu.slice_mask = 1; in __igt_ctx_sseu()
1289 hweight32(engine->sseu.slice_mask), in __igt_ctx_sseu()
1290 hweight32(pg_sseu.slice_mask)); in __igt_ctx_sseu()
/linux/include/uapi/drm/
H A Di915_drm.h2218 __u64 slice_mask; member
/linux/tools/include/uapi/drm/
H A Di915_drm.h2218 __u64 slice_mask; member
/linux/drivers/gpu/drm/i915/gt/uc/
H A Dintel_guc_ads.c900 hweight8(gt->info.sseu.slice_mask)); in __guc_ads_init()