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Searched refs:set_wptr (Results 1 – 25 of 25) sorted by relevance

/linux/drivers/gpu/drm/radeon/
H A Dradeon_asic.c194 .set_wptr = &r100_gfx_set_wptr,
344 .set_wptr = &r100_gfx_set_wptr,
358 .set_wptr = &r100_gfx_set_wptr,
915 .set_wptr = &r600_gfx_set_wptr,
928 .set_wptr = &r600_dma_set_wptr,
1013 .set_wptr = &uvd_v1_0_set_wptr,
1212 .set_wptr = &uvd_v1_0_set_wptr,
1319 .set_wptr = &r600_gfx_set_wptr,
1332 .set_wptr = &r600_dma_set_wptr,
1629 .set_wptr = &cayman_gfx_set_wptr,
[all …]
H A Dradeon.h1805 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); member
2717 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_ring.h236 void (*set_wptr)(struct amdgpu_ring *ring); member
436 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
H A Djpeg_v2_5.c698 .set_wptr = jpeg_v2_5_dec_ring_set_wptr,
729 .set_wptr = jpeg_v2_5_dec_ring_set_wptr,
H A Djpeg_v5_0_0.c685 .set_wptr = jpeg_v5_0_0_dec_ring_set_wptr,
H A Damdgpu_umsch_mm.c100 .set_wptr = umsch_mm_ring_set_wptr,
H A Dvce_v1_0.c798 .set_wptr = vce_v1_0_ring_set_wptr,
H A Djpeg_v1_0.c563 .set_wptr = jpeg_v1_0_decode_ring_set_wptr,
H A Djpeg_v4_0_5.c809 .set_wptr = jpeg_v4_0_5_dec_ring_set_wptr,
H A Dsdma_v2_4.c1122 .set_wptr = sdma_v2_4_ring_set_wptr,
H A Dvcn_v2_5.c1784 .set_wptr = vcn_v2_5_dec_ring_set_wptr,
1884 .set_wptr = vcn_v2_5_enc_ring_set_wptr,
H A Dsdma_v4_4_2.c2117 .set_wptr = sdma_v4_4_2_ring_set_wptr,
2149 .set_wptr = sdma_v4_4_2_page_ring_set_wptr,
H A Dsdma_v4_0.c2421 .set_wptr = sdma_v4_0_ring_set_wptr,
2453 .set_wptr = sdma_v4_0_page_ring_set_wptr,
H A Dcik_sdma.c1228 .set_wptr = cik_sdma_ring_set_wptr,
H A Dsdma_v3_0.c1564 .set_wptr = sdma_v3_0_ring_set_wptr,
H A Dvcn_v5_0_0.c1212 .set_wptr = vcn_v5_0_0_unified_ring_set_wptr,
H A Dvcn_v4_0_5.c1488 .set_wptr = vcn_v4_0_5_unified_ring_set_wptr,
H A Dsdma_v6_0.c1768 .set_wptr = sdma_v6_0_ring_set_wptr,
H A Dmes_v11_0.c110 .set_wptr = mes_v11_0_ring_set_wptr,
H A Dgfx_v12_0.c5480 .set_wptr = gfx_v12_0_ring_set_wptr_gfx,
5527 .set_wptr = gfx_v12_0_ring_set_wptr_compute,
5565 .set_wptr = gfx_v12_0_ring_set_wptr_compute,
H A Dsdma_v5_2.c1931 .set_wptr = sdma_v5_2_ring_set_wptr,
H A Dsdma_v5_0.c1929 .set_wptr = sdma_v5_0_ring_set_wptr,
H A Dmes_v12_0.c89 .set_wptr = mes_v12_0_ring_set_wptr,
H A Dgfx_v11_0.c7216 .set_wptr = gfx_v11_0_ring_set_wptr_gfx,
7270 .set_wptr = gfx_v11_0_ring_set_wptr_compute,
7311 .set_wptr = gfx_v11_0_ring_set_wptr_compute,
H A Dgfx_v10_0.c9828 .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
9885 .set_wptr = gfx_v10_0_ring_set_wptr_compute,
9925 .set_wptr = gfx_v10_0_ring_set_wptr_compute,