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Searched refs:seq_state (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_hw_sequencer.c1329 void hwss_add_optc_pipe_control_lock(struct block_sequence_state *seq_state, in hwss_add_optc_pipe_control_lock() argument
1334 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { in hwss_add_optc_pipe_control_lock()
1335 seq_state->steps[*seq_state->num_steps].params.pipe_control_lock_params.dc = dc; in hwss_add_optc_pipe_control_lock()
1336 seq_state->steps[*seq_state->num_steps].params.pipe_control_lock_params.pipe_ctx = pipe_ctx; in hwss_add_optc_pipe_control_lock()
1337 seq_state->steps[*seq_state->num_steps].params.pipe_control_lock_params.lock = lock; in hwss_add_optc_pipe_control_lock()
1338 seq_state->steps[*seq_state->num_steps].func = OPTC_PIPE_CONTROL_LOCK; in hwss_add_optc_pipe_control_lock()
1339 (*seq_state->num_steps)++; in hwss_add_optc_pipe_control_lock()
1346 void hwss_add_hubp_set_flip_control_gsl(struct block_sequence_state *seq_state, in hwss_add_hubp_set_flip_control_gsl() argument
1350 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { in hwss_add_hubp_set_flip_control_gsl()
1351 seq_state->steps[*seq_state->num_steps].params.set_flip_control_gsl_params.hubp = hubp; in hwss_add_hubp_set_flip_control_gsl()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/
H A Dhw_sequencer.h1009 struct block_sequence_state *seq_state);
1030 struct block_sequence_state *seq_state);
1275 struct block_sequence_state *seq_state);
1282 struct block_sequence_state *seq_state);
1288 struct block_sequence_state *seq_state);
1604 void hwss_add_optc_pipe_control_lock(struct block_sequence_state *seq_state,
1607 void hwss_add_hubp_set_flip_control_gsl(struct block_sequence_state *seq_state,
1610 void hwss_add_hubp_program_triplebuffer(struct block_sequence_state *seq_state,
1613 void hwss_add_hubp_update_plane_addr(struct block_sequence_state *seq_state,
1616 void hwss_add_dpp_set_input_transfer_func(struct block_sequence_state *seq_state,
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H A Dhw_sequencer_private.h87 struct block_sequence_state *seq_state);
90 struct block_sequence_state *seq_state);
110 struct block_sequence_state *seq_state);
120 struct block_sequence_state *seq_state);
131 struct block_sequence_state *seq_state);
161 struct pipe_ctx *pipe_ctx, struct block_sequence_state *seq_state);
169 struct block_sequence_state *seq_state);
173 struct block_sequence_state *seq_state);
176 struct block_sequence_state *seq_state);
184 struct block_sequence_state *seq_state);
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.h87 struct pipe_ctx *otg_master, struct block_sequence_state *seq_state);
107 struct block_sequence_state *seq_state);
123 struct block_sequence_state *seq_state);
127 struct block_sequence_state *seq_state);
132 struct block_sequence_state *seq_state);
140 struct block_sequence_state *seq_state);
147 struct block_sequence_state *seq_state);
152 struct block_sequence_state *seq_state);
158 struct block_sequence_state *seq_state);
164 struct block_sequence_state *seq_state);
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H A Ddcn401_hwseq.c1623 struct pipe_ctx *otg_master, struct block_sequence_state *seq_state) in dcn401_add_dsc_sequence_for_odm_change() argument
1659 hwss_add_dccg_set_dto_dscclk(seq_state, dc->res_pool->dccg, in dcn401_add_dsc_sequence_for_odm_change()
1664 last_dsc_calc = *seq_state->num_steps; in dcn401_add_dsc_sequence_for_odm_change()
1665 hwss_add_dsc_calculate_and_set_config(seq_state, otg_master, true, opp_cnt); in dcn401_add_dsc_sequence_for_odm_change()
1668 hwss_add_dsc_enable_with_opp(seq_state, otg_master); in dcn401_add_dsc_sequence_for_odm_change()
1677 hwss_add_dccg_set_dto_dscclk(seq_state, dc->res_pool->dccg, in dcn401_add_dsc_sequence_for_odm_change()
1682 last_dsc_calc = *seq_state->num_steps; in dcn401_add_dsc_sequence_for_odm_change()
1683 hwss_add_dsc_calculate_and_set_config(seq_state, odm_pipe, true, opp_cnt); in dcn401_add_dsc_sequence_for_odm_change()
1686 hwss_add_dsc_enable_with_opp(seq_state, odm_pipe); in dcn401_add_dsc_sequence_for_odm_change()
1690 hwss_add_tg_set_dsc_config(seq_state, otg_master->stream_res.tg, in dcn401_add_dsc_sequence_for_odm_change()
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/linux/arch/mips/kernel/
H A Dsmp-cps.c46 u32 stat, seq_state; in power_up_other_cluster() local
54 seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE; in power_up_other_cluster()
55 seq_state >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE); in power_up_other_cluster()
56 if (seq_state == CPC_Cx_STAT_CONF_SEQSTATE_U5) in power_up_other_cluster()
71 seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE; in power_up_other_cluster()
72 seq_state >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE); in power_up_other_cluster()
73 if (seq_state == CPC_Cx_STAT_CONF_SEQSTATE_U5) in power_up_other_cluster()
472 u32 access, stat, seq_state; in boot_core() local
565 seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE; in boot_core()
566 seq_state >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE); in boot_core()
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/linux/arch/alpha/kernel/
H A Dcore_cia.c938 const char *seq_state; in cia_decode_mem_error() local
973 seq_state = "Idle"; in cia_decode_mem_error()
976 seq_state = "DMA READ or DMA WRITE"; in cia_decode_mem_error()
979 seq_state = "READ MISS (or READ MISS MODIFY) with victim"; in cia_decode_mem_error()
982 seq_state = "READ MISS (or READ MISS MODIFY) with no victim"; in cia_decode_mem_error()
985 seq_state = "Refresh"; in cia_decode_mem_error()
988 seq_state = "Idle, waiting for DMA pending read"; in cia_decode_mem_error()
991 seq_state = "Idle, ras precharge"; in cia_decode_mem_error()
994 seq_state = "Unknown"; in cia_decode_mem_error()
1024 printk(KERN_CRIT " Memory sequencer state: %s\n", seq_state); in cia_decode_mem_error()
/linux/drivers/spi/
H A Dspi-fsi.c368 u64 seq_state; in fsi_spi_transfer_init() local
384 seq_state = status & SPI_FSI_STATUS_SEQ_STATE; in fsi_spi_transfer_init()
403 } while (seq_state && (seq_state != SPI_FSI_STATUS_SEQ_STATE_IDLE)); in fsi_spi_transfer_init()
/linux/drivers/hwtracing/coresight/
H A Dcoresight-etm4x-cfg.c69 CHECKREG(TRCSEQSTR, seq_state); in etm4_cfg_map_reg_offset()
H A Dcoresight-etm4x.h882 u32 seq_state; member
957 u32 seq_state; member
H A Dcoresight-etm4x-sysfs.c229 config->seq_state = 0x0; in reset_store()
1422 val = config->seq_state; in seq_state_show()
1439 config->seq_state = val; in seq_state_store()
1442 static DEVICE_ATTR_RW(seq_state);
H A Dcoresight-etm4x-core.c551 etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); in etm4_enable_hw()
/linux/drivers/net/ieee802154/
H A Dmcr20a.c885 u8 seq_state = lp->irq_data[DAR_IRQ_STS1] & DAR_PHY_CTRL1_XCVSEQ_MASK; in mcr20a_irq_clean_complete() local
894 switch (seq_state) { in mcr20a_irq_clean_complete()
/linux/Documentation/trace/coresight/
H A Dcoresight-etm4x-reference.rst559 :File: ``seq_state`` (rw)
/linux/Documentation/ABI/testing/
H A Dsysfs-bus-coresight-devices-etm4x189 What: /sys/bus/coresight/devices/etm<N>/seq_state