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Searched refs:sdhci_writel (Results 1 – 25 of 27) sorted by relevance

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/linux/drivers/mmc/host/
H A Dsdhci-pci-dwc-mshc.c41 sdhci_writel(host, reg, (SDHC_AT_CTRL_R + vendor_ptr)); in sdhci_snps_set_clock()
49 sdhci_writel(host, reg, (SDHC_GPIO_OUT + vendor_ptr)); in sdhci_snps_set_clock()
53 sdhci_writel(host, DIV_REG_100_MHZ, SDHC_MMCM_DIV_REG); in sdhci_snps_set_clock()
54 sdhci_writel(host, CLKFBOUT_100_MHZ, in sdhci_snps_set_clock()
57 sdhci_writel(host, DIV_REG_200_MHZ, SDHC_MMCM_DIV_REG); in sdhci_snps_set_clock()
58 sdhci_writel(host, CLKFBOUT_200_MHZ, in sdhci_snps_set_clock()
65 sdhci_writel(host, reg, (SDHC_GPIO_OUT + vendor_ptr)); in sdhci_snps_set_clock()
H A Dsdhci-milbeaut.c67 sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2); in sdhci_milbeaut_soft_voltage_switch()
69 sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2); in sdhci_milbeaut_soft_voltage_switch()
72 sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2); in sdhci_milbeaut_soft_voltage_switch()
77 sdhci_writel(host, ctrl, F_SDH30_TUNING_SETTING); in sdhci_milbeaut_soft_voltage_switch()
120 sdhci_writel(host, ctl, F_SDH30_ESD_CONTROL); in sdhci_milbeaut_reset()
138 sdhci_writel(host, 0, MLB_SOFT_RESET); in sdhci_milbeaut_bridge_reset()
140 sdhci_writel(host, MLB_SOFT_RESET_RSTX, MLB_SOFT_RESET); in sdhci_milbeaut_bridge_reset()
169 sdhci_writel(host, val, MLB_CR_SET); in sdhci_milbeaut_bridge_init()
171 sdhci_writel(host, MLB_CDR_SET_CLK2POW16, MLB_CDR_SET); in sdhci_milbeaut_bridge_init()
173 sdhci_writel(host, MLB_WP_CD_LED_SET_LED_INV, MLB_WP_CD_LED_SET); in sdhci_milbeaut_bridge_init()
[all …]
H A Dsdhci-of-esdhc.c527 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); in esdhc_of_adma_workaround()
550 sdhci_writel(host, value, ESDHC_DMA_SYSCTL); in esdhc_of_enable_dma()
602 sdhci_writel(host, val, ESDHC_SYSTEM_CONTROL); in esdhc_clock_enable()
630 sdhci_writel(host, val, ESDHC_DMA_SYSCTL); in esdhc_flush_async_fifo()
723 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); in esdhc_of_set_clock()
747 sdhci_writel(host, temp | ESDHC_HS400_MODE, ESDHC_TBCTL); in esdhc_of_set_clock()
749 sdhci_writel(host, temp | ESDHC_CMD_CLK_CTL, ESDHC_SDCLKCTL); in esdhc_of_set_clock()
756 sdhci_writel(host, temp, ESDHC_DLLCFG0); in esdhc_of_set_clock()
759 sdhci_writel(host, temp, ESDHC_DLLCFG0); in esdhc_of_set_clock()
762 sdhci_writel(host, temp, ESDHC_DLLCFG0); in esdhc_of_set_clock()
[all …]
H A Dsdhci_f_sdh30.c47 sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2); in sdhci_f_sdh30_soft_voltage_switch()
49 sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2); in sdhci_f_sdh30_soft_voltage_switch()
52 sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2); in sdhci_f_sdh30_soft_voltage_switch()
59 sdhci_writel(host, ctrl, F_SDH30_ESD_CONTROL); in sdhci_f_sdh30_soft_voltage_switch()
64 sdhci_writel(host, ctrl, F_SDH30_TUNING_SETTING); in sdhci_f_sdh30_soft_voltage_switch()
85 sdhci_writel(host, ctl, F_SDH30_ESD_CONTROL); in sdhci_f_sdh30_reset()
92 sdhci_writel(host, ctl, F_SDH30_TEST); in sdhci_f_sdh30_reset()
178 sdhci_writel(host, reg & ~F_SDH30_EMMC_RST, F_SDH30_ESD_CONTROL); in sdhci_f_sdh30_probe()
180 sdhci_writel(host, reg | F_SDH30_EMMC_RST, F_SDH30_ESD_CONTROL); in sdhci_f_sdh30_probe()
H A Dsdhci-xenon-phy.c258 sdhci_writel(host, reg, phy_regs->timing_adj); in xenon_emmc_phy_init()
383 sdhci_writel(host, reg, phy_regs->dll_ctrl); in xenon_emmc_phy_enable_dll()
438 sdhci_writel(host, reg, XENON_SLOT_OP_STATUS_CTRL); in xenon_emmc_phy_config_tuning()
452 sdhci_writel(host, reg, XENON_SLOT_EMMC_CTRL); in xenon_emmc_phy_disable_strobe()
458 sdhci_writel(host, reg, XENON_EMMC_5_0_PHY_PAD_CONTROL); in xenon_emmc_phy_disable_strobe()
462 sdhci_writel(host, reg, XENON_EMMC_PHY_PAD_CONTROL1); in xenon_emmc_phy_disable_strobe()
495 sdhci_writel(host, reg, XENON_SLOT_EMMC_CTRL); in xenon_emmc_phy_strobe_delay_adj()
502 sdhci_writel(host, reg, XENON_EMMC_5_0_PHY_PAD_CONTROL); in xenon_emmc_phy_strobe_delay_adj()
507 sdhci_writel(host, reg, XENON_EMMC_PHY_PAD_CONTROL1); in xenon_emmc_phy_strobe_delay_adj()
566 sdhci_writel(host, reg, phy_regs->timing_adj); in xenon_emmc_phy_slow_mode()
[all …]
H A Dsdhci-of-dwcmshc.c365 sdhci_writel(host, SDHCI_INT_RESPONSE, SDHCI_INT_STATUS); in dwcmshc_reset()
423 sdhci_writel(host, val, PHY_CNFG_R); in dwcmshc_phy_init()
553 sdhci_writel(host, vendor, reg); in dwcmshc_hs400_enhanced_strobe()
650 sdhci_writel(host, reg, dwc_priv->vendor_specific_area2 + CQHCI_SSC1); in rk35xx_sdhci_cqe_pre_enable()
654 sdhci_writel(host, reg, dwc_priv->vendor_specific_area2 + CQHCI_CFG); in rk35xx_sdhci_cqe_pre_enable()
688 sdhci_writel(host, ctrl, SDHCI_INT_ENABLE); in rk35xx_sdhci_cqe_disable()
689 sdhci_writel(host, SDHCI_INT_RESPONSE, SDHCI_INT_STATUS); in rk35xx_sdhci_cqe_disable()
704 sdhci_writel(host, ctrl, dwc_priv->vendor_specific_area2 + CQHCI_CFG); in rk35xx_sdhci_cqe_post_disable()
739 sdhci_writel(host, extra, reg); in dwcmshc_rk3568_set_clock()
753 sdhci_writel(host, DWCMSHC_EMMC_DLL_BYPASS | DWCMSHC_EMMC_DLL_START, DWCMSHC_EMMC_DLL_CTRL); in dwcmshc_rk3568_set_clock()
[all …]
H A Dsdhci-xenon.c34 sdhci_writel(host, reg, SDHCI_CLOCK_CONTROL); in xenon_enable_internal_clk()
68 sdhci_writel(host, reg, XENON_SYS_OP_CTRL); in xenon_set_sdclk_off_idle()
81 sdhci_writel(host, reg, XENON_SYS_OP_CTRL); in xenon_set_acg()
92 sdhci_writel(host, reg, XENON_SYS_OP_CTRL); in xenon_enable_sdhc()
110 sdhci_writel(host, reg, XENON_SYS_OP_CTRL); in xenon_disable_sdhc()
121 sdhci_writel(host, reg, XENON_SYS_EXT_OP_CTRL); in xenon_enable_sdhc_parallel_tran()
131 sdhci_writel(host, reg, XENON_SYS_EXT_OP_CTRL); in xenon_mask_cmd_conflict_err()
143 sdhci_writel(host, reg, XENON_SLOT_RETUNING_REQ_CTRL); in xenon_retune_setup()
148 sdhci_writel(host, reg, SDHCI_SIGNAL_ENABLE); in xenon_retune_setup()
151 sdhci_writel(host, reg, SDHCI_INT_ENABLE); in xenon_retune_setup()
[all …]
H A Dsdhci-bcm-kona.c58 sdhci_writel(host, val, KONA_SDHOST_CORECTRL); in sdhci_bcm_kona_sd_reset()
78 sdhci_writel(host, val, KONA_SDHOST_CORECTRL); in sdhci_bcm_kona_sd_reset()
90 sdhci_writel(host, val, KONA_SDHOST_COREIMR); in sdhci_bcm_kona_sd_init()
103 sdhci_writel(host, val, KONA_SDHOST_CORECTRL); in sdhci_bcm_kona_sd_init()
138 sdhci_writel(host, val, KONA_SDHOST_CORESTAT); in sdhci_bcm_kona_sd_card_emulate()
141 sdhci_writel(host, val, KONA_SDHOST_CORESTAT); in sdhci_bcm_kona_sd_card_emulate()
H A Dsdhci-sprd.c125 sdhci_writel(host, val, SDHCI_SPRD_REG_DEBOUNCE); in sdhci_sprd_init_config()
202 sdhci_writel(host, dll_dly_offset, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); in sdhci_sprd_set_dll_invert()
247 sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI); in _sdhci_sprd_set_clock()
252 sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI); in _sdhci_sprd_set_clock()
263 sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG); in sdhci_sprd_enable_phy_dll()
270 sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG); in sdhci_sprd_enable_phy_dll()
276 sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG); in sdhci_sprd_enable_phy_dll()
377 sdhci_writel(host, p[timing], SDHCI_SPRD_REG_32_DLL_DLY); in sdhci_sprd_set_uhs_signaling()
567 sdhci_writel(host, p[MMC_TIMING_MMC_HS400 + 1], in sdhci_sprd_hs400_enhanced_strobe()
647 sdhci_writel(host, dll_cfg, SDHCI_SPRD_REG_32_DLL_CFG); in sdhci_sprd_tuning()
[all …]
H A Dsdhci-uhs2.c117 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); in sdhci_uhs2_reset_cmd_data()
118 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); in sdhci_uhs2_reset_cmd_data()
251 sdhci_writel(host, ier, SDHCI_UHS2_INT_STATUS_ENABLE); in sdhci_uhs2_clear_set_irqs()
252 sdhci_writel(host, ier, SDHCI_UHS2_INT_SIGNAL_ENABLE); in sdhci_uhs2_clear_set_irqs()
437 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); in sdhci_uhs2_do_detect_init()
438 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); in sdhci_uhs2_do_detect_init()
484 sdhci_writel(host, value, sdhci_uhs2_gen_set_reg); in sdhci_uhs2_set_config()
492 sdhci_writel(host, value, sdhci_uhs2_phy_set_reg); in sdhci_uhs2_set_config()
497 sdhci_writel(host, value, sdhci_uhs2_tran_set_reg); in sdhci_uhs2_set_config()
498 sdhci_writel(host, host->mmc->uhs2_caps.n_data_gap_set, sdhci_uhs2_tran_set_1_reg); in sdhci_uhs2_set_config()
[all …]
H A Dsdhci-pci-gli.c323 sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT); in gl9750_wt_on()
340 sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT); in gl9750_wt_off()
359 sdhci_writel(host, burst_value, SDHCI_GLI_9750_GM_BURST_SIZE); in gli_set_9750()
376 sdhci_writel(host, driving_value, SDHCI_GLI_9750_DRIVING); in gli_set_9750()
381 sdhci_writel(host, sw_ctrl_value, SDHCI_GLI_9750_SW_CTRL); in gli_set_9750()
412 sdhci_writel(host, pll_value, SDHCI_GLI_9750_PLL); in gli_set_9750()
413 sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC); in gli_set_9750()
424 sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL); in gli_set_9750()
427 sdhci_writel(host, parameter_value, SDHCI_GLI_9750_TUNING_PARAMETERS); in gli_set_9750()
433 sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL); in gli_set_9750()
[all …]
H A Dsdhci.c174 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); in sdhci_set_card_detection()
175 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); in sdhci_set_card_detection()
312 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); in sdhci_set_default_irqs()
313 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); in sdhci_set_default_irqs()
605 sdhci_writel(host, scratch, SDHCI_BUFFER); in sdhci_write_block_pio()
886 sdhci_writel(host, lower_32_bits(addr), SDHCI_ADMA_ADDRESS); in sdhci_set_adma_addr()
888 sdhci_writel(host, upper_32_bits(addr), SDHCI_ADMA_ADDRESS_HI); in sdhci_set_adma_addr()
904 sdhci_writel(host, addr, SDHCI_DMA_ADDRESS); in sdhci_set_sdma_addr()
1042 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); in sdhci_set_transfer_irqs()
1043 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); in sdhci_set_transfer_irqs()
[all …]
H A Dsdhci-tegra.c355 sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); in tegra_sdhci_set_tap()
407 sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL); in tegra_sdhci_reset()
408 sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); in tegra_sdhci_reset()
414 sdhci_writel(host, pad_ctrl, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); in tegra_sdhci_reset()
437 sdhci_writel(host, val, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); in tegra_sdhci_configure_cal_pad()
451 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); in tegra_sdhci_set_pad_autocal_offset()
497 sdhci_writel(host, reg, in tegra_sdhci_set_padctrl()
559 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); in tegra_sdhci_pad_autocalib()
577 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); in tegra_sdhci_pad_autocalib()
815 sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL); in tegra_sdhci_hs400_enhanced_strobe()
[all …]
H A Dsdhci-of-arasan.c468 sdhci_writel(host, vendor, SDHCI_ARASAN_VENDOR_REGISTER); in sdhci_arasan_hs400_enhanced_strobe()
944 sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER); in sdhci_versal_sdcardclk_set_phase()
947 sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER); in sdhci_versal_sdcardclk_set_phase()
1011 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER); in sdhci_versal_sampleclk_set_phase()
1013 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER); in sdhci_versal_sampleclk_set_phase()
1016 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER); in sdhci_versal_sampleclk_set_phase()
1018 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER); in sdhci_versal_sampleclk_set_phase()
1060 sdhci_writel(host, regval, PHY_CTRL_REG1); in sdhci_versal_net_emmc_sdcardclk_set_phase()
1063 sdhci_writel(host, regval, PHY_CTRL_REG1); in sdhci_versal_net_emmc_sdcardclk_set_phase()
1094 sdhci_writel(host, regval, PHY_CTRL_REG1); in sdhci_versal_net_emmc_sampleclk_set_phase()
[all …]
H A Dsdhci-of-k1.c71 sdhci_writel(host, sdhci_readl(host, reg) | val, reg); in spacemit_sdhci_setbits()
76 sdhci_writel(host, sdhci_readl(host, reg) & ~val, reg); in spacemit_sdhci_clrbits()
84 sdhci_writel(host, val, reg); in spacemit_sdhci_clrsetbits()
H A Dsdhci-pci-o2micro.c118 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_enable_internal_clock()
121 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_enable_internal_clock()
125 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_enable_internal_clock()
152 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_enable_internal_clock()
265 sdhci_writel(host, scratch_32, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_dll_recovery()
791 sdhci_writel(host, reg, O2_SD_VENDOR_SETTING2); in sdhci_pci_o2_probe_slot()
H A Dsdhci-omap.c494 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); in sdhci_omap_execute_tuning()
495 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); in sdhci_omap_execute_tuning()
521 sdhci_writel(host, ier, SDHCI_INT_ENABLE); in sdhci_omap_card_busy()
522 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE); in sdhci_omap_card_busy()
537 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); in sdhci_omap_card_busy()
538 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); in sdhci_omap_card_busy()
912 sdhci_writel(host, intmask & CMD_MASK, SDHCI_INT_STATUS); in sdhci_omap_irq()
H A Dsdhci-pxav2.c108 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK, SDHCI_INT_STATUS); in pxav1_irq()
145 sdhci_writel(host, 0, SDHCI_ARGUMENT); in pxav1_request_done()
H A Dsdhci-acpi.c404 sdhci_writel(host, 0x3, VENDOR_SPECIFIC_PWRCTL_CLEAR_REG); in sdhci_acpi_qcom_handler()
405 sdhci_writel(host, 0x1, VENDOR_SPECIFIC_PWRCTL_CTL_REG); in sdhci_acpi_qcom_handler()
519 sdhci_writel(host, 0x40003210, SDHCI_AMD_RESET_DLL_REGISTER); in sdhci_acpi_amd_hs400_dll()
522 sdhci_writel(host, 0x40033210, SDHCI_AMD_RESET_DLL_REGISTER); in sdhci_acpi_amd_hs400_dll()
H A Dsdhci-esdhc-mcf.c201 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); in esdhc_mcf_reset()
202 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); in esdhc_mcf_reset()
H A Dsdhci-brcmstb.c155 sdhci_writel(host, reg, SDHCI_VENDOR); in enable_clock_gating()
179 sdhci_writel(host, reg | new_mask, SDHCI_CLOCK_CONTROL); in brcmstb_sdhci_reset_cmd_data()
H A Dsdhci.h731 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) in sdhci_writel() function
781 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) in sdhci_writel() function
H A Dsdhci-of-ma35d1.c165 sdhci_writel(host, regs[idx], restore_data[idx].reg); in ma35_execute_tuning()
H A Dsdhci-esdhc-imx.c996 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); in esdhc_pltfm_set_clock()
1025 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); in esdhc_pltfm_set_clock()
1458 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); in esdhc_reset()
1459 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); in esdhc_reset()
H A Dsdhci-of-at91.c128 sdhci_writel(host, calcr | SDMMC_CALCR_ALWYSON | SDMMC_CALCR_EN, in sdhci_at91_reset()

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