Searched refs:sclk_voltage_mapping_table (Results 1 – 8 of 8) sorted by relevance
88 struct sumo_sclk_voltage_mapping_table sclk_voltage_mapping_table; member198 struct sumo_sclk_voltage_mapping_table *sclk_voltage_mapping_table,
1032 for (i = 0; i < pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries; i++) { in sumo_get_valid_engine_clock()1033 if (pi->sys_info.sclk_voltage_mapping_table.entries[i].sclk_frequency >= lower_limit) in sumo_get_valid_engine_clock()1034 return pi->sys_info.sclk_voltage_mapping_table.entries[i].sclk_frequency; in sumo_get_valid_engine_clock()1037 …return pi->sys_info.sclk_voltage_mapping_table.entries[pi->sys_info.sclk_voltage_mapping_table.num… in sumo_get_valid_engine_clock()1592 struct sumo_sclk_voltage_mapping_table *sclk_voltage_mapping_table, in sumo_construct_sclk_voltage_mapping_table() argument1601 sclk_voltage_mapping_table->entries[n].sclk_frequency = in sumo_construct_sclk_voltage_mapping_table()1603 sclk_voltage_mapping_table->entries[n].vid_2bit = in sumo_construct_sclk_voltage_mapping_table()1610 sclk_voltage_mapping_table->num_max_dpm_entries = n; in sumo_construct_sclk_voltage_mapping_table()1718 &pi->sys_info.sclk_voltage_mapping_table, in sumo_parse_sys_info_table()
87 struct sumo_sclk_voltage_mapping_table sclk_voltage_mapping_table; member
573 &pi->sys_info.sclk_voltage_mapping_table; in kv_program_bootup_state()945 &pi->sys_info.sclk_voltage_mapping_table; in kv_calculate_dfs_bypass_settings()1558 &pi->sys_info.sclk_voltage_mapping_table; in kv_set_valid_clock_range()1768 if (pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries > 0) { in kv_construct_max_power_limits_table()1769 int idx = pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1; in kv_construct_max_power_limits_table()1771 pi->sys_info.sclk_voltage_mapping_table.entries[idx].sclk_frequency; in kv_construct_max_power_limits_table()1774 pi->sys_info.sclk_voltage_mapping_table.entries[idx].vid_2bit); in kv_construct_max_power_limits_table()1918 &pi->sys_info.sclk_voltage_mapping_table; in kv_get_high_voltage_limit()2000 &pi->sys_info.sclk_voltage_mapping_table; in kv_apply_state_adjust_rules()2172 &pi->sys_info.sclk_voltage_mapping_table; in kv_init_graphics_levels()[all …]
101 struct sumo_sclk_voltage_mapping_table sclk_voltage_mapping_table; member
1339 for (i = 0; i < pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries; i++) { in trinity_get_valid_engine_clock()1340 if (pi->sys_info.sclk_voltage_mapping_table.entries[i].sclk_frequency >= lower_limit) in trinity_get_valid_engine_clock()1341 return pi->sys_info.sclk_voltage_mapping_table.entries[i].sclk_frequency; in trinity_get_valid_engine_clock()1344 if (i == pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries) in trinity_get_valid_engine_clock()1862 &pi->sys_info.sclk_voltage_mapping_table, in trinity_parse_sys_info_table()
138 struct sumo_sclk_voltage_mapping_table *sclk_voltage_mapping_table, in sumo_construct_sclk_voltage_mapping_table() argument147 sclk_voltage_mapping_table->entries[n].sclk_frequency = in sumo_construct_sclk_voltage_mapping_table()149 sclk_voltage_mapping_table->entries[n].vid_2bit = in sumo_construct_sclk_voltage_mapping_table()156 sclk_voltage_mapping_table->num_max_dpm_entries = n; in sumo_construct_sclk_voltage_mapping_table()805 &pi->sys_info.sclk_voltage_mapping_table; in kv_program_bootup_state()1177 &pi->sys_info.sclk_voltage_mapping_table; in kv_calculate_dfs_bypass_settings()1796 &pi->sys_info.sclk_voltage_mapping_table; in kv_set_valid_clock_range()2031 if (pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries > 0) { in kv_construct_max_power_limits_table()2032 int idx = pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1; in kv_construct_max_power_limits_table()2034 pi->sys_info.sclk_voltage_mapping_table.entries[idx].sclk_frequency; in kv_construct_max_power_limits_table()[all …]
127 struct sumo_sclk_voltage_mapping_table sclk_voltage_mapping_table; member