| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn32/ |
| H A D | dcn32_dpp.c | 35 const struct scaler_data *scl_data, in dscl32_calc_lb_num_partitions() argument
43 int line_size = scl_data->viewport.width < scl_data->recout.width ? in dscl32_calc_lb_num_partitions()
44 scl_data->viewport.width : scl_data->recout.width; in dscl32_calc_lb_num_partitions()
45 int line_size_c = scl_data->viewport_c.width < scl_data->recout.width ? in dscl32_calc_lb_num_partitions()
46 scl_data->viewport_c.width : scl_data->recout.width; in dscl32_calc_lb_num_partitions()
67 if (scl_data->viewport.width == scl_data->h_active && in dscl32_calc_lb_num_partitions()
68 scl_data->viewport.height == scl_data->v_active) { in dscl32_calc_lb_num_partitions()
81 if (scl_data->viewport.width == scl_data->h_active && in dscl32_calc_lb_num_partitions()
82 scl_data->viewport.height == scl_data->v_active) { in dscl32_calc_lb_num_partitions()
97 if (scl_data->lb_params.alpha_en in dscl32_calc_lb_num_partitions()
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| H A D | dcn32_dpp.h | 40 const struct spl_scaler_data *scl_data,
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn201/ |
| H A D | dcn201_dpp.c | 192 struct scaler_data *scl_data, in dpp201_get_optimal_number_of_taps() argument
196 if (scl_data->viewport.width != scl_data->h_active && in dpp201_get_optimal_number_of_taps()
197 scl_data->viewport.height != scl_data->v_active && in dpp201_get_optimal_number_of_taps()
199 scl_data->format == PIXEL_FORMAT_FP16) in dpp201_get_optimal_number_of_taps()
202 if (scl_data->viewport.width > scl_data->h_active && in dpp201_get_optimal_number_of_taps()
204 scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width) in dpp201_get_optimal_number_of_taps()
208 if (scl_data->ratios.horz.value == (8ll << 32)) in dpp201_get_optimal_number_of_taps()
209 scl_data->ratios.horz.value--; in dpp201_get_optimal_number_of_taps()
210 if (scl_data->ratios.vert.value == (8ll << 32)) in dpp201_get_optimal_number_of_taps()
211 scl_data->ratios.vert.value--; in dpp201_get_optimal_number_of_taps()
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| H A D | dcn201_dpp.h | 72 struct scaler_data scl_data; member
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn10/ |
| H A D | dcn10_dpp_dscl.c | 280 const struct scaler_data *scl_data, in dpp1_dscl_set_scl_filter() argument
287 uint32_t h_2tap_sharp_factor = scl_data->sharpness.horz; in dpp1_dscl_set_scl_filter()
288 uint32_t v_2tap_sharp_factor = scl_data->sharpness.vert; in dpp1_dscl_set_scl_filter()
295 h_2tap_hardcode_coef_en = scl_data->taps.h_taps < 3 in dpp1_dscl_set_scl_filter()
296 && scl_data->taps.h_taps_c < 3 in dpp1_dscl_set_scl_filter()
297 && (scl_data->taps.h_taps > 1 && scl_data->taps.h_taps_c > 1); in dpp1_dscl_set_scl_filter()
298 v_2tap_hardcode_coef_en = scl_data->taps.v_taps < 3 in dpp1_dscl_set_scl_filter()
299 && scl_data->taps.v_taps_c < 3 in dpp1_dscl_set_scl_filter()
300 && (scl_data->taps.v_taps > 1 && scl_data->taps.v_taps_c > 1); in dpp1_dscl_set_scl_filter()
317 scl_data->taps.h_taps, scl_data->ratios.horz); in dpp1_dscl_set_scl_filter()
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| H A D | dcn10_dpp.c | 126 struct scaler_data *scl_data, in dpp1_get_optimal_number_of_taps() argument
130 if (scl_data->format == PIXEL_FORMAT_FP16 && in dpp1_get_optimal_number_of_taps()
132 scl_data->ratios.horz.value != dc_fixpt_one.value && in dpp1_get_optimal_number_of_taps()
133 scl_data->ratios.vert.value != dc_fixpt_one.value) in dpp1_get_optimal_number_of_taps()
136 if (scl_data->viewport.width > scl_data->h_active && in dpp1_get_optimal_number_of_taps()
138 scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width) in dpp1_get_optimal_number_of_taps()
144 if (scl_data->ratios.horz.value == (4ll << 32)) in dpp1_get_optimal_number_of_taps()
145 scl_data->ratios.horz.value--; in dpp1_get_optimal_number_of_taps()
146 if (scl_data->ratios.vert.value == (4ll << 32)) in dpp1_get_optimal_number_of_taps()
147 scl_data->ratios.vert.value--; in dpp1_get_optimal_number_of_taps()
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn401/ |
| H A D | dcn401_dpp.c | 285 const struct scaler_data *scl_data, in dscl401_calc_lb_num_partitions() argument
293 int line_size = scl_data->viewport.width < scl_data->recout.width ? in dscl401_calc_lb_num_partitions()
294 scl_data->viewport.width : scl_data->recout.width; in dscl401_calc_lb_num_partitions()
295 int line_size_c = scl_data->viewport_c.width < scl_data->recout.width ? in dscl401_calc_lb_num_partitions()
296 scl_data->viewport_c.width : scl_data->recout.width; in dscl401_calc_lb_num_partitions()
317 if (scl_data->viewport.width == scl_data->h_active && in dscl401_calc_lb_num_partitions()
318 scl_data->viewport.height == scl_data->v_active) { in dscl401_calc_lb_num_partitions()
331 if (scl_data->viewport.width == scl_data->h_active && in dscl401_calc_lb_num_partitions()
332 scl_data->viewport.height == scl_data->v_active) { in dscl401_calc_lb_num_partitions()
347 if (scl_data->lb_params.alpha_en in dscl401_calc_lb_num_partitions()
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn20/ |
| H A D | dcn20_dpp.c | 261 const struct scaler_data *scl_data, in dscl2_calc_lb_num_partitions() argument
269 int line_size = scl_data->viewport.width < scl_data->recout.width ? in dscl2_calc_lb_num_partitions()
270 scl_data->viewport.width : scl_data->recout.width; in dscl2_calc_lb_num_partitions()
271 int line_size_c = scl_data->viewport_c.width < scl_data->recout.width ? in dscl2_calc_lb_num_partitions()
272 scl_data->viewport_c.width : scl_data->recout.width; in dscl2_calc_lb_num_partitions()
306 if (scl_data->lb_params.alpha_en in dscl2_calc_lb_num_partitions()
438 const struct spl_scaler_data *scl_data, in dscl2_spl_calc_lb_num_partitions() argument
446 int line_size = scl_data->viewport.width < scl_data->recout.width ? in dscl2_spl_calc_lb_num_partitions()
447 scl_data->viewport.width : scl_data->recout.width; in dscl2_spl_calc_lb_num_partitions()
448 int line_size_c = scl_data->viewport_c.width < scl_data->recout.width ? in dscl2_spl_calc_lb_num_partitions()
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn30/ |
| H A D | dcn30_dpp.c | 440 struct scaler_data *scl_data, in dpp3_get_optimal_number_of_taps() argument
454 if (dc_fixpt_ceil(scl_data->ratios.horz) > 1) in dpp3_get_optimal_number_of_taps()
455 scl_data->taps.h_taps = min(2 * dc_fixpt_ceil(scl_data->ratios.horz), 8); in dpp3_get_optimal_number_of_taps()
457 scl_data->taps.h_taps = 4; in dpp3_get_optimal_number_of_taps()
459 scl_data->taps.h_taps = in_taps->h_taps; in dpp3_get_optimal_number_of_taps()
461 if (dc_fixpt_ceil(scl_data->ratios.vert) > 1) in dpp3_get_optimal_number_of_taps()
462 scl_data->taps.v_taps = min(dc_fixpt_ceil(dc_fixpt_mul_int(scl_data->ratios.vert, 2)), 8); in dpp3_get_optimal_number_of_taps()
464 scl_data->taps.v_taps = 4; in dpp3_get_optimal_number_of_taps()
466 scl_data->taps.v_taps = in_taps->v_taps; in dpp3_get_optimal_number_of_taps()
468 if (dc_fixpt_ceil(scl_data->ratios.vert_c) > 1) in dpp3_get_optimal_number_of_taps()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dce60/ |
| H A D | dce60_hwseq.c | 151 default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format; in dce60_set_default_colors()
158 default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth; in dce60_set_default_colors()
202 switch (pipe_ctx->plane_res.scl_data.format) { in dce60_get_surface_visual_confirm_color()
248 pipe_ctx->plane_res.scl_data.lb_params.depth, in dce60_program_scaler()
266 &pipe_ctx->plane_res.scl_data); in dce60_program_scaler()
312 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; in dce60_program_front_end_for_pipe()
371 pipe_ctx->plane_res.scl_data.viewport.width, in dce60_program_front_end_for_pipe()
372 pipe_ctx->plane_res.scl_data.viewport.height, in dce60_program_front_end_for_pipe()
373 pipe_ctx->plane_res.scl_data.viewport.x, in dce60_program_front_end_for_pipe()
374 pipe_ctx->plane_res.scl_data.viewport.y, in dce60_program_front_end_for_pipe()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/calcs/ |
| H A D | dcn_calcs.c | 341 input->src.viewport_width = pipe->plane_res.scl_data.viewport.width; in pipe_ctx_to_e2e_pipe_params()
342 input->src.viewport_height = pipe->plane_res.scl_data.viewport.height; in pipe_ctx_to_e2e_pipe_params()
343 input->src.data_pitch = pipe->plane_res.scl_data.viewport.width; in pipe_ctx_to_e2e_pipe_params()
344 input->src.data_pitch_c = pipe->plane_res.scl_data.viewport.width; in pipe_ctx_to_e2e_pipe_params()
398 input->scale_taps.htaps = pipe->plane_res.scl_data.taps.h_taps; in pipe_ctx_to_e2e_pipe_params()
399 input->scale_ratio_depth.hscl_ratio = pipe->plane_res.scl_data.ratios.horz.value/4294967296.0; in pipe_ctx_to_e2e_pipe_params()
400 input->scale_ratio_depth.vscl_ratio = pipe->plane_res.scl_data.ratios.vert.value/4294967296.0; in pipe_ctx_to_e2e_pipe_params()
401 input->scale_ratio_depth.vinit = pipe->plane_res.scl_data.inits.v.value/4294967296.0; in pipe_ctx_to_e2e_pipe_params()
404 input->scale_taps.vtaps = pipe->plane_res.scl_data.taps.v_taps; in pipe_ctx_to_e2e_pipe_params()
405 input->scale_taps.vtaps_c = pipe->plane_res.scl_data.taps.v_taps_c; in pipe_ctx_to_e2e_pipe_params()
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| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dce_transform.c | 1170 struct scaler_data *scl_data, in dce_transform_get_optimal_number_of_taps() argument
1174 int pixel_width = scl_data->viewport.width; in dce_transform_get_optimal_number_of_taps()
1178 (scl_data->viewport.width > scl_data->recout.width)) in dce_transform_get_optimal_number_of_taps()
1179 pixel_width = scl_data->recout.width; in dce_transform_get_optimal_number_of_taps()
1183 scl_data->lb_params.depth, in dce_transform_get_optimal_number_of_taps()
1199 scl_data->taps.h_taps = decide_taps(scl_data->ratios.horz, in_taps->h_taps, false); in dce_transform_get_optimal_number_of_taps()
1200 scl_data->taps.v_taps = decide_taps(scl_data->ratios.vert, in_taps->v_taps, false); in dce_transform_get_optimal_number_of_taps()
1201 scl_data->taps.h_taps_c = decide_taps(scl_data->ratios.horz_c, in_taps->h_taps, true); in dce_transform_get_optimal_number_of_taps()
1202 scl_data->taps.v_taps_c = decide_taps(scl_data->ratios.vert_c, in_taps->v_taps, true); in dce_transform_get_optimal_number_of_taps()
1204 if (!IDENTITY_RATIO(scl_data->ratios.vert)) { in dce_transform_get_optimal_number_of_taps()
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc_spl_translate.c | 98 populate_splformat_from_format(&spl_in->basic_in.format, pipe_ctx->plane_res.scl_data.format); in translate_SPL_in_params_from_pipe_ctx()
139 spl_in->basic_out.alpha_en = pipe_ctx->plane_res.scl_data.lb_params.alpha_en; in translate_SPL_in_params_from_pipe_ctx()
199 spl_in->h_active = pipe_ctx->plane_res.scl_data.h_active; in translate_SPL_in_params_from_pipe_ctx()
200 spl_in->v_active = pipe_ctx->plane_res.scl_data.v_active; in translate_SPL_in_params_from_pipe_ctx()
220 populate_rect_from_splrect(&pipe_ctx->plane_res.scl_data.recout, &spl_out->dscl_prog_data->recout); in translate_SPL_out_params_to_pipe_ctx()
222 …populate_ratios_from_splratios(&pipe_ctx->plane_res.scl_data.ratios, &spl_out->dscl_prog_data->rat… in translate_SPL_out_params_to_pipe_ctx()
224 …populate_rect_from_splrect(&pipe_ctx->plane_res.scl_data.viewport, &spl_out->dscl_prog_data->viewp… in translate_SPL_out_params_to_pipe_ctx()
226 …populate_rect_from_splrect(&pipe_ctx->plane_res.scl_data.viewport_c, &spl_out->dscl_prog_data->vie… in translate_SPL_out_params_to_pipe_ctx()
228 populate_taps_from_spltaps(&pipe_ctx->plane_res.scl_data.taps, &spl_out->dscl_prog_data->taps); in translate_SPL_out_params_to_pipe_ctx()
230 populate_inits_from_splinits(&pipe_ctx->plane_res.scl_data.inits, &spl_out->dscl_prog_data->init); in translate_SPL_out_params_to_pipe_ctx()
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_resource.c | 1166 pipe_ctx->plane_res.scl_data.recout = shift_rec( in calculate_recout()
1170 &pipe_ctx->plane_res.scl_data.recout, in calculate_recout()
1174 memset(&pipe_ctx->plane_res.scl_data.recout, 0, in calculate_recout()
1195 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction( in calculate_scaling_ratios()
1198 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction( in calculate_scaling_ratios()
1203 pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2; in calculate_scaling_ratios()
1205 pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2; in calculate_scaling_ratios()
1207 pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64( in calculate_scaling_ratios()
1208 pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h); in calculate_scaling_ratios()
1209 pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64( in calculate_scaling_ratios()
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| /linux/drivers/gpu/drm/amd/display/dc/dce110/ |
| H A D | dce110_transform_v.c | 48 const struct scaler_data *scl_data, in calculate_viewport() argument
53 luma_viewport->x = scl_data->viewport.x - scl_data->viewport.x % 2; in calculate_viewport()
54 luma_viewport->y = scl_data->viewport.y - scl_data->viewport.y % 2; in calculate_viewport()
56 scl_data->viewport.width - scl_data->viewport.width % 2; in calculate_viewport()
58 scl_data->viewport.height - scl_data->viewport.height % 2; in calculate_viewport()
64 if (scl_data->format == PIXEL_FORMAT_420BPP8) { in calculate_viewport()
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| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | transform.h | 173 const struct scaler_data *scl_data);
182 struct scaler_data *scl_data,
286 const struct scaler_data *scl_data,
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| H A D | dpp.h | 246 const struct scaler_data *scl_data);
255 struct scaler_data *scl_data,
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| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm_trace.h | 440 __entry->recout_x = plane_res->scl_data.recout.x;
441 __entry->recout_y = plane_res->scl_data.recout.y;
442 __entry->recout_w = plane_res->scl_data.recout.width;
443 __entry->recout_h = plane_res->scl_data.recout.height;
444 __entry->viewport_x = plane_res->scl_data.viewport.x;
445 __entry->viewport_y = plane_res->scl_data.viewport.y;
446 __entry->viewport_w = plane_res->scl_data.viewport.width;
447 __entry->viewport_h = plane_res->scl_data.viewport.height;
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/ |
| H A D | dml21_translation_helper.c | 482 temp_pipe->plane_res.scl_data.taps = pipe->plane_res.scl_data.taps; in get_scaler_data_for_plane()
493 return &temp_pipe->plane_res.scl_data; in get_scaler_data_for_plane()
887 mcache_pipe_config->plane0.viewport_x_start = pipe_ctx->plane_res.scl_data.viewport.x; in dml21_get_pipe_mcache_config()
888 mcache_pipe_config->plane0.viewport_width = pipe_ctx->plane_res.scl_data.viewport.width; in dml21_get_pipe_mcache_config()
890 mcache_pipe_config->plane1.viewport_x_start = pipe_ctx->plane_res.scl_data.viewport_c.x; in dml21_get_pipe_mcache_config()
891 mcache_pipe_config->plane1.viewport_width = pipe_ctx->plane_res.scl_data.viewport_c.width; in dml21_get_pipe_mcache_config()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/ |
| H A D | dce110_hwseq.c | 1482 pipe_ctx->plane_res.scl_data.lb_params.depth, in program_scaler()
1500 &pipe_ctx->plane_res.scl_data); in program_scaler()
1700 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != NULL; in dce110_apply_single_controller_ctx_to_hw()
2553 default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format; in set_default_colors()
2560 default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth; in set_default_colors()
2951 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != NULL; in dce110_program_front_end_for_pipe()
3010 pipe_ctx->plane_res.scl_data.viewport.width, in dce110_program_front_end_for_pipe()
3011 pipe_ctx->plane_res.scl_data.viewport.height, in dce110_program_front_end_for_pipe()
3012 pipe_ctx->plane_res.scl_data.viewport.x, in dce110_program_front_end_for_pipe()
3013 pipe_ctx->plane_res.scl_data.viewport.y, in dce110_program_front_end_for_pipe()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
| H A D | dcn10_hwseq.c | 2970 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = per_pixel_alpha; in update_scaler()
2971 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_36BPP; in update_scaler()
2974 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data); in update_scaler()
3064 size.surface_size = pipe_ctx->plane_res.scl_data.viewport; in dcn10_update_dchubp_dpp()
3088 &pipe_ctx->plane_res.scl_data.viewport, in dcn10_update_dchubp_dpp()
3089 &pipe_ctx->plane_res.scl_data.viewport_c); in dcn10_update_dchubp_dpp()
3654 .viewport = pipe_ctx->plane_res.scl_data.viewport, in dcn10_set_cursor_position()
3655 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz, in dcn10_set_cursor_position()
3656 .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert, in dcn10_set_cursor_position()
3677 if ((pipe_ctx->plane_state->src_rect.width != pipe_ctx->plane_res.scl_data.viewport.width) || in dcn10_set_cursor_position()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.c | 1089 .viewport = pipe_ctx->plane_res.scl_data.viewport, in dcn401_set_cursor_position()
1090 .recout = pipe_ctx->plane_res.scl_data.recout, in dcn401_set_cursor_position()
1091 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz, in dcn401_set_cursor_position()
1092 .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert, in dcn401_set_cursor_position()
1111 if ((pipe_ctx->plane_state->src_rect.width != pipe_ctx->plane_res.scl_data.viewport.width) || in dcn401_set_cursor_position()
1112 (pipe_ctx->plane_state->src_rect.height != pipe_ctx->plane_res.scl_data.viewport.height)) { in dcn401_set_cursor_position()
1196 bottom_pipe_x_pos = x_pos - pipe_ctx->plane_res.scl_data.recout.x; in dcn401_set_cursor_position()
1198 x_pos = pipe_ctx->plane_res.scl_data.recout.x; in dcn401_set_cursor_position()
2879 …if (memcmp(&old_pipe->plane_res.scl_data, &new_pipe->plane_res.scl_data, sizeof(struct scaler_data… in dcn401_detect_pipe_changes()
2882 …if (memcmp(&old_pipe->plane_res.scl_data.viewport, &new_pipe->plane_res.scl_data.viewport, sizeof(… in dcn401_detect_pipe_changes()
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| /linux/drivers/gpu/drm/amd/display/dc/sspl/ |
| H A D | dc_spl_types.h | 416 struct spl_scaler_data scl_data; member
524 const struct spl_scaler_data *scl_data,
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/ |
| H A D | dml2_utils.c | 273 pipe_ctx->pipe_dlg_param.recout_height = pipe_ctx->plane_res.scl_data.recout.height; in populate_pipe_ctx_dlg_params_from_dml()
274 pipe_ctx->pipe_dlg_param.recout_width = pipe_ctx->plane_res.scl_data.recout.width; in populate_pipe_ctx_dlg_params_from_dml()
275 pipe_ctx->pipe_dlg_param.full_recout_height = pipe_ctx->plane_res.scl_data.recout.height; in populate_pipe_ctx_dlg_params_from_dml()
276 pipe_ctx->pipe_dlg_param.full_recout_width = pipe_ctx->plane_res.scl_data.recout.width; in populate_pipe_ctx_dlg_params_from_dml()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| H A D | dcn20_hwseq.c | 1594 …if (memcmp(&old_pipe->plane_res.scl_data, &new_pipe->plane_res.scl_data, sizeof(struct scaler_data… in dcn20_detect_pipe_changes()
1597 …if (memcmp(&old_pipe->plane_res.scl_data.viewport, &new_pipe->plane_res.scl_data.viewport, sizeof(… in dcn20_detect_pipe_changes()
1598 || memcmp(&old_pipe->plane_res.scl_data.viewport_c, in dcn20_detect_pipe_changes()
1599 &new_pipe->plane_res.scl_data.viewport_c, sizeof(struct rect))) in dcn20_detect_pipe_changes()
1763 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha; in dcn20_update_dchubp_dpp()
1764 ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_36BPP); in dcn20_update_dchubp_dpp()
1767 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data); in dcn20_update_dchubp_dpp()
1777 &pipe_ctx->plane_res.scl_data.viewport, in dcn20_update_dchubp_dpp()
1778 &pipe_ctx->plane_res.scl_data.viewport_c); in dcn20_update_dchubp_dpp()
1830 size.surface_size = pipe_ctx->plane_res.scl_data.viewport; in dcn20_update_dchubp_dpp()
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