| /linux/drivers/gpu/drm/amd/display/dc/hubbub/dcn32/ |
| H A D | dcn32_hubbub.c | 181 bool safe_to_lower) in hubbub32_program_urgent_watermarks() argument
189 if (safe_to_lower || watermarks->a.urgent_ns > hubbub2->watermarks.a.urgent_ns) { in hubbub32_program_urgent_watermarks()
203 if (safe_to_lower || watermarks->a.frac_urg_bw_flip in hubbub32_program_urgent_watermarks()
213 if (safe_to_lower || watermarks->a.frac_urg_bw_nom in hubbub32_program_urgent_watermarks()
223 if (safe_to_lower || watermarks->a.urgent_latency_ns > hubbub2->watermarks.a.urgent_latency_ns) { in hubbub32_program_urgent_watermarks()
233 if (safe_to_lower || watermarks->b.urgent_ns > hubbub2->watermarks.b.urgent_ns) { in hubbub32_program_urgent_watermarks()
247 if (safe_to_lower || watermarks->b.frac_urg_bw_flip in hubbub32_program_urgent_watermarks()
257 if (safe_to_lower || watermarks->b.frac_urg_bw_nom in hubbub32_program_urgent_watermarks()
267 if (safe_to_lower || watermarks->b.urgent_latency_ns > hubbub2->watermarks.b.urgent_latency_ns) { in hubbub32_program_urgent_watermarks()
277 if (safe_to_lower || watermarks->c.urgent_ns > hubbub2->watermarks.c.urgent_ns) { in hubbub32_program_urgent_watermarks()
[all …]
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| H A D | dcn32_hubbub.h | 123 bool safe_to_lower);
129 bool safe_to_lower);
135 bool safe_to_lower);
141 bool safe_to_lower);
|
| /linux/drivers/gpu/drm/amd/display/dc/hubbub/dcn21/ |
| H A D | dcn21_hubbub.c | 145 bool safe_to_lower) in hubbub21_program_urgent_watermarks() argument
153 if (safe_to_lower || watermarks->a.urgent_ns > hubbub1->watermarks.a.urgent_ns) { in hubbub21_program_urgent_watermarks()
168 if (safe_to_lower || watermarks->a.frac_urg_bw_flip in hubbub21_program_urgent_watermarks()
178 if (safe_to_lower || watermarks->a.frac_urg_bw_nom in hubbub21_program_urgent_watermarks()
188 if (safe_to_lower || watermarks->a.urgent_latency_ns > hubbub1->watermarks.a.urgent_latency_ns) { in hubbub21_program_urgent_watermarks()
198 if (safe_to_lower || watermarks->b.urgent_ns > hubbub1->watermarks.b.urgent_ns) { in hubbub21_program_urgent_watermarks()
213 if (safe_to_lower || watermarks->a.frac_urg_bw_flip in hubbub21_program_urgent_watermarks()
223 if (safe_to_lower || watermarks->a.frac_urg_bw_nom in hubbub21_program_urgent_watermarks()
233 if (safe_to_lower || watermarks->b.urgent_latency_ns > hubbub1->watermarks.b.urgent_latency_ns) { in hubbub21_program_urgent_watermarks()
243 if (safe_to_lower || watermarks->c.urgent_ns > hubbub1->watermarks.c.urgent_ns) { in hubbub21_program_urgent_watermarks()
[all …]
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| H A D | dcn21_hubbub.h | 132 bool safe_to_lower);
137 bool safe_to_lower);
142 bool safe_to_lower);
147 bool safe_to_lower);
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/ |
| H A D | dcn201_clk_mgr.c | 86 bool safe_to_lower) in dcn201_update_clocks() argument
116 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) in dcn201_update_clocks()
123 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) in dcn201_update_clocks()
126 if (should_set_clock(safe_to_lower, in dcn201_update_clocks()
130 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz)) in dcn201_update_clocks()
135 …if (should_update_pstate_support(safe_to_lower, p_state_change_support, clk_mgr_base->clks.p_state… in dcn201_update_clocks()
140 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) in dcn201_update_clocks()
143 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { in dcn201_update_clocks()
151 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { in dcn201_update_clocks()
157 if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) { in dcn201_update_clocks()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/hubbub/dcn31/ |
| H A D | dcn31_hubbub.c | 177 bool safe_to_lower) in hubbub31_program_urgent_watermarks() argument
185 if (safe_to_lower || watermarks->a.urgent_ns > hubbub2->watermarks.a.urgent_ns) { in hubbub31_program_urgent_watermarks()
199 if (safe_to_lower || watermarks->a.frac_urg_bw_flip in hubbub31_program_urgent_watermarks()
209 if (safe_to_lower || watermarks->a.frac_urg_bw_nom in hubbub31_program_urgent_watermarks()
219 if (safe_to_lower || watermarks->a.urgent_latency_ns > hubbub2->watermarks.a.urgent_latency_ns) { in hubbub31_program_urgent_watermarks()
229 if (safe_to_lower || watermarks->b.urgent_ns > hubbub2->watermarks.b.urgent_ns) { in hubbub31_program_urgent_watermarks()
243 if (safe_to_lower || watermarks->b.frac_urg_bw_flip in hubbub31_program_urgent_watermarks()
253 if (safe_to_lower || watermarks->b.frac_urg_bw_nom in hubbub31_program_urgent_watermarks()
263 if (safe_to_lower || watermarks->b.urgent_latency_ns > hubbub2->watermarks.b.urgent_latency_ns) { in hubbub31_program_urgent_watermarks()
273 if (safe_to_lower || watermarks->c.urgent_ns > hubbub2->watermarks.c.urgent_ns) { in hubbub31_program_urgent_watermarks()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| H A D | dcn20_clk_mgr.c | 105 struct dc_state *context, bool safe_to_lower) in dcn20_update_clocks_update_dpp_dto() argument
121 if (safe_to_lower || prev_dppclk_khz < dppclk_khz) in dcn20_update_clocks_update_dpp_dto()
218 bool safe_to_lower) in dcn2_update_clocks() argument
253 if (enter_display_off == safe_to_lower) { in dcn2_update_clocks()
262 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { in dcn2_update_clocks()
268 if (should_set_clock(safe_to_lower, in dcn2_update_clocks()
275 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz)) { in dcn2_update_clocks()
283 …if (should_update_pstate_support(safe_to_lower, p_state_change_support, clk_mgr_base->clks.p_state… in dcn2_update_clocks()
290 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) { in dcn2_update_clocks()
296 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { in dcn2_update_clocks()
[all …]
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| H A D | dcn20_clk_mgr.h | 31 bool safe_to_lower);
35 bool safe_to_lower);
37 struct dc_state *context, bool safe_to_lower);
|
| /linux/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/ |
| H A D | dcn401_hubbub.c | 71 bool safe_to_lower) in hubbub401_program_urgent_watermarks() argument
78 if (safe_to_lower || watermarks->dcn4x.a.urgent > hubbub2->watermarks.dcn4x.a.urgent) { in hubbub401_program_urgent_watermarks()
89 if (safe_to_lower || watermarks->dcn4x.a.frac_urg_bw_flip in hubbub401_program_urgent_watermarks()
98 if (safe_to_lower || watermarks->dcn4x.a.frac_urg_bw_nom in hubbub401_program_urgent_watermarks()
107 if (safe_to_lower || watermarks->dcn4x.a.frac_urg_bw_mall in hubbub401_program_urgent_watermarks()
115 …if (safe_to_lower || watermarks->dcn4x.a.refcyc_per_trip_to_mem > hubbub2->watermarks.dcn4x.a.refc… in hubbub401_program_urgent_watermarks()
122 …if (safe_to_lower || watermarks->dcn4x.a.refcyc_per_meta_trip_to_mem > hubbub2->watermarks.dcn4x.a… in hubbub401_program_urgent_watermarks()
131 if (safe_to_lower || watermarks->dcn4x.b.urgent > hubbub2->watermarks.dcn4x.b.urgent) { in hubbub401_program_urgent_watermarks()
142 if (safe_to_lower || watermarks->dcn4x.b.frac_urg_bw_flip in hubbub401_program_urgent_watermarks()
151 if (safe_to_lower || watermarks->dcn4x.b.frac_urg_bw_nom in hubbub401_program_urgent_watermarks()
[all …]
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| H A D | dcn401_hubbub.h | 142 bool safe_to_lower);
148 bool safe_to_lower);
154 bool safe_to_lower);
160 bool safe_to_lower);
200 bool safe_to_lower);
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/ |
| H A D | rv1_clk_mgr.c | 89 bool safe_to_lower) in ramp_up_dispclk_with_dpp() argument
153 if (!safe_to_lower) in ramp_up_dispclk_with_dpp()
189 bool safe_to_lower) in rv1_update_clocks() argument
214 if (enter_display_off == safe_to_lower) { in rv1_update_clocks()
230 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) { in rv1_update_clocks()
239 if (should_set_clock(safe_to_lower, new_clocks->fclk_khz, clk_mgr_base->clks.fclk_khz)) { in rv1_update_clocks()
245 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { in rv1_update_clocks()
250 if (should_set_clock(safe_to_lower, in rv1_update_clocks()
272 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz) in rv1_update_clocks()
274 ramp_up_dispclk_with_dpp(clk_mgr, dc, new_clocks, safe_to_lower); in rv1_update_clocks()
|
| /linux/drivers/gpu/drm/amd/display/dc/hubbub/dcn35/ |
| H A D | dcn35_hubbub.c | 116 bool safe_to_lower) in hubbub35_program_stutter_z8_watermarks() argument
139 if (safe_to_lower || watermarks->a.cstate_pstate.cstate_exit_z8_ns in hubbub35_program_stutter_z8_watermarks()
157 if (safe_to_lower || watermarks->b.cstate_pstate.cstate_enter_plus_exit_z8_ns in hubbub35_program_stutter_z8_watermarks()
173 if (safe_to_lower || watermarks->b.cstate_pstate.cstate_exit_z8_ns in hubbub35_program_stutter_z8_watermarks()
190 if (safe_to_lower || watermarks->c.cstate_pstate.cstate_enter_plus_exit_z8_ns in hubbub35_program_stutter_z8_watermarks()
206 if (safe_to_lower || watermarks->c.cstate_pstate.cstate_exit_z8_ns in hubbub35_program_stutter_z8_watermarks()
223 if (safe_to_lower || watermarks->d.cstate_pstate.cstate_enter_plus_exit_z8_ns in hubbub35_program_stutter_z8_watermarks()
239 if (safe_to_lower || watermarks->d.cstate_pstate.cstate_exit_z8_ns in hubbub35_program_stutter_z8_watermarks()
302 bool safe_to_lower) in hubbub35_program_watermarks() argument
307 if (hubbub32_program_urgent_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower)) in hubbub35_program_watermarks()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| H A D | dcn30_clk_mgr.c | 195 bool safe_to_lower) in dcn3_update_clocks() argument
228 if (enter_display_off == safe_to_lower) in dcn3_update_clocks()
235 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { in dcn3_update_clocks()
240 …if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_d… in dcn3_update_clocks()
245 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz)) in dcn3_update_clocks()
253 if (dc->clk_mgr->dc_mode_softmax_enabled && safe_to_lower && !p_state_change_support) { in dcn3_update_clocks()
259 …if (should_update_pstate_support(safe_to_lower, p_state_change_support, clk_mgr_base->clks.p_state… in dcn3_update_clocks()
276 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) { in dcn3_update_clocks()
286 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) { in dcn3_update_clocks()
295 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { in dcn3_update_clocks()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/ |
| H A D | dcn401_clk_mgr.c | 557 struct dc_state *context, bool safe_to_lower, int ref_dppclk_khz) in dcn401_update_clocks_update_dpp_dto() argument
584 if (safe_to_lower || prev_dppclk_khz < dppclk_khz) in dcn401_update_clocks_update_dpp_dto()
737 params->update_dppclk_dto_params.safe_to_lower, in dcn401_execute_block_sequence()
768 bool safe_to_lower) in dcn401_build_update_bandwidth_clocks_sequence() argument
807 if (enter_display_off == safe_to_lower) { in dcn401_build_update_bandwidth_clocks_sequence()
817 …if (should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fc… in dcn401_build_update_bandwidth_clocks_sequence()
845 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { in dcn401_build_update_bandwidth_clocks_sequence()
857 …if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_d… in dcn401_build_update_bandwidth_clocks_sequence()
867 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz)) in dcn401_build_update_bandwidth_clocks_sequence()
901 …if (should_update_pstate_support(safe_to_lower, uclk_p_state_change_support, clk_mgr_base->clks.pr… in dcn401_build_update_bandwidth_clocks_sequence()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| H A D | dcn316_clk_mgr.c | 103 bool safe_to_lower, bool disable) in dcn316_disable_otg_wa() argument
109 struct pipe_ctx *pipe = safe_to_lower in dcn316_disable_otg_wa()
137 bool safe_to_lower) in dcn316_update_clocks() argument
156 if (safe_to_lower) { in dcn316_update_clocks()
190 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { in dcn316_update_clocks()
195 if (should_set_clock(safe_to_lower, in dcn316_update_clocks()
205 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { in dcn316_update_clocks()
212 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz) && in dcn316_update_clocks()
213 (new_clocks->dispclk_khz > 0 || (safe_to_lower && display_count == 0))) { in dcn316_update_clocks()
216 dcn316_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true); in dcn316_update_clocks()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| H A D | dcn35_clk_mgr.c | 190 bool safe_to_lower, bool disable) in dcn35_disable_otg_wa() argument
203 struct pipe_ctx *pipe = safe_to_lower in dcn35_disable_otg_wa()
281 struct dc_state *context, bool safe_to_lower) in dcn35_update_clocks_update_dpp_dto() argument
310 if (safe_to_lower || prev_dppclk_khz < dppclk_khz) in dcn35_update_clocks_update_dpp_dto()
315 if (safe_to_lower) in dcn35_update_clocks_update_dpp_dto()
342 bool safe_to_lower) in dcn35_notify_host_router_bw() argument
370 …if (should_set_clock(safe_to_lower, new_clocks->host_router_bw_kbps[i], clk_mgr_base->clks.host_ro… in dcn35_notify_host_router_bw()
379 bool safe_to_lower) in dcn35_update_clocks() argument
404 if (safe_to_lower) { in dcn35_update_clocks()
457 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { in dcn35_update_clocks()
[all …]
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| H A D | dcn35_clk_mgr.h | 54 bool safe_to_lower);
70 bool safe_to_lower,
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| H A D | dcn32_clk_mgr.c | 315 struct dc_state *context, bool safe_to_lower) in dcn32_update_clocks_update_dpp_dto() argument
342 if (safe_to_lower || prev_dppclk_khz < dppclk_khz) in dcn32_update_clocks_update_dpp_dto()
623 bool safe_to_lower) in dcn32_update_clocks() argument
658 if (enter_display_off == safe_to_lower) in dcn32_update_clocks()
665 …if (should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fc… in dcn32_update_clocks()
680 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz) && in dcn32_update_clocks()
686 …if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_d… in dcn32_update_clocks()
692 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz)) in dcn32_update_clocks()
706 …if (should_update_pstate_support(safe_to_lower, p_state_change_support, clk_mgr_base->clks.p_state… in dcn32_update_clocks()
735 …if (safe_to_lower && (clk_mgr_base->clks.fclk_p_state_change_support != clk_mgr_base->clks.fclk_pr… in dcn32_update_clocks()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/hubbub/dcn201/ |
| H A D | dcn201_hubbub.c | 57 bool safe_to_lower) in hubbub201_program_watermarks() argument
62 if (hubbub1_program_urgent_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower)) in hubbub201_program_watermarks()
65 if (hubbub1_program_pstate_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower)) in hubbub201_program_watermarks()
|
| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dce_clk_mgr.c | 674 bool safe_to_lower) in dce_update_clocks() argument
686 if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower) in dce_update_clocks()
692 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr->clks.dispclk_khz)) { in dce_update_clocks()
701 bool safe_to_lower) in dce11_update_clocks() argument
713 if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower) in dce11_update_clocks()
719 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr->clks.dispclk_khz)) { in dce11_update_clocks()
728 bool safe_to_lower) in dce112_update_clocks() argument
740 if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower) in dce112_update_clocks()
746 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr->clks.dispclk_khz)) { in dce112_update_clocks()
755 bool safe_to_lower) in dce12_update_clocks() argument
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| H A D | rn_clk_mgr.c | 107 struct dc_state *context, int ref_dpp_clk, bool safe_to_lower) in rn_update_clocks_update_dpp_dto() argument
124 if (safe_to_lower || prev_dppclk_khz < dppclk_khz) in rn_update_clocks_update_dpp_dto()
133 bool safe_to_lower) in rn_update_clocks() argument
152 if (safe_to_lower && !dc->debug.disable_48mhz_pwrdwn) { in rn_update_clocks()
174 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { in rn_update_clocks()
179 if (should_set_clock(safe_to_lower, in rn_update_clocks()
199 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) { in rn_update_clocks()
206 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { in rn_update_clocks()
219 safe_to_lower); in rn_update_clocks()
229 safe_to_lower); in rn_update_clocks()
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/ |
| H A D | dce120_clk_mgr.c | 86 bool safe_to_lower) in dce12_update_clocks() argument
97 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) { in dce12_update_clocks()
112 if (should_set_clock(safe_to_lower, max_pix_clk, clk_mgr_base->clks.phyclk_khz)) { in dce12_update_clocks()
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/ |
| H A D | dce60_clk_mgr.c | 111 bool safe_to_lower) in dce60_update_clocks() argument
121 if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower) in dce60_update_clocks()
127 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) { in dce60_update_clocks()
|
| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | clk_mgr_internal.h | 437 static inline bool should_set_clock(bool safe_to_lower, int calc_clk, int cur_clk) in should_set_clock() argument
439 return ((safe_to_lower && calc_clk < cur_clk) || calc_clk > cur_clk); in should_set_clock()
442 static inline bool should_update_pstate_support(bool safe_to_lower, bool calc_support, bool cur_sup… in should_update_pstate_support() argument
445 if (calc_support && safe_to_lower) in should_update_pstate_support()
447 else if (!calc_support && !safe_to_lower) in should_update_pstate_support()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| H A D | vg_clk_mgr.c | 97 bool safe_to_lower) in vg_update_clocks() argument
114 if (safe_to_lower) { in vg_update_clocks()
142 …if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz) && !dc-… in vg_update_clocks()
147 if (should_set_clock(safe_to_lower, in vg_update_clocks()
157 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { in vg_update_clocks()
164 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { in vg_update_clocks()
173 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); in vg_update_clocks()
180 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); in vg_update_clocks()
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