1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2 /*
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
5 */
6
7 #ifndef ATH12K_CORE_H
8 #define ATH12K_CORE_H
9
10 #include <linux/types.h>
11 #include <linux/interrupt.h>
12 #include <linux/irq.h>
13 #include <linux/bitfield.h>
14 #include <linux/dmi.h>
15 #include <linux/ctype.h>
16 #include <linux/firmware.h>
17 #include <linux/of_reserved_mem.h>
18 #include <linux/panic_notifier.h>
19 #include <linux/average.h>
20 #include <linux/of.h>
21 #include <linux/rhashtable.h>
22 #include "qmi.h"
23 #include "htc.h"
24 #include "wmi.h"
25 #include "hal.h"
26 #include "dp.h"
27 #include "ce.h"
28 #include "mac.h"
29 #include "hw.h"
30 #include "reg.h"
31 #include "dbring.h"
32 #include "fw.h"
33 #include "acpi.h"
34 #include "wow.h"
35 #include "debugfs_htt_stats.h"
36 #include "coredump.h"
37 #include "cmn_defs.h"
38 #include "dp_cmn.h"
39
40 #define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK)
41
42 #define ATH12K_TX_MGMT_NUM_PENDING_MAX 512
43
44 #define ATH12K_TX_MGMT_TARGET_MAX_SUPPORT_WMI 64
45
46 /* Pending management packets threshold for dropping probe responses */
47 #define ATH12K_PRB_RSP_DROP_THRESHOLD ((ATH12K_TX_MGMT_TARGET_MAX_SUPPORT_WMI * 3) / 4)
48
49 /* SMBIOS type containing Board Data File Name Extension */
50 #define ATH12K_SMBIOS_BDF_EXT_TYPE 0xF8
51
52 /* SMBIOS type structure length (excluding strings-set) */
53 #define ATH12K_SMBIOS_BDF_EXT_LENGTH 0x9
54
55 /* The magic used by QCA spec */
56 #define ATH12K_SMBIOS_BDF_EXT_MAGIC "BDF_"
57
58 #define ATH12K_INVALID_HW_MAC_ID 0xFF
59 #define ATH12K_CONNECTION_LOSS_HZ (3 * HZ)
60
61 #define ATH12K_MON_TIMER_INTERVAL 10
62 #define ATH12K_RESET_TIMEOUT_HZ (20 * HZ)
63 #define ATH12K_RESET_MAX_FAIL_COUNT_FIRST 3
64 #define ATH12K_RESET_MAX_FAIL_COUNT_FINAL 5
65 #define ATH12K_RESET_FAIL_TIMEOUT_HZ (20 * HZ)
66 #define ATH12K_RECONFIGURE_TIMEOUT_HZ (10 * HZ)
67 #define ATH12K_RECOVER_START_TIMEOUT_HZ (20 * HZ)
68
69 #define ATH12K_INVALID_GROUP_ID 0xFF
70 #define ATH12K_INVALID_DEVICE_ID 0xFF
71
72 #define ATH12K_MAX_MLO_PEERS 256
73 #define ATH12K_MLO_PEER_ID_INVALID 0xFFFF
74
75 #define ATH12K_INVALID_RSSI_FULL -1
76 #define ATH12K_INVALID_RSSI_EMPTY -128
77
78 enum ath12k_bdf_search {
79 ATH12K_BDF_SEARCH_DEFAULT,
80 ATH12K_BDF_SEARCH_BUS_AND_BOARD,
81 };
82
83 enum wme_ac {
84 WME_AC_BE,
85 WME_AC_BK,
86 WME_AC_VI,
87 WME_AC_VO,
88 WME_NUM_AC
89 };
90
91 #define ATH12K_HT_MCS_MAX 7
92 #define ATH12K_VHT_MCS_MAX 9
93 #define ATH12K_HE_MCS_MAX 11
94 #define ATH12K_EHT_MCS_MAX 15
95
96 enum ath12k_crypt_mode {
97 /* Only use hardware crypto engine */
98 ATH12K_CRYPT_MODE_HW,
99 /* Only use software crypto */
100 ATH12K_CRYPT_MODE_SW,
101 };
102
ath12k_tid_to_ac(u32 tid)103 static inline enum wme_ac ath12k_tid_to_ac(u32 tid)
104 {
105 return (((tid == 0) || (tid == 3)) ? WME_AC_BE :
106 ((tid == 1) || (tid == 2)) ? WME_AC_BK :
107 ((tid == 4) || (tid == 5)) ? WME_AC_VI :
108 WME_AC_VO);
109 }
110
ath12k_le32hilo_to_u64(__le32 hi,__le32 lo)111 static inline u64 ath12k_le32hilo_to_u64(__le32 hi, __le32 lo)
112 {
113 u64 hi64 = le32_to_cpu(hi);
114 u64 lo64 = le32_to_cpu(lo);
115
116 return (hi64 << 32) | lo64;
117 }
118
119 enum ath12k_skb_flags {
120 ATH12K_SKB_HW_80211_ENCAP = BIT(0),
121 ATH12K_SKB_CIPHER_SET = BIT(1),
122 ATH12K_SKB_MLO_STA = BIT(2),
123 };
124
125 struct ath12k_skb_cb {
126 dma_addr_t paddr;
127 struct ath12k *ar;
128 struct ieee80211_vif *vif;
129 dma_addr_t paddr_ext_desc;
130 u32 cipher;
131 u8 flags;
132 u8 link_id;
133 };
134
135 struct ath12k_skb_rxcb {
136 dma_addr_t paddr;
137 bool is_first_msdu;
138 bool is_last_msdu;
139 bool is_continuation;
140 bool is_mcbc;
141 bool is_eapol;
142 struct hal_rx_desc *rx_desc;
143 u8 err_rel_src;
144 u8 err_code;
145 u8 hw_link_id;
146 u8 unmapped;
147 u8 is_frag;
148 u8 tid;
149 u16 peer_id;
150 bool is_end_of_ppdu;
151 };
152
153 enum ath12k_hw_rev {
154 ATH12K_HW_QCN9274_HW10,
155 ATH12K_HW_QCN9274_HW20,
156 ATH12K_HW_WCN7850_HW20,
157 ATH12K_HW_IPQ5332_HW10,
158 ATH12K_HW_QCC2072_HW10,
159 };
160
161 enum ath12k_firmware_mode {
162 /* the default mode, standard 802.11 functionality */
163 ATH12K_FIRMWARE_MODE_NORMAL,
164
165 /* factory tests etc */
166 ATH12K_FIRMWARE_MODE_FTM,
167 };
168
169 #define ATH12K_IRQ_NUM_MAX 57
170 #define ATH12K_EXT_IRQ_NUM_MAX 16
171 #define ATH12K_MAX_TCL_RING_NUM 3
172
173 struct ath12k_ext_irq_grp {
174 struct ath12k_base *ab;
175 u32 irqs[ATH12K_EXT_IRQ_NUM_MAX];
176 u32 num_irq;
177 u32 grp_id;
178 u64 timestamp;
179 bool napi_enabled;
180 struct napi_struct napi;
181 struct net_device *napi_ndev;
182 };
183
184 enum ath12k_smbios_cc_type {
185 /* disable country code setting from SMBIOS */
186 ATH12K_SMBIOS_CC_DISABLE = 0,
187
188 /* set country code by ANSI country name, based on ISO3166-1 alpha2 */
189 ATH12K_SMBIOS_CC_ISO = 1,
190
191 /* worldwide regdomain */
192 ATH12K_SMBIOS_CC_WW = 2,
193 };
194
195 struct ath12k_smbios_bdf {
196 struct dmi_header hdr;
197 u8 features_disabled;
198
199 /* enum ath12k_smbios_cc_type */
200 u8 country_code_flag;
201
202 /* To set specific country, you need to set country code
203 * flag=ATH12K_SMBIOS_CC_ISO first, then if country is United
204 * States, then country code value = 0x5553 ("US",'U' = 0x55, 'S'=
205 * 0x53). To set country to INDONESIA, then country code value =
206 * 0x4944 ("IN", 'I'=0x49, 'D'=0x44). If country code flag =
207 * ATH12K_SMBIOS_CC_WW, then you can use worldwide regulatory
208 * setting.
209 */
210 u16 cc_code;
211
212 u8 bdf_enabled;
213 u8 bdf_ext[];
214 } __packed;
215
216 #define HEHANDLE_CAP_PHYINFO_SIZE 3
217 #define HECAP_PHYINFO_SIZE 9
218 #define HECAP_MACINFO_SIZE 5
219 #define HECAP_TXRX_MCS_NSS_SIZE 2
220 #define HECAP_PPET16_PPET8_MAX_SIZE 25
221
222 #define HE_PPET16_PPET8_SIZE 8
223
224 /* 802.11ax PPE (PPDU packet Extension) threshold */
225 struct he_ppe_threshold {
226 u32 numss_m1;
227 u32 ru_mask;
228 u32 ppet16_ppet8_ru3_ru0[HE_PPET16_PPET8_SIZE];
229 };
230
231 struct ath12k_he {
232 u8 hecap_macinfo[HECAP_MACINFO_SIZE];
233 u32 hecap_rxmcsnssmap;
234 u32 hecap_txmcsnssmap;
235 u32 hecap_phyinfo[HEHANDLE_CAP_PHYINFO_SIZE];
236 struct he_ppe_threshold hecap_ppet;
237 u32 heop_param;
238 };
239
240 enum {
241 WMI_HOST_TP_SCALE_MAX = 0,
242 WMI_HOST_TP_SCALE_50 = 1,
243 WMI_HOST_TP_SCALE_25 = 2,
244 WMI_HOST_TP_SCALE_12 = 3,
245 WMI_HOST_TP_SCALE_MIN = 4,
246 WMI_HOST_TP_SCALE_SIZE = 5,
247 };
248
249 enum ath12k_scan_state {
250 ATH12K_SCAN_IDLE,
251 ATH12K_SCAN_STARTING,
252 ATH12K_SCAN_RUNNING,
253 ATH12K_SCAN_ABORTING,
254 };
255
256 enum ath12k_11d_state {
257 ATH12K_11D_IDLE,
258 ATH12K_11D_PREPARING,
259 ATH12K_11D_RUNNING,
260 };
261
262 enum ath12k_hw_group_flags {
263 ATH12K_GROUP_FLAG_REGISTERED,
264 ATH12K_GROUP_FLAG_UNREGISTER,
265 };
266
267 enum ath12k_dev_flags {
268 ATH12K_FLAG_CAC_RUNNING,
269 ATH12K_FLAG_CRASH_FLUSH,
270 ATH12K_FLAG_RAW_MODE,
271 ATH12K_FLAG_HW_CRYPTO_DISABLED,
272 ATH12K_FLAG_RECOVERY,
273 ATH12K_FLAG_UNREGISTERING,
274 ATH12K_FLAG_REGISTERED,
275 ATH12K_FLAG_QMI_FAIL,
276 ATH12K_FLAG_HTC_SUSPEND_COMPLETE,
277 ATH12K_FLAG_CE_IRQ_ENABLED,
278 ATH12K_FLAG_EXT_IRQ_ENABLED,
279 ATH12K_FLAG_QMI_FW_READY_COMPLETE,
280 ATH12K_FLAG_FTM_SEGMENTED,
281 ATH12K_FLAG_FIXED_MEM_REGION,
282 };
283
284 struct ath12k_tx_conf {
285 bool changed;
286 u16 ac;
287 struct ieee80211_tx_queue_params tx_queue_params;
288 };
289
290 struct ath12k_key_conf {
291 enum set_key_cmd cmd;
292 struct list_head list;
293 struct ieee80211_sta *sta;
294 struct ieee80211_key_conf *key;
295 };
296
297 struct ath12k_vif_cache {
298 struct ath12k_tx_conf tx_conf;
299 struct ath12k_key_conf key_conf;
300 u32 bss_conf_changed;
301 };
302
303 struct ath12k_rekey_data {
304 u8 kck[NL80211_KCK_LEN];
305 u8 kek[NL80211_KCK_LEN];
306 u64 replay_ctr;
307 bool enable_offload;
308 };
309
310 struct ath12k_link_vif {
311 u32 vdev_id;
312 u32 beacon_interval;
313 u32 dtim_period;
314
315 struct ath12k *ar;
316
317 bool beacon_prot;
318
319 struct wmi_wmm_params_all_arg wmm_params;
320 struct list_head list;
321
322 bool is_created;
323 bool is_started;
324 bool is_up;
325 u8 bssid[ETH_ALEN];
326 struct cfg80211_bitrate_mask bitrate_mask;
327 struct delayed_work connection_loss_work;
328 int num_legacy_stations;
329 int rtscts_prot_mode;
330 int txpower;
331 bool rsnie_present;
332 bool wpaie_present;
333 u8 vdev_stats_id;
334 u32 punct_bitmap;
335 u8 link_id;
336 struct ath12k_vif *ahvif;
337 struct ath12k_rekey_data rekey_data;
338 struct ath12k_link_stats link_stats;
339 spinlock_t link_stats_lock; /* Protects updates to link_stats */
340
341 u8 current_cntdown_counter;
342
343 /* only used in station mode */
344 bool is_sta_assoc_link;
345
346 struct ath12k_reg_tpc_power_info reg_tpc_info;
347
348 bool group_key_valid;
349 struct wmi_vdev_install_key_arg group_key;
350 bool pairwise_key_done;
351 u16 num_stations;
352 bool is_csa_in_progress;
353 struct wiphy_work bcn_tx_work;
354 };
355
356 struct ath12k_vif {
357 struct ath12k_dp_vif dp_vif;
358
359 enum wmi_vdev_type vdev_type;
360 enum wmi_vdev_subtype vdev_subtype;
361 struct ieee80211_vif *vif;
362 struct ath12k_hw *ah;
363
364 union {
365 struct {
366 u32 uapsd;
367 } sta;
368 struct {
369 /* 127 stations; wmi limit */
370 u8 tim_bitmap[16];
371 u8 tim_len;
372 u32 ssid_len;
373 u8 ssid[IEEE80211_MAX_SSID_LEN];
374 bool hidden_ssid;
375 /* P2P_IE with NoA attribute for P2P_GO case */
376 u32 noa_len;
377 u8 *noa_data;
378 } ap;
379 } u;
380
381 u32 aid;
382 bool ps;
383
384 struct ath12k_link_vif deflink;
385 struct ath12k_link_vif __rcu *link[ATH12K_NUM_MAX_LINKS];
386 struct ath12k_vif_cache *cache[IEEE80211_MLD_MAX_NUM_LINKS];
387 /* indicates bitmap of link vif created in FW */
388 u32 links_map;
389 /* Must be last - ends in a flexible-array member.
390 *
391 * FIXME: Driver should not copy struct ieee80211_chanctx_conf,
392 * especially because it has a flexible array. Find a better way.
393 */
394 struct ieee80211_chanctx_conf chanctx;
395 };
396
397 struct ath12k_vif_iter {
398 u32 vdev_id;
399 struct ath12k *ar;
400 struct ath12k_link_vif *arvif;
401 };
402
403 #define ATH12K_SCAN_TIMEOUT_HZ (20 * HZ)
404
405 #define ATH12K_HE_MCS_NUM 12
406 #define ATH12K_VHT_MCS_NUM 10
407 #define ATH12K_BW_NUM 5
408 #define ATH12K_NSS_NUM 4
409 #define ATH12K_LEGACY_NUM 12
410 #define ATH12K_GI_NUM 4
411 #define ATH12K_HT_MCS_NUM 32
412
413 enum ath12k_pkt_rx_err {
414 ATH12K_PKT_RX_ERR_FCS,
415 ATH12K_PKT_RX_ERR_TKIP,
416 ATH12K_PKT_RX_ERR_CRYPT,
417 ATH12K_PKT_RX_ERR_PEER_IDX_INVAL,
418 ATH12K_PKT_RX_ERR_MAX,
419 };
420
421 enum ath12k_ampdu_subfrm_num {
422 ATH12K_AMPDU_SUBFRM_NUM_10,
423 ATH12K_AMPDU_SUBFRM_NUM_20,
424 ATH12K_AMPDU_SUBFRM_NUM_30,
425 ATH12K_AMPDU_SUBFRM_NUM_40,
426 ATH12K_AMPDU_SUBFRM_NUM_50,
427 ATH12K_AMPDU_SUBFRM_NUM_60,
428 ATH12K_AMPDU_SUBFRM_NUM_MORE,
429 ATH12K_AMPDU_SUBFRM_NUM_MAX,
430 };
431
432 enum ath12k_amsdu_subfrm_num {
433 ATH12K_AMSDU_SUBFRM_NUM_1,
434 ATH12K_AMSDU_SUBFRM_NUM_2,
435 ATH12K_AMSDU_SUBFRM_NUM_3,
436 ATH12K_AMSDU_SUBFRM_NUM_4,
437 ATH12K_AMSDU_SUBFRM_NUM_MORE,
438 ATH12K_AMSDU_SUBFRM_NUM_MAX,
439 };
440
441 enum ath12k_counter_type {
442 ATH12K_COUNTER_TYPE_BYTES,
443 ATH12K_COUNTER_TYPE_PKTS,
444 ATH12K_COUNTER_TYPE_MAX,
445 };
446
447 enum ath12k_stats_type {
448 ATH12K_STATS_TYPE_SUCC,
449 ATH12K_STATS_TYPE_FAIL,
450 ATH12K_STATS_TYPE_RETRY,
451 ATH12K_STATS_TYPE_AMPDU,
452 ATH12K_STATS_TYPE_MAX,
453 };
454
455 struct ath12k_htt_data_stats {
456 u64 legacy[ATH12K_COUNTER_TYPE_MAX][ATH12K_LEGACY_NUM];
457 u64 ht[ATH12K_COUNTER_TYPE_MAX][ATH12K_HT_MCS_NUM];
458 u64 vht[ATH12K_COUNTER_TYPE_MAX][ATH12K_VHT_MCS_NUM];
459 u64 he[ATH12K_COUNTER_TYPE_MAX][ATH12K_HE_MCS_NUM];
460 u64 bw[ATH12K_COUNTER_TYPE_MAX][ATH12K_BW_NUM];
461 u64 nss[ATH12K_COUNTER_TYPE_MAX][ATH12K_NSS_NUM];
462 u64 gi[ATH12K_COUNTER_TYPE_MAX][ATH12K_GI_NUM];
463 u64 transmit_type[ATH12K_COUNTER_TYPE_MAX][HAL_RX_RECEPTION_TYPE_MAX];
464 u64 ru_loc[ATH12K_COUNTER_TYPE_MAX][HAL_RX_RU_ALLOC_TYPE_MAX];
465 };
466
467 struct ath12k_htt_tx_stats {
468 struct ath12k_htt_data_stats stats[ATH12K_STATS_TYPE_MAX];
469 u64 tx_duration;
470 u64 ba_fails;
471 u64 ack_fails;
472 u16 ru_start;
473 u16 ru_tones;
474 u32 mu_group[MAX_MU_GROUP_ID];
475 };
476
477 struct ath12k_per_ppdu_tx_stats {
478 u16 succ_pkts;
479 u16 failed_pkts;
480 u16 retry_pkts;
481 u32 succ_bytes;
482 u32 failed_bytes;
483 u32 retry_bytes;
484 };
485
486 struct ath12k_link_sta {
487 struct ath12k_link_vif *arvif;
488 struct ath12k_sta *ahsta;
489
490 /* link address similar to ieee80211_link_sta */
491 u8 addr[ETH_ALEN];
492
493 /* the following are protected by ar->data_lock */
494 u32 changed; /* IEEE80211_RC_* */
495 u32 bw;
496 u32 nss;
497 u32 smps;
498
499 struct wiphy_work update_wk;
500 u8 link_id;
501 u32 bw_prev;
502 u32 peer_nss;
503 s8 rssi_beacon;
504 s8 chain_signal[IEEE80211_MAX_CHAINS];
505
506 /* For now the assoc link will be considered primary */
507 bool is_assoc_link;
508
509 /* for firmware use only */
510 u8 link_idx;
511
512 /* peer addr based rhashtable list pointer */
513 struct rhash_head rhash_addr;
514 };
515
516 struct ath12k_sta {
517 struct ath12k_vif *ahvif;
518 enum hal_pn_type pn_type;
519 struct ath12k_link_sta deflink;
520 struct ath12k_link_sta __rcu *link[IEEE80211_MLD_MAX_NUM_LINKS];
521 /* indicates bitmap of link sta created in FW */
522 u16 links_map;
523 u8 assoc_link_id;
524 u16 ml_peer_id;
525 u8 num_peer;
526
527 enum ieee80211_sta_state state;
528 };
529
530 #define ATH12K_HALF_20MHZ_BW 10
531 #define ATH12K_2GHZ_MIN_CENTER 2412
532 #define ATH12K_2GHZ_MAX_CENTER 2484
533 #define ATH12K_5GHZ_MIN_CENTER 4900
534 #define ATH12K_5GHZ_MAX_CENTER 5920
535 #define ATH12K_6GHZ_MIN_CENTER 5935
536 #define ATH12K_6GHZ_MAX_CENTER 7115
537 #define ATH12K_MIN_2GHZ_FREQ (ATH12K_2GHZ_MIN_CENTER - ATH12K_HALF_20MHZ_BW - 1)
538 #define ATH12K_MAX_2GHZ_FREQ (ATH12K_2GHZ_MAX_CENTER + ATH12K_HALF_20MHZ_BW + 1)
539 #define ATH12K_MIN_5GHZ_FREQ (ATH12K_5GHZ_MIN_CENTER - ATH12K_HALF_20MHZ_BW)
540 #define ATH12K_MAX_5GHZ_FREQ (ATH12K_5GHZ_MAX_CENTER + ATH12K_HALF_20MHZ_BW)
541 #define ATH12K_MIN_6GHZ_FREQ (ATH12K_6GHZ_MIN_CENTER - ATH12K_HALF_20MHZ_BW)
542 #define ATH12K_MAX_6GHZ_FREQ (ATH12K_6GHZ_MAX_CENTER + ATH12K_HALF_20MHZ_BW)
543 #define ATH12K_NUM_CHANS 101
544 #define ATH12K_MAX_5GHZ_CHAN 173
545
ath12k_is_2ghz_channel_freq(u32 freq)546 static inline bool ath12k_is_2ghz_channel_freq(u32 freq)
547 {
548 return freq >= ATH12K_MIN_2GHZ_FREQ &&
549 freq <= ATH12K_MAX_2GHZ_FREQ;
550 }
551
552 enum ath12k_hw_state {
553 ATH12K_HW_STATE_OFF,
554 ATH12K_HW_STATE_ON,
555 ATH12K_HW_STATE_RESTARTING,
556 ATH12K_HW_STATE_RESTARTED,
557 ATH12K_HW_STATE_WEDGED,
558 ATH12K_HW_STATE_TM,
559 /* Add other states as required */
560 };
561
562 /* Antenna noise floor */
563 #define ATH12K_DEFAULT_NOISE_FLOOR -95
564
565 struct ath12k_ftm_event_obj {
566 u32 data_pos;
567 u32 expected_seq;
568 u8 *eventdata;
569 };
570
571 struct ath12k_fw_stats {
572 u32 pdev_id;
573 u32 stats_id;
574 struct list_head pdevs;
575 struct list_head vdevs;
576 struct list_head bcn;
577 u32 num_vdev_recvd;
578 };
579
580 struct ath12k_dbg_htt_stats {
581 enum ath12k_dbg_htt_ext_stats_type type;
582 u32 cfg_param[4];
583 u8 reset;
584 struct debug_htt_stats_req *stats_req;
585 };
586
587 struct ath12k_debug {
588 struct dentry *debugfs_pdev;
589 struct dentry *debugfs_pdev_symlink;
590 struct ath12k_dbg_htt_stats htt_stats;
591 enum wmi_halphy_ctrl_path_stats_id tpc_stats_type;
592 bool tpc_request;
593 struct completion tpc_complete;
594 struct wmi_tpc_stats_arg *tpc_stats;
595 u32 rx_filter;
596 bool extd_rx_stats;
597 };
598
599 struct ath12k_pdev_rssi_offsets {
600 s32 temp_offset;
601 s8 min_nf_dbm;
602 /* Cache the sum here to avoid calculating it every time in hot path
603 * noise_floor = min_nf_dbm + temp_offset
604 */
605 s32 noise_floor;
606 };
607
608 #define ATH12K_FLUSH_TIMEOUT (5 * HZ)
609 #define ATH12K_VDEV_DELETE_TIMEOUT_HZ (5 * HZ)
610
611 struct ath12k {
612 struct ath12k_base *ab;
613 struct ath12k_pdev *pdev;
614 struct ath12k_hw *ah;
615 struct ath12k_wmi_pdev *wmi;
616 struct ath12k_pdev_dp dp;
617 u8 mac_addr[ETH_ALEN];
618 u32 ht_cap_info;
619 u32 vht_cap_info;
620 struct ath12k_he ar_he;
621 bool supports_6ghz;
622 struct {
623 struct completion started;
624 struct completion completed;
625 struct completion on_channel;
626 struct delayed_work timeout;
627 enum ath12k_scan_state state;
628 bool is_roc;
629 int roc_freq;
630 bool roc_notify;
631 struct wiphy_work vdev_clean_wk;
632 struct ath12k_link_vif *arvif;
633 } scan;
634
635 struct {
636 struct ieee80211_supported_band sbands[NUM_NL80211_BANDS];
637 struct ieee80211_sband_iftype_data
638 iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES];
639 } mac;
640
641 unsigned long dev_flags;
642 unsigned int filter_flags;
643 u32 min_tx_power;
644 u32 max_tx_power;
645 u32 txpower_limit_2g;
646 u32 txpower_limit_5g;
647 u32 txpower_scale;
648 u32 power_scale;
649 u32 chan_tx_pwr;
650 u32 rts_threshold;
651 u32 num_stations;
652 u32 max_num_stations;
653
654 /* protects the radio specific data like debug stats, ppdu_stats_info stats,
655 * vdev_stop_status info, scan data, ath12k_sta info, ath12k_link_vif info,
656 * channel context data, survey info, test mode data, regd_channel_update_queue.
657 */
658 spinlock_t data_lock;
659
660 struct list_head arvifs;
661 /* should never be NULL; needed for regular htt rx */
662 struct ieee80211_channel *rx_channel;
663
664 /* valid during scan; needed for mgmt rx during scan */
665 struct ieee80211_channel *scan_channel;
666
667 u8 cfg_tx_chainmask;
668 u8 cfg_rx_chainmask;
669 u8 num_rx_chains;
670 u8 num_tx_chains;
671 /* pdev_idx starts from 0 whereas pdev->pdev_id starts with 1 */
672 u8 pdev_idx;
673 u8 lmac_id;
674 u8 hw_link_id;
675
676 struct completion peer_assoc_done;
677 struct completion peer_delete_done;
678
679 int install_key_status;
680 struct completion install_key_done;
681
682 int last_wmi_vdev_start_status;
683 struct completion vdev_setup_done;
684 struct completion vdev_delete_done;
685
686 int num_peers;
687 int max_num_peers;
688 u32 num_started_vdevs;
689 u32 num_created_vdevs;
690 unsigned long long allocated_vdev_map;
691
692 struct idr txmgmt_idr;
693 /* protects txmgmt_idr data */
694 spinlock_t txmgmt_idr_lock;
695 atomic_t num_pending_mgmt_tx;
696 wait_queue_head_t txmgmt_empty_waitq;
697
698 /* cycle count is reported twice for each visited channel during scan.
699 * access protected by data_lock
700 */
701 u32 survey_last_rx_clear_count;
702 u32 survey_last_cycle_count;
703
704 /* Channel info events are expected to come in pairs without and with
705 * COMPLETE flag set respectively for each channel visit during scan.
706 *
707 * However there are deviations from this rule. This flag is used to
708 * avoid reporting garbage data.
709 */
710 bool ch_info_can_report_survey;
711 struct survey_info survey[ATH12K_NUM_CHANS];
712 struct completion bss_survey_done;
713
714 struct work_struct regd_update_work;
715 struct work_struct regd_channel_update_work;
716 struct list_head regd_channel_update_queue;
717
718 struct wiphy_work wmi_mgmt_tx_work;
719 struct sk_buff_head wmi_mgmt_tx_queue;
720
721 struct ath12k_wow wow;
722 struct completion target_suspend;
723 bool target_suspend_ack;
724
725 struct ath12k_per_peer_tx_stats cached_stats;
726 u32 last_ppdu_id;
727 u32 cached_ppdu_id;
728 #ifdef CONFIG_ATH12K_DEBUGFS
729 struct ath12k_debug debug;
730 #endif
731
732 bool dfs_block_radar_events;
733 bool monitor_vdev_created;
734 bool monitor_started;
735 int monitor_vdev_id;
736
737 struct wiphy_radio_freq_range freq_range;
738
739 bool nlo_enabled;
740
741 /* Protected by wiphy::mtx lock. */
742 u32 vdev_id_11d_scan;
743 struct completion completed_11d_scan;
744 enum ath12k_11d_state state_11d;
745 u8 alpha2[REG_ALPHA2_LEN];
746 bool regdom_set_by_user;
747 struct completion regd_update_completed;
748
749 struct completion fw_stats_complete;
750 struct completion fw_stats_done;
751
752 struct completion mlo_setup_done;
753 u32 mlo_setup_status;
754 u8 ftm_msgref;
755 struct ath12k_fw_stats fw_stats;
756 unsigned long last_tx_power_update;
757
758 s8 max_allowed_tx_power;
759 struct ath12k_pdev_rssi_offsets rssi_info;
760 };
761
762 struct ath12k_hw {
763 struct ieee80211_hw *hw;
764 struct device *dev;
765
766 /* Protect the write operation of the hardware state ath12k_hw::state
767 * between hardware start<=>reconfigure<=>stop transitions.
768 */
769 struct mutex hw_mutex;
770 enum ath12k_hw_state state;
771 bool regd_updated;
772 bool use_6ghz_regd;
773
774 u8 num_radio;
775
776 DECLARE_BITMAP(free_ml_peer_id_map, ATH12K_MAX_MLO_PEERS);
777
778 struct ath12k_dp_hw dp_hw;
779
780 /* Keep last */
781 struct ath12k radio[] __aligned(sizeof(void *));
782 };
783
784 struct ath12k_band_cap {
785 u32 phy_id;
786 u32 max_bw_supported;
787 u32 ht_cap_info;
788 u32 he_cap_info[2];
789 u32 he_mcs;
790 u32 he_cap_phy_info[PSOC_HOST_MAX_PHY_SIZE];
791 struct ath12k_wmi_ppe_threshold_arg he_ppet;
792 u16 he_6ghz_capa;
793 u32 eht_cap_mac_info[WMI_MAX_EHTCAP_MAC_SIZE];
794 u32 eht_cap_phy_info[WMI_MAX_EHTCAP_PHY_SIZE];
795 u32 eht_mcs_20_only;
796 u32 eht_mcs_80;
797 u32 eht_mcs_160;
798 u32 eht_mcs_320;
799 struct ath12k_wmi_ppe_threshold_arg eht_ppet;
800 u32 eht_cap_info_internal;
801 };
802
803 struct ath12k_pdev_cap {
804 u32 supported_bands;
805 u32 ampdu_density;
806 u32 vht_cap;
807 u32 vht_mcs;
808 u32 he_mcs;
809 u32 tx_chain_mask;
810 u32 rx_chain_mask;
811 u32 tx_chain_mask_shift;
812 u32 rx_chain_mask_shift;
813 struct ath12k_band_cap band[NUM_NL80211_BANDS];
814 u32 eml_cap;
815 u32 mld_cap;
816 bool nss_ratio_enabled;
817 u8 nss_ratio_info;
818 };
819
820 struct mlo_timestamp {
821 u32 info;
822 u32 sync_timestamp_lo_us;
823 u32 sync_timestamp_hi_us;
824 u32 mlo_offset_lo;
825 u32 mlo_offset_hi;
826 u32 mlo_offset_clks;
827 u32 mlo_comp_clks;
828 u32 mlo_comp_timer;
829 };
830
831 struct ath12k_pdev {
832 struct ath12k *ar;
833 u32 pdev_id;
834 u32 hw_link_id;
835 struct ath12k_pdev_cap cap;
836 u8 mac_addr[ETH_ALEN];
837 struct mlo_timestamp timestamp;
838 };
839
840 struct ath12k_fw_pdev {
841 u32 pdev_id;
842 u32 phy_id;
843 u32 supported_bands;
844 };
845
846 struct ath12k_board_data {
847 const struct firmware *fw;
848 const void *data;
849 size_t len;
850 };
851
852 struct ath12k_reg_freq {
853 u32 start_freq;
854 u32 end_freq;
855 };
856
857 struct ath12k_mlo_memory {
858 struct target_mem_chunk chunk[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01];
859 int mlo_mem_size;
860 bool init_done;
861 };
862
863 struct ath12k_hw_link {
864 u8 device_id;
865 u8 pdev_idx;
866 };
867
868 /* Holds info on the group of devices that are registered as a single
869 * wiphy, protected with struct ath12k_hw_group::mutex.
870 */
871 struct ath12k_hw_group {
872 /* Keep dp_hw_grp as the first member to allow efficient
873 * usage of cache lines for DP fields
874 */
875 struct ath12k_dp_hw_group dp_hw_grp;
876 struct ath12k_hw_link hw_links[ATH12K_GROUP_MAX_RADIO];
877 struct list_head list;
878 u8 id;
879 u8 num_devices;
880 u8 num_probed;
881 u8 num_started;
882 unsigned long flags;
883 struct ath12k_base *ab[ATH12K_MAX_DEVICES];
884
885 /* protects access to this struct */
886 struct mutex mutex;
887
888 /* Holds information of wiphy (hw) registration.
889 *
890 * In Multi/Single Link Operation case, all pdevs are registered as
891 * a single wiphy. In other (legacy/Non-MLO) cases, each pdev is
892 * registered as separate wiphys.
893 */
894 struct ath12k_hw *ah[ATH12K_GROUP_MAX_RADIO];
895 u8 num_hw;
896 bool mlo_capable;
897 struct device_node *wsi_node[ATH12K_MAX_DEVICES];
898 struct ath12k_mlo_memory mlo_mem;
899 bool hw_link_id_init_done;
900 };
901
902 /* Holds WSI info specific to each device, excluding WSI group info */
903 struct ath12k_wsi_info {
904 u32 index;
905 u32 hw_link_id_base;
906 };
907
908 struct ath12k_dp_profile_params {
909 u32 tx_comp_ring_size;
910 u32 rxdma_monitor_buf_ring_size;
911 u32 rxdma_monitor_dst_ring_size;
912 u32 num_pool_tx_desc;
913 u32 rx_desc_count;
914 };
915
916 struct ath12k_mem_profile_based_param {
917 u32 num_vdevs;
918 u32 max_client_single;
919 u32 max_client_dbs;
920 u32 max_client_dbs_sbs;
921 struct ath12k_dp_profile_params dp_params;
922 };
923
924 enum ath12k_device_family {
925 ATH12K_DEVICE_FAMILY_START,
926 ATH12K_DEVICE_FAMILY_WIFI7 = ATH12K_DEVICE_FAMILY_START,
927 ATH12K_DEVICE_FAMILY_MAX,
928 };
929
930 /* Master structure to hold the hw data which may be used in core module */
931 struct ath12k_base {
932 enum ath12k_hw_rev hw_rev;
933 struct platform_device *pdev;
934 struct device *dev;
935 struct ath12k_qmi qmi;
936 struct ath12k_wmi_base wmi_ab;
937 struct completion fw_ready;
938 u8 device_id;
939 int num_radios;
940 /* HW channel counters frequency value in hertz common to all MACs */
941 u32 cc_freq_hz;
942
943 struct ath12k_dump_file_data *dump_data;
944 size_t ath12k_coredump_len;
945 struct work_struct dump_work;
946
947 struct ath12k_htc htc;
948
949 struct ath12k_dp *dp;
950
951 void __iomem *mem;
952 unsigned long mem_len;
953
954 void __iomem *mem_ce;
955 u32 ce_remap_base_addr;
956 u32 cmem_offset;
957 bool ce_remap;
958
959 struct {
960 enum ath12k_bus bus;
961 const struct ath12k_hif_ops *ops;
962 } hif;
963
964 struct {
965 struct completion wakeup_completed;
966 u32 wmi_conf_rx_decap_mode;
967 } wow;
968
969 struct ath12k_ce ce;
970 struct timer_list rx_replenish_retry;
971 struct ath12k_hal hal;
972 /* To synchronize core_start/core_stop */
973 struct mutex core_lock;
974 /* Protects data like peers */
975 spinlock_t base_lock;
976
977 /* Single pdev device (struct ath12k_hw_params::single_pdev_only):
978 *
979 * Firmware maintains data for all bands but advertises a single
980 * phy to the host which is stored as a single element in this
981 * array.
982 *
983 * Other devices:
984 *
985 * This array will contain as many elements as the number of
986 * radios.
987 */
988 struct ath12k_pdev pdevs[MAX_RADIOS];
989
990 /* struct ath12k_hw_params::single_pdev_only devices use this to
991 * store phy specific data
992 */
993 struct ath12k_fw_pdev fw_pdev[MAX_RADIOS];
994 u8 fw_pdev_count;
995
996 struct ath12k_pdev __rcu *pdevs_active[MAX_RADIOS];
997
998 struct ath12k_wmi_hal_reg_capabilities_ext_arg hal_reg_cap[MAX_RADIOS];
999 unsigned long long free_vdev_map;
1000 unsigned long long free_vdev_stats_id_map;
1001 wait_queue_head_t peer_mapping_wq;
1002 u8 mac_addr[ETH_ALEN];
1003 bool wmi_ready;
1004 u32 wlan_init_status;
1005 int irq_num[ATH12K_IRQ_NUM_MAX];
1006 struct ath12k_ext_irq_grp ext_irq_grp[ATH12K_EXT_IRQ_GRP_NUM_MAX];
1007 struct napi_struct *napi;
1008 struct ath12k_wmi_target_cap_arg target_caps;
1009 u32 ext_service_bitmap[WMI_SERVICE_EXT_BM_SIZE];
1010 bool pdevs_macaddr_valid;
1011
1012 const struct ath12k_hw_params *hw_params;
1013
1014 const struct firmware *cal_file;
1015
1016 /* Below regd's are protected by ab->data_lock */
1017 /* This is the regd set for every radio
1018 * by the firmware during initialization
1019 */
1020 struct ieee80211_regdomain *default_regd[MAX_RADIOS];
1021 /* This regd is set during dynamic country setting
1022 * This may or may not be used during the runtime
1023 */
1024 struct ieee80211_regdomain *new_regd[MAX_RADIOS];
1025
1026 struct ath12k_reg_info *reg_info[MAX_RADIOS];
1027
1028 /* Current DFS Regulatory */
1029 enum ath12k_dfs_region dfs_region;
1030 #ifdef CONFIG_ATH12K_DEBUGFS
1031 struct dentry *debugfs_soc;
1032 #endif
1033
1034 unsigned long dev_flags;
1035 struct completion driver_recovery;
1036 struct workqueue_struct *workqueue;
1037 struct work_struct restart_work;
1038 struct workqueue_struct *workqueue_aux;
1039 struct work_struct reset_work;
1040 atomic_t reset_count;
1041 atomic_t recovery_count;
1042 bool is_reset;
1043 struct completion reset_complete;
1044 /* continuous recovery fail count */
1045 atomic_t fail_cont_count;
1046 unsigned long reset_fail_timeout;
1047 struct work_struct update_11d_work;
1048 u8 new_alpha2[2];
1049 struct {
1050 /* protected by data_lock */
1051 u32 fw_crash_counter;
1052 } stats;
1053 u32 pktlog_defs_checksum;
1054
1055 struct ath12k_dbring_cap *db_caps;
1056 u32 num_db_cap;
1057
1058 struct completion htc_suspend;
1059
1060 u64 fw_soc_drop_count;
1061 bool static_window_map;
1062
1063 struct work_struct rfkill_work;
1064 /* true means radio is on */
1065 bool rfkill_radio_on;
1066
1067 struct {
1068 enum ath12k_bdf_search bdf_search;
1069 u32 vendor;
1070 u32 device;
1071 u32 subsystem_vendor;
1072 u32 subsystem_device;
1073 } id;
1074
1075 struct {
1076 u32 api_version;
1077
1078 const struct firmware *fw;
1079 const u8 *amss_data;
1080 size_t amss_len;
1081 const u8 *amss_dualmac_data;
1082 size_t amss_dualmac_len;
1083 const u8 *m3_data;
1084 size_t m3_len;
1085 const u8 *aux_uc_data;
1086 size_t aux_uc_len;
1087
1088 DECLARE_BITMAP(fw_features, ATH12K_FW_FEATURE_COUNT);
1089 bool fw_features_valid;
1090 } fw;
1091
1092 struct completion restart_completed;
1093
1094 #ifdef CONFIG_ACPI
1095
1096 struct {
1097 bool started;
1098 u32 func_bit;
1099 bool acpi_tas_enable;
1100 bool acpi_bios_sar_enable;
1101 bool acpi_disable_11be;
1102 bool acpi_disable_rfkill;
1103 bool acpi_cca_enable;
1104 bool acpi_band_edge_enable;
1105 bool acpi_enable_bdf;
1106 u32 bit_flag;
1107 char bdf_string[ATH12K_ACPI_BDF_MAX_LEN];
1108 u8 tas_cfg[ATH12K_ACPI_DSM_TAS_CFG_SIZE];
1109 u8 tas_sar_power_table[ATH12K_ACPI_DSM_TAS_DATA_SIZE];
1110 u8 bios_sar_data[ATH12K_ACPI_DSM_BIOS_SAR_DATA_SIZE];
1111 u8 geo_offset_data[ATH12K_ACPI_DSM_GEO_OFFSET_DATA_SIZE];
1112 u8 cca_data[ATH12K_ACPI_DSM_CCA_DATA_SIZE];
1113 u8 band_edge_power[ATH12K_ACPI_DSM_BAND_EDGE_DATA_SIZE];
1114 } acpi;
1115
1116 #endif /* CONFIG_ACPI */
1117
1118 struct notifier_block panic_nb;
1119
1120 struct ath12k_hw_group *ag;
1121 struct ath12k_wsi_info wsi_info;
1122 enum ath12k_firmware_mode fw_mode;
1123 struct ath12k_ftm_event_obj ftm_event_obj;
1124 bool hw_group_ref;
1125
1126 /* Denote whether MLO is possible within the device */
1127 bool single_chip_mlo_support;
1128
1129 struct ath12k_reg_freq reg_freq_2ghz;
1130 struct ath12k_reg_freq reg_freq_5ghz;
1131 struct ath12k_reg_freq reg_freq_6ghz;
1132 const struct ath12k_mem_profile_based_param *profile_param;
1133 enum ath12k_qmi_mem_mode target_mem_mode;
1134
1135 /* FIXME: Define this field in a ag equivalent object available
1136 * during the initial phase of probe later.
1137 */
1138 const struct ieee80211_ops *ath12k_ops;
1139
1140 struct rhashtable *rhead_sta_addr;
1141 struct rhashtable_params rhash_sta_addr_param;
1142
1143 /* must be last */
1144 u8 drv_priv[] __aligned(sizeof(void *));
1145 };
1146
1147 struct ath12k_pdev_map {
1148 struct ath12k_base *ab;
1149 u8 pdev_idx;
1150 };
1151
1152 struct ath12k_fw_stats_vdev {
1153 struct list_head list;
1154
1155 u32 vdev_id;
1156 u32 beacon_snr;
1157 u32 data_snr;
1158 u32 num_tx_frames[WLAN_MAX_AC];
1159 u32 num_rx_frames;
1160 u32 num_tx_frames_retries[WLAN_MAX_AC];
1161 u32 num_tx_frames_failures[WLAN_MAX_AC];
1162 u32 num_rts_fail;
1163 u32 num_rts_success;
1164 u32 num_rx_err;
1165 u32 num_rx_discard;
1166 u32 num_tx_not_acked;
1167 u32 tx_rate_history[MAX_TX_RATE_VALUES];
1168 u32 beacon_rssi_history[MAX_TX_RATE_VALUES];
1169 };
1170
1171 struct ath12k_fw_stats_bcn {
1172 struct list_head list;
1173
1174 u32 vdev_id;
1175 u32 tx_bcn_succ_cnt;
1176 u32 tx_bcn_outage_cnt;
1177 };
1178
1179 struct ath12k_fw_stats_pdev {
1180 struct list_head list;
1181
1182 /* PDEV stats */
1183 s32 ch_noise_floor;
1184 u32 tx_frame_count;
1185 u32 rx_frame_count;
1186 u32 rx_clear_count;
1187 u32 cycle_count;
1188 u32 phy_err_count;
1189 u32 chan_tx_power;
1190 u32 ack_rx_bad;
1191 u32 rts_bad;
1192 u32 rts_good;
1193 u32 fcs_bad;
1194 u32 no_beacons;
1195 u32 mib_int_count;
1196
1197 /* PDEV TX stats */
1198 s32 comp_queued;
1199 s32 comp_delivered;
1200 s32 msdu_enqued;
1201 s32 mpdu_enqued;
1202 s32 wmm_drop;
1203 s32 local_enqued;
1204 s32 local_freed;
1205 s32 hw_queued;
1206 s32 hw_reaped;
1207 s32 underrun;
1208 s32 tx_abort;
1209 s32 mpdus_requed;
1210 u32 tx_ko;
1211 u32 data_rc;
1212 u32 self_triggers;
1213 u32 sw_retry_failure;
1214 u32 illgl_rate_phy_err;
1215 u32 pdev_cont_xretry;
1216 u32 pdev_tx_timeout;
1217 u32 pdev_resets;
1218 u32 stateless_tid_alloc_failure;
1219 u32 phy_underrun;
1220 u32 txop_ovf;
1221
1222 /* PDEV RX stats */
1223 s32 mid_ppdu_route_change;
1224 s32 status_rcvd;
1225 s32 r0_frags;
1226 s32 r1_frags;
1227 s32 r2_frags;
1228 s32 r3_frags;
1229 s32 htt_msdus;
1230 s32 htt_mpdus;
1231 s32 loc_msdus;
1232 s32 loc_mpdus;
1233 s32 oversize_amsdu;
1234 s32 phy_errs;
1235 s32 phy_err_drop;
1236 s32 mpdu_errs;
1237 };
1238
1239 int ath12k_core_qmi_firmware_ready(struct ath12k_base *ab);
1240 void ath12k_core_hw_group_cleanup(struct ath12k_hw_group *ag);
1241 int ath12k_core_pre_init(struct ath12k_base *ab);
1242 int ath12k_core_init(struct ath12k_base *ath12k);
1243 void ath12k_core_deinit(struct ath12k_base *ath12k);
1244 struct ath12k_base *ath12k_core_alloc(struct device *dev, size_t priv_size,
1245 enum ath12k_bus bus);
1246 void ath12k_core_free(struct ath12k_base *ath12k);
1247 int ath12k_core_fetch_board_data_api_1(struct ath12k_base *ab,
1248 struct ath12k_board_data *bd,
1249 char *filename);
1250 int ath12k_core_fetch_bdf(struct ath12k_base *ath12k,
1251 struct ath12k_board_data *bd);
1252 void ath12k_core_free_bdf(struct ath12k_base *ab, struct ath12k_board_data *bd);
1253 int ath12k_core_fetch_regdb(struct ath12k_base *ab, struct ath12k_board_data *bd);
1254 int ath12k_core_check_dt(struct ath12k_base *ath12k);
1255 int ath12k_core_check_smbios(struct ath12k_base *ab);
1256 void ath12k_core_halt(struct ath12k *ar);
1257 int ath12k_core_resume_early(struct ath12k_base *ab);
1258 int ath12k_core_resume(struct ath12k_base *ab);
1259 int ath12k_core_suspend(struct ath12k_base *ab);
1260 int ath12k_core_suspend_late(struct ath12k_base *ab);
1261 void ath12k_core_hw_group_unassign(struct ath12k_base *ab);
1262 u8 ath12k_get_num_partner_link(struct ath12k *ar);
1263
1264 const struct firmware *ath12k_core_firmware_request(struct ath12k_base *ab,
1265 const char *filename);
1266 u32 ath12k_core_get_max_station_per_radio(struct ath12k_base *ab);
1267 u32 ath12k_core_get_max_peers_per_radio(struct ath12k_base *ab);
1268
1269 void ath12k_core_hw_group_set_mlo_capable(struct ath12k_hw_group *ag);
1270 void ath12k_fw_stats_init(struct ath12k *ar);
1271 void ath12k_fw_stats_bcn_free(struct list_head *head);
1272 void ath12k_fw_stats_free(struct ath12k_fw_stats *stats);
1273 void ath12k_fw_stats_reset(struct ath12k *ar);
1274 struct reserved_mem *ath12k_core_get_reserved_mem(struct ath12k_base *ab,
1275 int index);
1276 enum ath12k_qmi_mem_mode ath12k_core_get_memory_mode(struct ath12k_base *ab);
1277
ath12k_scan_state_str(enum ath12k_scan_state state)1278 static inline const char *ath12k_scan_state_str(enum ath12k_scan_state state)
1279 {
1280 switch (state) {
1281 case ATH12K_SCAN_IDLE:
1282 return "idle";
1283 case ATH12K_SCAN_STARTING:
1284 return "starting";
1285 case ATH12K_SCAN_RUNNING:
1286 return "running";
1287 case ATH12K_SCAN_ABORTING:
1288 return "aborting";
1289 }
1290
1291 return "unknown";
1292 }
1293
ATH12K_SKB_CB(struct sk_buff * skb)1294 static inline struct ath12k_skb_cb *ATH12K_SKB_CB(struct sk_buff *skb)
1295 {
1296 BUILD_BUG_ON(sizeof(struct ath12k_skb_cb) >
1297 IEEE80211_TX_INFO_DRIVER_DATA_SIZE);
1298 return (struct ath12k_skb_cb *)&IEEE80211_SKB_CB(skb)->driver_data;
1299 }
1300
ATH12K_SKB_RXCB(struct sk_buff * skb)1301 static inline struct ath12k_skb_rxcb *ATH12K_SKB_RXCB(struct sk_buff *skb)
1302 {
1303 BUILD_BUG_ON(sizeof(struct ath12k_skb_rxcb) > sizeof(skb->cb));
1304 return (struct ath12k_skb_rxcb *)skb->cb;
1305 }
1306
ath12k_vif_to_ahvif(struct ieee80211_vif * vif)1307 static inline struct ath12k_vif *ath12k_vif_to_ahvif(struct ieee80211_vif *vif)
1308 {
1309 return (struct ath12k_vif *)vif->drv_priv;
1310 }
1311
ath12k_sta_to_ahsta(struct ieee80211_sta * sta)1312 static inline struct ath12k_sta *ath12k_sta_to_ahsta(struct ieee80211_sta *sta)
1313 {
1314 return (struct ath12k_sta *)sta->drv_priv;
1315 }
1316
ath12k_ahsta_to_sta(struct ath12k_sta * ahsta)1317 static inline struct ieee80211_sta *ath12k_ahsta_to_sta(struct ath12k_sta *ahsta)
1318 {
1319 return container_of((void *)ahsta, struct ieee80211_sta, drv_priv);
1320 }
1321
ath12k_ahvif_to_vif(struct ath12k_vif * ahvif)1322 static inline struct ieee80211_vif *ath12k_ahvif_to_vif(struct ath12k_vif *ahvif)
1323 {
1324 return container_of((void *)ahvif, struct ieee80211_vif, drv_priv);
1325 }
1326
ath12k_ab_to_ar(struct ath12k_base * ab,int mac_id)1327 static inline struct ath12k *ath12k_ab_to_ar(struct ath12k_base *ab,
1328 int mac_id)
1329 {
1330 return ab->pdevs[ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id)].ar;
1331 }
1332
ath12k_core_create_firmware_path(struct ath12k_base * ab,const char * filename,void * buf,size_t buf_len)1333 static inline void ath12k_core_create_firmware_path(struct ath12k_base *ab,
1334 const char *filename,
1335 void *buf, size_t buf_len)
1336 {
1337 const char *fw_name = NULL;
1338
1339 of_property_read_string(ab->dev->of_node, "firmware-name", &fw_name);
1340
1341 if (fw_name && strncmp(filename, "board", 5))
1342 snprintf(buf, buf_len, "%s/%s/%s/%s", ATH12K_FW_DIR,
1343 ab->hw_params->fw.dir, fw_name, filename);
1344 else
1345 snprintf(buf, buf_len, "%s/%s/%s", ATH12K_FW_DIR,
1346 ab->hw_params->fw.dir, filename);
1347 }
1348
ath12k_bus_str(enum ath12k_bus bus)1349 static inline const char *ath12k_bus_str(enum ath12k_bus bus)
1350 {
1351 switch (bus) {
1352 case ATH12K_BUS_PCI:
1353 return "pci";
1354 case ATH12K_BUS_AHB:
1355 return "ahb";
1356 }
1357
1358 return "unknown";
1359 }
1360
ath12k_hw_to_ah(struct ieee80211_hw * hw)1361 static inline struct ath12k_hw *ath12k_hw_to_ah(struct ieee80211_hw *hw)
1362 {
1363 return hw->priv;
1364 }
1365
ath12k_ah_to_ar(struct ath12k_hw * ah,u8 hw_link_id)1366 static inline struct ath12k *ath12k_ah_to_ar(struct ath12k_hw *ah, u8 hw_link_id)
1367 {
1368 if (WARN(hw_link_id >= ah->num_radio,
1369 "bad hw link id %d, so switch to default link\n", hw_link_id))
1370 hw_link_id = 0;
1371
1372 return &ah->radio[hw_link_id];
1373 }
1374
ath12k_ar_to_ah(struct ath12k * ar)1375 static inline struct ath12k_hw *ath12k_ar_to_ah(struct ath12k *ar)
1376 {
1377 return ar->ah;
1378 }
1379
ath12k_ar_to_hw(struct ath12k * ar)1380 static inline struct ieee80211_hw *ath12k_ar_to_hw(struct ath12k *ar)
1381 {
1382 return ar->ah->hw;
1383 }
1384
1385 #define for_each_ar(ah, ar, index) \
1386 for ((index) = 0; ((index) < (ah)->num_radio && \
1387 ((ar) = &(ah)->radio[(index)])); (index)++)
1388
ath12k_ag_to_ah(struct ath12k_hw_group * ag,int idx)1389 static inline struct ath12k_hw *ath12k_ag_to_ah(struct ath12k_hw_group *ag, int idx)
1390 {
1391 return ag->ah[idx];
1392 }
1393
ath12k_ag_set_ah(struct ath12k_hw_group * ag,int idx,struct ath12k_hw * ah)1394 static inline void ath12k_ag_set_ah(struct ath12k_hw_group *ag, int idx,
1395 struct ath12k_hw *ah)
1396 {
1397 ag->ah[idx] = ah;
1398 }
1399
ath12k_ab_to_ag(struct ath12k_base * ab)1400 static inline struct ath12k_hw_group *ath12k_ab_to_ag(struct ath12k_base *ab)
1401 {
1402 return ab->ag;
1403 }
1404
ath12k_ag_to_ab(struct ath12k_hw_group * ag,u8 device_id)1405 static inline struct ath12k_base *ath12k_ag_to_ab(struct ath12k_hw_group *ag,
1406 u8 device_id)
1407 {
1408 return ag->ab[device_id];
1409 }
1410
ath12k_pdev_get_noise_floor(struct ath12k * ar)1411 static inline s32 ath12k_pdev_get_noise_floor(struct ath12k *ar)
1412 {
1413 lockdep_assert_held(&ar->data_lock);
1414
1415 return ar->rssi_info.noise_floor;
1416 }
1417
1418 /* The @ab->dp NULL check or assertion is intentionally omitted because
1419 * @ab->dp is guaranteed to be non-NULL after a successful probe and
1420 * remains valid until teardown. Invoking this before allocation or
1421 * after teardown is considered invalid usage.
1422 */
ath12k_ab_to_dp(struct ath12k_base * ab)1423 static inline struct ath12k_dp *ath12k_ab_to_dp(struct ath12k_base *ab)
1424 {
1425 return ab->dp;
1426 }
1427
ath12k_pdev_dp_to_ar(struct ath12k_pdev_dp * dp)1428 static inline struct ath12k *ath12k_pdev_dp_to_ar(struct ath12k_pdev_dp *dp)
1429 {
1430 return container_of(dp, struct ath12k, dp);
1431 }
1432 #endif /* _CORE_H_ */
1433