Searched refs:rtmr0 (Results 1 – 15 of 15) sorted by relevance
14 u8 rtmr0[SHA256_DIGEST_SIZE]; member20 .rtmr0 = "rtmr0",76 { MR_(rtmr0, SHA256) | TSM_MR_F_LIVE },80 { .mr_value = &sample_report.rtmr0,
144 vreg_rtmr0_1p15: regulator-rtmr0-1p15 {161 vreg_rtmr0_1p8: regulator-rtmr0-1p8 {178 vreg_rtmr0_3p3: regulator-rtmr0-3p3 {988 rtmr0_default: rtmr0-reset-n-active-state {994 rtmr0_3p3_reg_en: rtmr0-3p3-reg-en-state {1002 rtmr0_1p8_reg_en: rtmr0-1p8-reg-en-state {1020 rtmr0_1p15_reg_en: rtmr0-1p15-reg-en-state {
186 vreg_rtmr0_1p15: regulator-rtmr0-1p15 {202 vreg_rtmr0_1p8: regulator-rtmr0-1p8 {218 vreg_rtmr0_3p3: regulator-rtmr0-3p3 {999 rtmr0_default: rtmr0-reset-n-active-state {1005 rtmr0_3p3_reg_en: rtmr0-3p3-reg-en-state {1013 rtmr0_1p15_reg_en: rtmr0-1p15-reg-en-state {1021 rtmr0_1p8_reg_en: rtmr0-1p8-reg-en-state {
204 vreg_rtmr0_1p15: regulator-rtmr0-1p15 {221 vreg_rtmr0_1p8: regulator-rtmr0-1p8 {238 vreg_rtmr0_3p3: regulator-rtmr0-3p3 {1170 rtmr0_default: rtmr0-reset-n-active-state {1176 rtmr0_3p3_reg_en: rtmr0-3p3-reg-en-state {1184 rtmr0_1p8_reg_en: rtmr0-1p8-reg-en-state {1202 rtmr0_1p15_reg_en: rtmr0-1p15-reg-en-state {
205 vreg_rtmr0_1p15: regulator-rtmr0-1p15 {221 vreg_rtmr0_1p8: regulator-rtmr0-1p8 {237 vreg_rtmr0_3p3: regulator-rtmr0-3p3 {965 rtmr0_default: rtmr0-reset-n-active-state {
299 vreg_rtmr0_1p15: regulator-rtmr0-1p15 {315 vreg_rtmr0_1p8: regulator-rtmr0-1p8 {331 vreg_rtmr0_3p3: regulator-rtmr0-3p3 {1013 rtmr0_default: rtmr0-reset-n-active-state {
240 vreg_rtmr0_1p15: regulator-rtmr0-1p15 {256 vreg_rtmr0_1p8: regulator-rtmr0-1p8 {272 vreg_rtmr0_3p3: regulator-rtmr0-3p3 {1067 rtmr0_default: rtmr0-reset-n-active-state {
308 vreg_rtmr0_1p15: regulator-rtmr0-1p15 {324 vreg_rtmr0_1p8: regulator-rtmr0-1p8 {340 vreg_rtmr0_3p3: regulator-rtmr0-3p3 {1075 rtmr0_default: rtmr0-reset-n-active-state {
187 vreg_rtmr0_1p15: regulator-rtmr0-1p15 {203 vreg_rtmr0_1p8: regulator-rtmr0-1p8 {219 vreg_rtmr0_3p3: regulator-rtmr0-3p3 {1091 rtmr0_default: rtmr0-reset-n-active-state {
316 vreg_rtmr0_1p15: regulator-rtmr0-1p15 {332 vreg_rtmr0_1p8: regulator-rtmr0-1p8 {348 vreg_rtmr0_3p3: regulator-rtmr0-3p3 {1123 rtmr0_default: rtmr0-reset-n-active-state {
256 vreg_rtmr0_1p15: regulator-rtmr0-1p15 {272 vreg_rtmr0_1p8: regulator-rtmr0-1p8 {288 vreg_rtmr0_3p3: regulator-rtmr0-3p3 {1224 rtmr0_default: rtmr0-reset-n-active-state {
254 vreg_rtmr0_1p15: regulator-rtmr0-1p15 {270 vreg_rtmr0_1p8: regulator-rtmr0-1p8 {286 vreg_rtmr0_3p3: regulator-rtmr0-3p3 {1184 rtmr0_default: rtmr0-reset-n-active-state {
305 vreg_rtmr0_1p15: regulator-rtmr0-1p15 {321 vreg_rtmr0_1p8: regulator-rtmr0-1p8 {337 vreg_rtmr0_3p3: regulator-rtmr0-3p3 {1139 rtmr0_default: rtmr0-reset-n-active-state {
346 vreg_rtmr0_1p15: regulator-rtmr0-1p15 {362 vreg_rtmr0_1p8: regulator-rtmr0-1p8 {378 vreg_rtmr0_3p3: regulator-rtmr0-3p3 {1288 rtmr0_default: rtmr0-reset-n-active-state {
96 { TDX_MR_(rtmr0) | TSM_MR_F_RTMR },