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Searched refs:rq_regs (Results 1 – 25 of 52) sorted by relevance

123

/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn21/
H A Ddcn21_hubp.c139 struct _vcs_dpi_display_rq_regs_st *rq_regs) in hubp21_program_requestor() argument
144 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); in hubp21_program_requestor()
146 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, in hubp21_program_requestor()
147 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, in hubp21_program_requestor()
148 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, in hubp21_program_requestor()
149 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); in hubp21_program_requestor()
151 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, in hubp21_program_requestor()
152 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, in hubp21_program_requestor()
153 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, in hubp21_program_requestor()
154 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, in hubp21_program_requestor()
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/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn201/
H A Ddcn201_hubp.c67 struct _vcs_dpi_display_rq_regs_st *rq_regs) in hubp201_program_requestor() argument
72 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); in hubp201_program_requestor()
75 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, in hubp201_program_requestor()
76 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, in hubp201_program_requestor()
77 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, in hubp201_program_requestor()
78 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); in hubp201_program_requestor()
82 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, in hubp201_program_requestor()
83 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, in hubp201_program_requestor()
84 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, in hubp201_program_requestor()
85 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, in hubp201_program_requestor()
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/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn20/
H A Ddcn20_hubp.c198 struct _vcs_dpi_display_rq_regs_st *rq_regs) in hubp2_program_requestor() argument
203 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); in hubp2_program_requestor()
205 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, in hubp2_program_requestor()
206 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, in hubp2_program_requestor()
207 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, in hubp2_program_requestor()
208 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); in hubp2_program_requestor()
210 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, in hubp2_program_requestor()
211 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, in hubp2_program_requestor()
212 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, in hubp2_program_requestor()
213 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, in hubp2_program_requestor()
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/linux/drivers/gpu/drm/amd/display/dc/dml/
H A Ddisplay_rq_dlg_helpers.c145 …_regs_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_data_rq_regs_st *rq_regs) in print__data_rq_regs_st() argument
149 dml_print("DML_RQ_DLG_CALC: chunk_size = 0x%0x\n", rq_regs->chunk_size); in print__data_rq_regs_st()
150 dml_print("DML_RQ_DLG_CALC: min_chunk_size = 0x%0x\n", rq_regs->min_chunk_size); in print__data_rq_regs_st()
151 dml_print("DML_RQ_DLG_CALC: meta_chunk_size = 0x%0x\n", rq_regs->meta_chunk_size); in print__data_rq_regs_st()
154 rq_regs->min_meta_chunk_size); in print__data_rq_regs_st()
155 dml_print("DML_RQ_DLG_CALC: dpte_group_size = 0x%0x\n", rq_regs->dpte_group_size); in print__data_rq_regs_st()
156 dml_print("DML_RQ_DLG_CALC: mpte_group_size = 0x%0x\n", rq_regs->mpte_group_size); in print__data_rq_regs_st()
157 dml_print("DML_RQ_DLG_CALC: swath_height = 0x%0x\n", rq_regs->swath_height); in print__data_rq_regs_st()
160 rq_regs->pte_row_height_linear); in print__data_rq_regs_st()
164 …t__rq_regs_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_rq_regs_st *rq_regs) in print__rq_regs_st() argument
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H A Ddml1_display_rq_dlg_calc.c208 struct _vcs_dpi_display_data_rq_regs_st *rq_regs, in extract_rq_sizing_regs() argument
214 rq_regs->chunk_size = dml_log2(rq_sizing->chunk_bytes) - 10; in extract_rq_sizing_regs()
217 rq_regs->min_chunk_size = 0; in extract_rq_sizing_regs()
219 rq_regs->min_chunk_size = dml_log2(rq_sizing->min_chunk_bytes) - 8 + 1; in extract_rq_sizing_regs()
221 rq_regs->meta_chunk_size = dml_log2(rq_sizing->meta_chunk_bytes) - 10; in extract_rq_sizing_regs()
223 rq_regs->min_meta_chunk_size = 0; in extract_rq_sizing_regs()
225 rq_regs->min_meta_chunk_size = dml_log2(rq_sizing->min_meta_chunk_bytes) - 6 + 1; in extract_rq_sizing_regs()
227 rq_regs->dpte_group_size = dml_log2(rq_sizing->dpte_group_bytes) - 6; in extract_rq_sizing_regs()
228 rq_regs->mpte_group_size = dml_log2(rq_sizing->mpte_group_bytes) - 6; in extract_rq_sizing_regs()
233 struct _vcs_dpi_display_rq_regs_st *rq_regs, in dml1_extract_rq_regs() argument
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H A Ddisplay_rq_dlg_helpers.h40 …regs_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_data_rq_regs_st *rq_regs);
41 …__rq_regs_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_rq_regs_st *rq_regs);
H A Ddisplay_mode_lib.h65 display_rq_regs_st *rq_regs,
76 void (*rq_dlg_get_rq_reg_v2)(display_rq_regs_st *rq_regs,
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn10/
H A Ddcn10_hubp.c575 struct _vcs_dpi_display_rq_regs_st *rq_regs) in hubp1_program_requestor() argument
580 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); in hubp1_program_requestor()
582 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, in hubp1_program_requestor()
583 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, in hubp1_program_requestor()
584 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, in hubp1_program_requestor()
585 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); in hubp1_program_requestor()
587 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, in hubp1_program_requestor()
588 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, in hubp1_program_requestor()
589 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, in hubp1_program_requestor()
590 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, in hubp1_program_requestor()
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/linux/drivers/gpu/drm/amd/display/dc/dml2_0/
H A Ddml_display_rq_dlg_calc.c39 void dml_rq_dlg_get_rq_reg(dml_display_rq_regs_st *rq_regs, in dml_rq_dlg_get_rq_reg() argument
73 memset(rq_regs, 0, sizeof(*rq_regs)); in dml_rq_dlg_get_rq_reg()
97 rq_regs->rq_regs_l.chunk_size = (dml_uint_t)(dml_log2((dml_float_t) pixel_chunk_bytes) - 10); in dml_rq_dlg_get_rq_reg()
98 rq_regs->rq_regs_c.chunk_size = (dml_uint_t)(dml_log2((dml_float_t) p1_pixel_chunk_bytes) - 10); in dml_rq_dlg_get_rq_reg()
101 rq_regs->rq_regs_l.min_chunk_size = 0; in dml_rq_dlg_get_rq_reg()
103 …rq_regs->rq_regs_l.min_chunk_size = (dml_uint_t)(dml_log2((dml_float_t) min_pixel_chunk_bytes) - 8… in dml_rq_dlg_get_rq_reg()
106 rq_regs->rq_regs_c.min_chunk_size = 0; in dml_rq_dlg_get_rq_reg()
108 …rq_regs->rq_regs_c.min_chunk_size = (dml_uint_t)(dml_log2((dml_float_t) p1_min_pixel_chunk_bytes) … in dml_rq_dlg_get_rq_reg()
110 rq_regs->rq_regs_l.meta_chunk_size = (dml_uint_t)(dml_log2((dml_float_t) meta_chunk_bytes) - 10); in dml_rq_dlg_get_rq_reg()
111 …rq_regs->rq_regs_c.meta_chunk_size = (dml_uint_t)(dml_log2((dml_float_t) p1_meta_chunk_bytes) - 10… in dml_rq_dlg_get_rq_reg()
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H A Ddml2_translation_helper.c1429 void dml2_update_pipe_ctx_dchub_regs(struct _vcs_dpi_dml_display_rq_regs_st *rq_regs, in dml2_update_pipe_ctx_dchub_regs() argument
1434 memset(&out->rq_regs, 0, sizeof(out->rq_regs)); in dml2_update_pipe_ctx_dchub_regs()
1435 out->rq_regs.rq_regs_l.chunk_size = rq_regs->rq_regs_l.chunk_size; in dml2_update_pipe_ctx_dchub_regs()
1436 out->rq_regs.rq_regs_l.min_chunk_size = rq_regs->rq_regs_l.min_chunk_size; in dml2_update_pipe_ctx_dchub_regs()
1437 out->rq_regs.rq_regs_l.meta_chunk_size = rq_regs->rq_regs_l.meta_chunk_size; in dml2_update_pipe_ctx_dchub_regs()
1438 out->rq_regs.rq_regs_l.min_meta_chunk_size = rq_regs->rq_regs_l.min_meta_chunk_size; in dml2_update_pipe_ctx_dchub_regs()
1439 out->rq_regs.rq_regs_l.dpte_group_size = rq_regs->rq_regs_l.dpte_group_size; in dml2_update_pipe_ctx_dchub_regs()
1440 out->rq_regs.rq_regs_l.mpte_group_size = rq_regs->rq_regs_l.mpte_group_size; in dml2_update_pipe_ctx_dchub_regs()
1441 out->rq_regs.rq_regs_l.swath_height = rq_regs->rq_regs_l.swath_height; in dml2_update_pipe_ctx_dchub_regs()
1442 out->rq_regs.rq_regs_l.pte_row_height_linear = rq_regs->rq_regs_l.pte_row_height_linear; in dml2_update_pipe_ctx_dchub_regs()
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H A Ddisplay_mode_util.c218 void dml_print_data_rq_regs_st(const dml_display_plane_rq_regs_st *rq_regs) in dml_print_data_rq_regs_st() argument
222 dml_print("DML: chunk_size = 0x%x\n", rq_regs->chunk_size); in dml_print_data_rq_regs_st()
223 dml_print("DML: min_chunk_size = 0x%x\n", rq_regs->min_chunk_size); in dml_print_data_rq_regs_st()
224 dml_print("DML: meta_chunk_size = 0x%x\n", rq_regs->meta_chunk_size); in dml_print_data_rq_regs_st()
225 dml_print("DML: min_meta_chunk_size = 0x%x\n", rq_regs->min_meta_chunk_size); in dml_print_data_rq_regs_st()
226 dml_print("DML: dpte_group_size = 0x%x\n", rq_regs->dpte_group_size); in dml_print_data_rq_regs_st()
227 dml_print("DML: mpte_group_size = 0x%x\n", rq_regs->mpte_group_size); in dml_print_data_rq_regs_st()
228 dml_print("DML: swath_height = 0x%x\n", rq_regs->swath_height); in dml_print_data_rq_regs_st()
229 dml_print("DML: pte_row_height_linear = 0x%x\n", rq_regs->pte_row_height_linear); in dml_print_data_rq_regs_st()
233 void dml_print_rq_regs_st(const dml_display_rq_regs_st *rq_regs) in dml_print_rq_regs_st() argument
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H A Ddml_display_rq_dlg_calc.h43 void dml_rq_dlg_get_rq_reg(dml_display_rq_regs_st *rq_regs,
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddisplay_rq_dlg_calc_32.c43 void dml32_rq_dlg_get_rq_reg(display_rq_regs_st *rq_regs, in dml32_rq_dlg_get_rq_reg() argument
72 memset(rq_regs, 0, sizeof(*rq_regs)); in dml32_rq_dlg_get_rq_reg()
98 rq_regs->rq_regs_l.chunk_size = dml_log2(pixel_chunk_bytes) - 10; in dml32_rq_dlg_get_rq_reg()
99 rq_regs->rq_regs_c.chunk_size = dml_log2(p1_pixel_chunk_bytes) - 10; in dml32_rq_dlg_get_rq_reg()
102 rq_regs->rq_regs_l.min_chunk_size = 0; in dml32_rq_dlg_get_rq_reg()
104 rq_regs->rq_regs_l.min_chunk_size = dml_log2(min_pixel_chunk_bytes) - 8 + 1; in dml32_rq_dlg_get_rq_reg()
107 rq_regs->rq_regs_c.min_chunk_size = 0; in dml32_rq_dlg_get_rq_reg()
109 rq_regs->rq_regs_c.min_chunk_size = dml_log2(p1_min_pixel_chunk_bytes) - 8 + 1; in dml32_rq_dlg_get_rq_reg()
111 rq_regs->rq_regs_l.meta_chunk_size = dml_log2(meta_chunk_bytes) - 10; in dml32_rq_dlg_get_rq_reg()
112 rq_regs->rq_regs_c.meta_chunk_size = dml_log2(p1_meta_chunk_bytes) - 10; in dml32_rq_dlg_get_rq_reg()
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H A Ddisplay_rq_dlg_calc_32.h44 void dml32_rq_dlg_get_rq_reg(display_rq_regs_st *rq_regs,
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn401/
H A Ddcn401_hubp.c222 struct dml2_display_rq_regs *rq_regs) in hubp401_program_requestor() argument
227 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); in hubp401_program_requestor()
229 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, in hubp401_program_requestor()
230 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, in hubp401_program_requestor()
231 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, in hubp401_program_requestor()
232 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); in hubp401_program_requestor()
234 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, in hubp401_program_requestor()
235 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, in hubp401_program_requestor()
236 DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size, in hubp401_program_requestor()
237 VM_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size, in hubp401_program_requestor()
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/linux/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_hw_sequencer_debug.c206 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; in dcn10_get_rq_states() local
213 …pool->hubps[i]->inst, rq_regs->drq_expansion_mode, rq_regs->prq_expansion_mode, rq_regs->mrq_expan… in dcn10_get_rq_states()
214 rq_regs->crq_expansion_mode, rq_regs->plane1_base_address, rq_regs->rq_regs_l.chunk_size, in dcn10_get_rq_states()
215 rq_regs->rq_regs_l.min_chunk_size, rq_regs->rq_regs_l.meta_chunk_size, in dcn10_get_rq_states()
216 rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs->rq_regs_l.dpte_group_size, in dcn10_get_rq_states()
217 rq_regs->rq_regs_l.mpte_group_size, rq_regs->rq_regs_l.swath_height, in dcn10_get_rq_states()
218 …rq_regs->rq_regs_l.pte_row_height_linear, rq_regs->rq_regs_c.chunk_size, rq_regs->rq_regs_c.min_ch… in dcn10_get_rq_states()
219 rq_regs->rq_regs_c.meta_chunk_size, rq_regs->rq_regs_c.min_meta_chunk_size, in dcn10_get_rq_states()
220 rq_regs->rq_regs_c.dpte_group_size, rq_regs->rq_regs_c.mpte_group_size, in dcn10_get_rq_states()
221 rq_regs->rq_regs_c.swath_height, rq_regs->rq_regs_c.pte_row_height_linear); in dcn10_get_rq_states()
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn30/
H A Ddcn30_hubp.c446 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; in hubp3_read_state() local
451 CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size, in hubp3_read_state()
452 MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size, in hubp3_read_state()
453 META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size, in hubp3_read_state()
454 MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size, in hubp3_read_state()
455 DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size, in hubp3_read_state()
456 SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height, in hubp3_read_state()
457 PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear); in hubp3_read_state()
460 CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size, in hubp3_read_state()
461 MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size, in hubp3_read_state()
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddisplay_rq_dlg_calc_20v2.c166 display_data_rq_regs_st *rq_regs, in extract_rq_sizing_regs() argument
172 rq_regs->chunk_size = dml_log2(rq_sizing->chunk_bytes) - 10; in extract_rq_sizing_regs()
175 rq_regs->min_chunk_size = 0; in extract_rq_sizing_regs()
177 rq_regs->min_chunk_size = dml_log2(rq_sizing->min_chunk_bytes) - 8 + 1; in extract_rq_sizing_regs()
179 rq_regs->meta_chunk_size = dml_log2(rq_sizing->meta_chunk_bytes) - 10; in extract_rq_sizing_regs()
181 rq_regs->min_meta_chunk_size = 0; in extract_rq_sizing_regs()
183 rq_regs->min_meta_chunk_size = dml_log2(rq_sizing->min_meta_chunk_bytes) - 6 + 1; in extract_rq_sizing_regs()
185 rq_regs->dpte_group_size = dml_log2(rq_sizing->dpte_group_bytes) - 6; in extract_rq_sizing_regs()
186 rq_regs->mpte_group_size = dml_log2(rq_sizing->mpte_group_bytes) - 6; in extract_rq_sizing_regs()
190 display_rq_regs_st *rq_regs, in extract_rq_regs() argument
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H A Ddisplay_rq_dlg_calc_20.c166 display_data_rq_regs_st *rq_regs, in extract_rq_sizing_regs() argument
172 rq_regs->chunk_size = dml_log2(rq_sizing->chunk_bytes) - 10; in extract_rq_sizing_regs()
175 rq_regs->min_chunk_size = 0; in extract_rq_sizing_regs()
177 rq_regs->min_chunk_size = dml_log2(rq_sizing->min_chunk_bytes) - 8 + 1; in extract_rq_sizing_regs()
179 rq_regs->meta_chunk_size = dml_log2(rq_sizing->meta_chunk_bytes) - 10; in extract_rq_sizing_regs()
181 rq_regs->min_meta_chunk_size = 0; in extract_rq_sizing_regs()
183 rq_regs->min_meta_chunk_size = dml_log2(rq_sizing->min_meta_chunk_bytes) - 6 + 1; in extract_rq_sizing_regs()
185 rq_regs->dpte_group_size = dml_log2(rq_sizing->dpte_group_bytes) - 6; in extract_rq_sizing_regs()
186 rq_regs->mpte_group_size = dml_log2(rq_sizing->mpte_group_bytes) - 6; in extract_rq_sizing_regs()
190 display_rq_regs_st *rq_regs, in extract_rq_regs() argument
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H A Ddisplay_rq_dlg_calc_20.h45 display_rq_regs_st *rq_regs,
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn21/
H A Ddisplay_rq_dlg_calc_21.c143 display_data_rq_regs_st *rq_regs, in extract_rq_sizing_regs() argument
149 rq_regs->chunk_size = dml_log2(rq_sizing->chunk_bytes) - 10; in extract_rq_sizing_regs()
152 rq_regs->min_chunk_size = 0; in extract_rq_sizing_regs()
154 rq_regs->min_chunk_size = dml_log2(rq_sizing->min_chunk_bytes) - 8 + 1; in extract_rq_sizing_regs()
156 rq_regs->meta_chunk_size = dml_log2(rq_sizing->meta_chunk_bytes) - 10; in extract_rq_sizing_regs()
158 rq_regs->min_meta_chunk_size = 0; in extract_rq_sizing_regs()
160 rq_regs->min_meta_chunk_size = dml_log2(rq_sizing->min_meta_chunk_bytes) - 6 + 1; in extract_rq_sizing_regs()
162 rq_regs->dpte_group_size = dml_log2(rq_sizing->dpte_group_bytes) - 6; in extract_rq_sizing_regs()
163 rq_regs->mpte_group_size = dml_log2(rq_sizing->mpte_group_bytes) - 6; in extract_rq_sizing_regs()
168 display_rq_regs_st *rq_regs, in extract_rq_regs() argument
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddisplay_rq_dlg_calc_31.c91 …_sizing_regs(struct display_mode_lib *mode_lib, display_data_rq_regs_st *rq_regs, const display_da… in extract_rq_sizing_regs() argument
95 rq_regs->chunk_size = dml_log2(rq_sizing->chunk_bytes) - 10; in extract_rq_sizing_regs()
98 rq_regs->min_chunk_size = 0; in extract_rq_sizing_regs()
100 rq_regs->min_chunk_size = dml_log2(rq_sizing->min_chunk_bytes) - 8 + 1; in extract_rq_sizing_regs()
102 rq_regs->meta_chunk_size = dml_log2(rq_sizing->meta_chunk_bytes) - 10; in extract_rq_sizing_regs()
104 rq_regs->min_meta_chunk_size = 0; in extract_rq_sizing_regs()
106 rq_regs->min_meta_chunk_size = dml_log2(rq_sizing->min_meta_chunk_bytes) - 6 + 1; in extract_rq_sizing_regs()
108 rq_regs->dpte_group_size = dml_log2(rq_sizing->dpte_group_bytes) - 6; in extract_rq_sizing_regs()
109 rq_regs->mpte_group_size = dml_log2(rq_sizing->mpte_group_bytes) - 6; in extract_rq_sizing_regs()
112 static void extract_rq_regs(struct display_mode_lib *mode_lib, display_rq_regs_st *rq_regs, const d… in extract_rq_regs() argument
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddisplay_rq_dlg_calc_30.c90 display_data_rq_regs_st *rq_regs, in extract_rq_sizing_regs() argument
96 rq_regs->chunk_size = dml_log2(rq_sizing->chunk_bytes) - 10; in extract_rq_sizing_regs()
99 rq_regs->min_chunk_size = 0; in extract_rq_sizing_regs()
101 rq_regs->min_chunk_size = dml_log2(rq_sizing->min_chunk_bytes) - 8 + 1; in extract_rq_sizing_regs()
103 rq_regs->meta_chunk_size = dml_log2(rq_sizing->meta_chunk_bytes) - 10; in extract_rq_sizing_regs()
105 rq_regs->min_meta_chunk_size = 0; in extract_rq_sizing_regs()
107 rq_regs->min_meta_chunk_size = dml_log2(rq_sizing->min_meta_chunk_bytes) - 6 + 1; in extract_rq_sizing_regs()
109 rq_regs->dpte_group_size = dml_log2(rq_sizing->dpte_group_bytes) - 6; in extract_rq_sizing_regs()
110 rq_regs->mpte_group_size = dml_log2(rq_sizing->mpte_group_bytes) - 6; in extract_rq_sizing_regs()
114 display_rq_regs_st *rq_regs, in extract_rq_regs() argument
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/
H A Ddisplay_rq_dlg_calc_314.c179 …_sizing_regs(struct display_mode_lib *mode_lib, display_data_rq_regs_st *rq_regs, const display_da… in extract_rq_sizing_regs() argument
183 rq_regs->chunk_size = dml_log2(rq_sizing->chunk_bytes) - 10; in extract_rq_sizing_regs()
186 rq_regs->min_chunk_size = 0; in extract_rq_sizing_regs()
188 rq_regs->min_chunk_size = dml_log2(rq_sizing->min_chunk_bytes) - 8 + 1; in extract_rq_sizing_regs()
190 rq_regs->meta_chunk_size = dml_log2(rq_sizing->meta_chunk_bytes) - 10; in extract_rq_sizing_regs()
192 rq_regs->min_meta_chunk_size = 0; in extract_rq_sizing_regs()
194 rq_regs->min_meta_chunk_size = dml_log2(rq_sizing->min_meta_chunk_bytes) - 6 + 1; in extract_rq_sizing_regs()
196 rq_regs->dpte_group_size = dml_log2(rq_sizing->dpte_group_bytes) - 6; in extract_rq_sizing_regs()
197 rq_regs->mpte_group_size = dml_log2(rq_sizing->mpte_group_bytes) - 6; in extract_rq_sizing_regs()
200 static void extract_rq_regs(struct display_mode_lib *mode_lib, display_rq_regs_st *rq_regs, const d… in extract_rq_regs() argument
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H A Ddisplay_rq_dlg_calc_314.h44 display_rq_regs_st *rq_regs,

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