1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */ 2 /* Copyright(c) 2014 - 2020 Intel Corporation */ 3 #ifndef _ICP_QAT_FW_INIT_ADMIN_H_ 4 #define _ICP_QAT_FW_INIT_ADMIN_H_ 5 6 #include "icp_qat_fw.h" 7 8 #define RL_MAX_RP_IDS 16 9 10 enum icp_qat_fw_init_admin_cmd_id { 11 ICP_QAT_FW_INIT_AE = 0, 12 ICP_QAT_FW_TRNG_ENABLE = 1, 13 ICP_QAT_FW_TRNG_DISABLE = 2, 14 ICP_QAT_FW_CONSTANTS_CFG = 3, 15 ICP_QAT_FW_STATUS_GET = 4, 16 ICP_QAT_FW_COUNTERS_GET = 5, 17 ICP_QAT_FW_LOOPBACK = 6, 18 ICP_QAT_FW_HEARTBEAT_SYNC = 7, 19 ICP_QAT_FW_HEARTBEAT_GET = 8, 20 ICP_QAT_FW_COMP_CAPABILITY_GET = 9, 21 ICP_QAT_FW_CRYPTO_CAPABILITY_GET = 10, 22 ICP_QAT_FW_DC_CHAIN_INIT = 11, 23 ICP_QAT_FW_HEARTBEAT_TIMER_SET = 13, 24 ICP_QAT_FW_RL_INIT = 15, 25 ICP_QAT_FW_TIMER_GET = 19, 26 ICP_QAT_FW_CNV_STATS_GET = 20, 27 ICP_QAT_FW_PM_STATE_CONFIG = 128, 28 ICP_QAT_FW_PM_INFO = 129, 29 ICP_QAT_FW_RL_ADD = 134, 30 ICP_QAT_FW_RL_UPDATE = 135, 31 ICP_QAT_FW_RL_REMOVE = 136, 32 ICP_QAT_FW_TL_START = 137, 33 ICP_QAT_FW_TL_STOP = 138, 34 ICP_QAT_FW_SVN_READ = 146, 35 ICP_QAT_FW_SVN_COMMIT = 147, 36 }; 37 38 enum icp_qat_fw_init_admin_resp_status { 39 ICP_QAT_FW_INIT_RESP_STATUS_SUCCESS = 0, 40 ICP_QAT_FW_INIT_RESP_STATUS_FAIL = 1, 41 ICP_QAT_FW_INIT_RESP_STATUS_RETRY = 2, 42 ICP_QAT_FW_INIT_RESP_STATUS_UNSUPPORTED = 4, 43 }; 44 45 struct icp_qat_fw_init_admin_tl_rp_indexes { 46 __u8 rp_num_index_0; 47 __u8 rp_num_index_1; 48 __u8 rp_num_index_2; 49 __u8 rp_num_index_3; 50 }; 51 52 struct icp_qat_fw_init_admin_slice_cnt { 53 __u8 cpr_cnt; 54 __u8 xlt_cnt; 55 __u8 dcpr_cnt; 56 __u8 pke_cnt; 57 __u8 wat_cnt; 58 __u8 wcp_cnt; 59 __u8 ucs_cnt; 60 __u8 cph_cnt; 61 __u8 ath_cnt; 62 }; 63 64 struct icp_qat_fw_init_admin_sla_config_params { 65 __u32 pcie_in_cir; 66 __u32 pcie_in_pir; 67 __u32 pcie_out_cir; 68 __u32 pcie_out_pir; 69 __u32 slice_util_cir; 70 __u32 slice_util_pir; 71 __u32 ae_util_cir; 72 __u32 ae_util_pir; 73 __u16 rp_ids[RL_MAX_RP_IDS]; 74 }; 75 76 struct icp_qat_fw_init_admin_req { 77 __u16 init_cfg_sz; 78 __u8 resrvd1; 79 __u8 cmd_id; 80 __u32 resrvd2; 81 __u64 opaque_data; 82 __u64 init_cfg_ptr; 83 84 union { 85 struct { 86 __u16 ibuf_size_in_kb; 87 __u16 resrvd3; 88 }; 89 struct { 90 __u32 int_timer_ticks; 91 }; 92 struct { 93 __u32 heartbeat_ticks; 94 }; 95 struct { 96 __u16 node_id; 97 __u8 node_type; 98 __u8 svc_type; 99 __u8 resrvd5[3]; 100 __u8 rp_count; 101 }; 102 __u32 idle_filter; 103 struct icp_qat_fw_init_admin_tl_rp_indexes rp_indexes; 104 }; 105 106 __u32 resrvd4; 107 } __packed; 108 109 struct icp_qat_fw_init_admin_resp { 110 __u8 flags; 111 __u8 resrvd1; 112 __u8 status; 113 __u8 cmd_id; 114 union { 115 __u32 resrvd2; 116 struct { 117 __u16 version_minor_num; 118 __u16 version_major_num; 119 }; 120 __u32 extended_features; 121 struct { 122 __u16 error_count; 123 __u16 latest_error; 124 }; 125 }; 126 __u64 opaque_data; 127 union { 128 __u32 resrvd3[ICP_QAT_FW_NUM_LONGWORDS_4]; 129 struct { 130 __u32 version_patch_num; 131 __u8 context_id; 132 __u8 ae_id; 133 __u16 resrvd4; 134 __u64 resrvd5; 135 }; 136 struct { 137 __u64 req_rec_count; 138 __u64 resp_sent_count; 139 }; 140 struct { 141 __u16 compression_algos; 142 __u16 checksum_algos; 143 __u32 deflate_capabilities; 144 __u32 resrvd6; 145 __u32 lzs_capabilities; 146 }; 147 struct { 148 __u32 cipher_algos; 149 __u32 hash_algos; 150 __u16 keygen_algos; 151 __u16 other; 152 __u16 public_key_algos; 153 __u16 prime_algos; 154 }; 155 struct { 156 __u64 timestamp; 157 __u64 resrvd7; 158 }; 159 struct { 160 __u32 successful_count; 161 __u32 unsuccessful_count; 162 __u64 resrvd8; 163 }; 164 struct icp_qat_fw_init_admin_slice_cnt slices; 165 __u16 fw_capabilities; 166 struct { 167 __u8 enforced_min_svn; 168 __u8 permanent_min_svn; 169 __u8 active_svn; 170 __u8 resrvd9; 171 __u16 svn_status; 172 __u16 resrvd10; 173 __u64 resrvd11; 174 }; 175 }; 176 } __packed; 177 178 #define ICP_QAT_FW_SYNC ICP_QAT_FW_HEARTBEAT_SYNC 179 #define ICP_QAT_FW_CAPABILITIES_GET ICP_QAT_FW_CRYPTO_CAPABILITY_GET 180 181 #define ICP_QAT_NUMBER_OF_PM_EVENTS 8 182 183 struct icp_qat_fw_init_admin_pm_info { 184 __u16 max_pwrreq; 185 __u16 min_pwrreq; 186 __u16 resvrd1; 187 __u8 pwr_state; 188 __u8 resvrd2; 189 __u32 fusectl0; 190 struct_group(event_counters, 191 __u32 sys_pm; 192 __u32 host_msg; 193 __u32 unknown; 194 __u32 local_ssm; 195 __u32 timer; 196 ); 197 __u32 event_log[ICP_QAT_NUMBER_OF_PM_EVENTS]; 198 struct_group(pm, 199 __u32 fw_init; 200 __u32 pwrreq; 201 __u32 status; 202 __u32 main; 203 __u32 thread; 204 ); 205 struct_group(ssm, 206 __u32 pm_enable; 207 __u32 pm_active_status; 208 __u32 pm_managed_status; 209 __u32 pm_domain_status; 210 __u32 active_constraint; 211 ); 212 __u32 resvrd3[6]; 213 }; 214 215 #endif 216