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Searched refs:regmap_write (Results 1 – 25 of 1341) sorted by relevance

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/linux/drivers/phy/qualcomm/
H A Dphy-qcom-sgmii-eth.c36 regmap_write(regmap, QSERDES_PCS + QPHY_PCS_SW_RESET, 0x01); in qcom_dwmac_sgmii_phy_init_1g()
37 regmap_write(regmap, QSERDES_PCS + QPHY_PCS_POWER_DOWN_CONTROL, 0x01); in qcom_dwmac_sgmii_phy_init_1g()
39 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_PLL_IVCO, 0x0F); in qcom_dwmac_sgmii_phy_init_1g()
40 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_CP_CTRL_MODE0, 0x06); in qcom_dwmac_sgmii_phy_init_1g()
41 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16); in qcom_dwmac_sgmii_phy_init_1g()
42 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36); in qcom_dwmac_sgmii_phy_init_1g()
43 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1A); in qcom_dwmac_sgmii_phy_init_1g()
44 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0A); in qcom_dwmac_sgmii_phy_init_1g()
45 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1A); in qcom_dwmac_sgmii_phy_init_1g()
46 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_DEC_START_MODE0, 0x82); in qcom_dwmac_sgmii_phy_init_1g()
[all …]
/linux/drivers/gpu/drm/sprd/
H A Dmegacores_pll.c102 regmap_write(regmap, reg_addr[i], reg_val[i]); in dphy_set_pll_reg()
131 regmap_write(regmap, 0x31, val[CLK]); in dphy_set_timing_reg()
132 regmap_write(regmap, 0x41, val[DATA]); in dphy_set_timing_reg()
133 regmap_write(regmap, 0x51, val[DATA]); in dphy_set_timing_reg()
134 regmap_write(regmap, 0x61, val[DATA]); in dphy_set_timing_reg()
135 regmap_write(regmap, 0x71, val[DATA]); in dphy_set_timing_reg()
137 regmap_write(regmap, 0x90, val[CLK]); in dphy_set_timing_reg()
138 regmap_write(regmap, 0xa0, val[DATA]); in dphy_set_timing_reg()
139 regmap_write(regmap, 0xb0, val[DATA]); in dphy_set_timing_reg()
140 regmap_write(regmap, 0xc0, val[DATA]); in dphy_set_timing_reg()
[all …]
/linux/sound/soc/codecs/
H A Des8389.c615 regmap_write(es8389->regmap, ES8389_CLK_DIV1, coeff_div[coeff].Reg0x04); in es8389_set_bias_level()
616 regmap_write(es8389->regmap, ES8389_CLK_MUL, coeff_div[coeff].Reg0x05); in es8389_set_bias_level()
617 regmap_write(es8389->regmap, ES8389_CLK_MUX1, coeff_div[coeff].Reg0x06); in es8389_set_bias_level()
618 regmap_write(es8389->regmap, ES8389_CLK_MUX2, coeff_div[coeff].Reg0x07); in es8389_set_bias_level()
619 regmap_write(es8389->regmap, ES8389_CLK_CTL1, coeff_div[coeff].Reg0x08); in es8389_set_bias_level()
620 regmap_write(es8389->regmap, ES8389_CLK_CTL2, coeff_div[coeff].Reg0x09); in es8389_set_bias_level()
621 regmap_write(es8389->regmap, ES8389_CLK_CTL3, coeff_div[coeff].Reg0x0A); in es8389_set_bias_level()
624 regmap_write(es8389->regmap, ES8389_CLK_DIV2, coeff_div[coeff].Reg0x11); in es8389_set_bias_level()
625 regmap_write(es8389->regmap, ES8389_ADC_OSR, coeff_div[coeff].Reg0x21); in es8389_set_bias_level()
626 regmap_write(es838 in es8389_set_bias_level()
[all...]
H A Des8326.c81 regmap_write(es8326->regmap, ES8326_DAC_CROSSTALK, crosstalk_l); in es8326_crosstalk1_set()
119 regmap_write(es8326->regmap, ES8326_DAC_CROSSTALK, crosstalk_l); in es8326_crosstalk2_set()
593 regmap_write(es8326->regmap, ES8326_CLK_DIV1, in es8326_pcm_hw_params()
595 regmap_write(es8326->regmap, ES8326_CLK_DIV2, in es8326_pcm_hw_params()
597 regmap_write(es8326->regmap, ES8326_CLK_DLL, in es8326_pcm_hw_params()
599 regmap_write(es8326->regmap, ES8326_CLK_MUX, in es8326_pcm_hw_params()
601 regmap_write(es8326->regmap, ES8326_CLK_ADC_SEL, in es8326_mute()
603 regmap_write(es8326->regmap, ES8326_CLK_DAC_SEL, in es8326_mute()
605 regmap_write(es8326->regmap, ES8326_CLK_ADC_OSR, in es8326_mute()
607 regmap_write(es832 in es8326_mute()
[all...]
H A Des8375.c324 regmap_write(es8375->regmap, ES8375_CLK_MGR4, in es8375_hw_params()
326 regmap_write(es8375->regmap, ES8375_CLK_MGR5, in es8375_hw_params()
328 regmap_write(es8375->regmap, ES8375_CLK_MGR6, in es8375_hw_params()
330 regmap_write(es8375->regmap, ES8375_CLK_MGR7, in es8375_hw_params()
332 regmap_write(es8375->regmap, ES8375_CLK_MGR8, in es8375_hw_params()
334 regmap_write(es8375->regmap, ES8375_CLK_MGR9, in es8375_hw_params()
336 regmap_write(es8375->regmap, ES8375_CLK_MGR10, in es8375_hw_params()
338 regmap_write(es8375->regmap, ES8375_CLK_MGR11, in es8375_hw_params()
340 regmap_write(es8375->regmap, ES8375_ADC_OSR_GAIN, in es8375_hw_params()
439 regmap_write(es837 in es8375_set_dai_fmt()
[all...]
H A Dmt6358.c229 regmap_write(priv->regmap, MT6358_ZCD_CON0, 0x0000); in hp_zcd_disable()
825 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0006); in mt_sgen_event()
827 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xCBA1); in mt_sgen_event()
829 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0003); in mt_sgen_event()
831 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x000B); in mt_sgen_event()
842 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0000); in mt_sgen_event()
843 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xcba0); in mt_sgen_event()
867 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0006); in mt_aif_in_event()
869 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xCBA1); in mt_aif_in_event()
871 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0003); in mt_aif_in_event()
[all …]
H A Drt1305.c393 regmap_write(regmap, RT1305_RESET, 0); in rt1305_reset()
999 regmap_write(rt1305->regmap, RT1305_ADC_SET_3, 0x0219); in rt1305_calibrate()
1000 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xcf, 0x5548); in rt1305_calibrate()
1001 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xc1, 0x0320); in rt1305_calibrate()
1002 regmap_write(rt1305->regmap, RT1305_CLOCK_DETECT, 0x1000); in rt1305_calibrate()
1003 regmap_write(rt1305->regmap, RT1305_CLK_1, 0x0600); in rt1305_calibrate()
1004 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xffd0); in rt1305_calibrate()
1005 regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0080); in rt1305_calibrate()
1006 regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0880); in rt1305_calibrate()
1007 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x0dfe); in rt1305_calibrate()
[all …]
H A Drt700.c38 ret = regmap_write(regmap, addr, value); in rt700_index_write()
279 regmap_write(rt700->regmap, in rt700_jack_init()
284 regmap_write(rt700->regmap, in rt700_jack_init()
286 regmap_write(rt700->regmap, in rt700_jack_init()
288 regmap_write(rt700->regmap, in rt700_jack_init()
298 regmap_write(rt700->regmap, in rt700_jack_init()
300 regmap_write(rt700->regmap, in rt700_jack_init()
302 regmap_write(rt700->regmap, in rt700_jack_init()
310 regmap_write(rt700->regmap, in rt700_jack_init()
400 regmap_write(rt700->regmap, in rt700_set_amp_gain_put()
[all …]
H A Drt715.c41 ret = regmap_write(regmap, addr, value); in rt715_index_write()
56 ret = regmap_write(regmap, addr, value); in rt715_index_write_nid()
97 regmap_write(regmap, RT715_FUNC_RESET, 0); in rt715_reset()
155 regmap_write(rt715->regmap, in rt715_set_amp_gain_put()
181 regmap_write(rt715->regmap, addr_h, in rt715_set_amp_gain_put()
183 regmap_write(rt715->regmap, addr_l, in rt715_set_amp_gain_put()
188 regmap_write(rt715->regmap, addr_h, in rt715_set_amp_gain_put()
192 regmap_write(rt715->regmap, addr_l, in rt715_set_amp_gain_put()
209 regmap_write(rt715->regmap, in rt715_set_amp_gain_put()
276 regmap_write(rt715->regmap, in rt715_set_main_switch_put()
[all …]
H A Drt711.c38 ret = regmap_write(regmap, addr, value); in rt711_index_write()
79 regmap_write(regmap, RT711_FUNC_RESET, 0); in rt711_reset()
93 regmap_write(rt711->regmap, in rt711_calibration()
129 regmap_write(rt711->regmap, in rt711_calibration()
368 regmap_write(rt711->regmap, in rt711_jack_init()
373 regmap_write(rt711->regmap, in rt711_jack_init()
375 regmap_write(rt711->regmap, in rt711_jack_init()
377 regmap_write(rt711->regmap, in rt711_jack_init()
439 regmap_write(rt711->regmap, in rt711_jack_init()
441 regmap_write(rt711->regmap, in rt711_jack_init()
[all …]
H A Drt1308-sdw.c115 regmap_write(rt1308->regmap, 0xe0, value); in rt1308_clock_config()
116 regmap_write(rt1308->regmap, 0xf0, value); in rt1308_clock_config()
173 regmap_write(rt1308->regmap, 0xc7f0, 0x04); in rt1308_apply_calib_params()
174 regmap_write(rt1308->regmap, 0xc7f1, 0xfe); in rt1308_apply_calib_params()
176 regmap_write(rt1308->regmap, 0xc7f0, 0x44); in rt1308_apply_calib_params()
178 regmap_write(rt1308->regmap, 0xc240, 0x10); in rt1308_apply_calib_params()
209 regmap_write(rt1308->regmap, reg, data); in rt1308_apply_bq_params()
240 regmap_write(rt1308->regmap, RT1308_SDW_RESET, 0); in rt1308_io_init()
247 regmap_write(rt1308->regmap, 0xc103, 0xc0); in rt1308_io_init()
248 regmap_write(rt1308->regmap, 0xc030, 0x17); in rt1308_io_init()
[all …]
/linux/drivers/gpu/drm/bridge/adv7511/
H A Dadv7533.c42 regmap_write(adv->regmap_cec, 0x16, in adv7533_dsi_config_timing_gen()
46 regmap_write(adv->regmap_cec, 0x28, mode->htotal >> 4); in adv7533_dsi_config_timing_gen()
47 regmap_write(adv->regmap_cec, 0x29, (mode->htotal << 4) & 0xff); in adv7533_dsi_config_timing_gen()
48 regmap_write(adv->regmap_cec, 0x2a, hsw >> 4); in adv7533_dsi_config_timing_gen()
49 regmap_write(adv->regmap_cec, 0x2b, (hsw << 4) & 0xff); in adv7533_dsi_config_timing_gen()
50 regmap_write(adv->regmap_cec, 0x2c, hfp >> 4); in adv7533_dsi_config_timing_gen()
51 regmap_write(adv->regmap_cec, 0x2d, (hfp << 4) & 0xff); in adv7533_dsi_config_timing_gen()
52 regmap_write(adv->regmap_cec, 0x2e, hbp >> 4); in adv7533_dsi_config_timing_gen()
53 regmap_write(adv->regmap_cec, 0x2f, (hbp << 4) & 0xff); in adv7533_dsi_config_timing_gen()
56 regmap_write(adv->regmap_cec, 0x30, mode->vtotal >> 4); in adv7533_dsi_config_timing_gen()
[all …]
/linux/drivers/media/tuners/
H A Dm88rs6000t.c108 ret = regmap_write(dev->regmap, 0x05, 0x40); in m88rs6000t_set_demod_mclk()
111 ret = regmap_write(dev->regmap, 0x11, 0x08); in m88rs6000t_set_demod_mclk()
114 ret = regmap_write(dev->regmap, 0x15, reg15); in m88rs6000t_set_demod_mclk()
117 ret = regmap_write(dev->regmap, 0x16, reg16); in m88rs6000t_set_demod_mclk()
120 ret = regmap_write(dev->regmap, 0x1D, reg1D); in m88rs6000t_set_demod_mclk()
123 ret = regmap_write(dev->regmap, 0x1E, reg1E); in m88rs6000t_set_demod_mclk()
126 ret = regmap_write(dev->regmap, 0x1F, reg1F); in m88rs6000t_set_demod_mclk()
129 ret = regmap_write(dev->regmap, 0x17, 0xc1); in m88rs6000t_set_demod_mclk()
132 ret = regmap_write(dev->regmap, 0x17, 0x81); in m88rs6000t_set_demod_mclk()
136 ret = regmap_write(dev->regmap, 0x05, 0x00); in m88rs6000t_set_demod_mclk()
[all …]
/linux/drivers/gpu/drm/bridge/
H A Dchrontel-ch7033.c338 regmap_write(priv->regmap, 0x03, 0x04); in ch7033_bridge_disable()
346 regmap_write(priv->regmap, 0x03, 0x04); in ch7033_bridge_enable()
363 regmap_write(priv->regmap, 0x03, 0x04); in ch7033_bridge_mode_set()
366 regmap_write(priv->regmap, 0x52, 0x00); in ch7033_bridge_mode_set()
368 regmap_write(priv->regmap, 0x52, RESETIB); in ch7033_bridge_mode_set()
373 regmap_write(priv->regmap, 0x03, 0x00); in ch7033_bridge_mode_set()
383 regmap_write(priv->regmap, 0x0b, (mode->htotal >> 8) << 3 | in ch7033_bridge_mode_set()
385 regmap_write(priv->regmap, 0x0c, mode->hdisplay); in ch7033_bridge_mode_set()
386 regmap_write(priv->regmap, 0x0d, mode->htotal); in ch7033_bridge_mode_set()
387 regmap_write(priv->regmap, 0x0e, (hsynclen >> 8) << 3 | in ch7033_bridge_mode_set()
[all …]
/linux/drivers/media/dvb-frontends/
H A Drtl2832_sdr.c550 ret = regmap_write(dev->regmap, 0x1b1, u8tmp1); in rtl2832_sdr_set_adc()
554 ret = regmap_write(dev->regmap, 0x008, u8tmp2); in rtl2832_sdr_set_adc()
558 ret = regmap_write(dev->regmap, 0x006, 0x80); in rtl2832_sdr_set_adc()
585 ret = regmap_write(dev->regmap, 0x019, 0x05); in rtl2832_sdr_set_adc()
600 ret = regmap_write(dev->regmap, 0x061, 0x60); in rtl2832_sdr_set_adc()
607 ret = regmap_write(dev->regmap, 0x112, 0x5a); in rtl2832_sdr_set_adc()
608 ret = regmap_write(dev->regmap, 0x102, 0x40); in rtl2832_sdr_set_adc()
609 ret = regmap_write(dev->regmap, 0x103, 0x5a); in rtl2832_sdr_set_adc()
610 ret = regmap_write(dev->regmap, 0x1c7, 0x30); in rtl2832_sdr_set_adc()
611 ret = regmap_write(dev->regmap, 0x104, 0xd0); in rtl2832_sdr_set_adc()
[all …]
H A Dts2020.c68 ret = regmap_write(priv->regmap, u8tmp, 0x00); in ts2020_sleep()
86 regmap_write(priv->regmap, 0x42, 0x73); in ts2020_init()
87 regmap_write(priv->regmap, 0x05, priv->clk_out_div); in ts2020_init()
88 regmap_write(priv->regmap, 0x20, 0x27); in ts2020_init()
89 regmap_write(priv->regmap, 0x07, 0x02); in ts2020_init()
90 regmap_write(priv->regmap, 0x11, 0xff); in ts2020_init()
91 regmap_write(priv->regmap, 0x60, 0xf9); in ts2020_init()
92 regmap_write(priv->regmap, 0x08, 0x01); in ts2020_init()
93 regmap_write(priv->regmap, 0x00, 0x41); in ts2020_init()
109 regmap_write(priv->regmap, 0x00, 0x01); in ts2020_init()
[all …]
/linux/drivers/iio/imu/inv_mpu6050/
H A Dinv_mpu_aux.c32 ret = regmap_write(st->map, st->reg->sample_rate_div, d); in inv_mpu_i2c_master_xfer()
38 ret = regmap_write(st->map, st->reg->user_ctrl, user_ctrl); in inv_mpu_i2c_master_xfer()
47 ret = regmap_write(st->map, st->reg->user_ctrl, user_ctrl); in inv_mpu_i2c_master_xfer()
53 ret = regmap_write(st->map, st->reg->sample_rate_div, d); in inv_mpu_i2c_master_xfer()
58 ret = regmap_write(st->map, INV_MPU6050_REG_I2C_SLV_CTRL(0), 0); in inv_mpu_i2c_master_xfer()
73 regmap_write(st->map, st->reg->user_ctrl, st->chip_config.user_ctrl); in inv_mpu_i2c_master_xfer()
75 regmap_write(st->map, st->reg->sample_rate_div, st->chip_config.divider); in inv_mpu_i2c_master_xfer()
77 regmap_write(st->map, INV_MPU6050_REG_I2C_SLV_CTRL(0), 0); in inv_mpu_i2c_master_xfer()
108 ret = regmap_write(st->map, INV_MPU6050_REG_I2C_MST_CTRL, val); in inv_mpu_aux_init()
113 ret = regmap_write(st->map, INV_MPU6050_REG_I2C_SLV4_CTRL, 0); in inv_mpu_aux_init()
[all …]
/linux/drivers/gpu/drm/sun4i/
H A Dsun8i_vi_scaler.c893 regmap_write(map, SUN8I_SCALER_VSU_YHCOEFF0(base, i), in sun8i_vi_scaler_set_coeff()
895 regmap_write(map, SUN8I_SCALER_VSU_YHCOEFF1(base, i), in sun8i_vi_scaler_set_coeff()
897 regmap_write(map, SUN8I_SCALER_VSU_CHCOEFF0(base, i), in sun8i_vi_scaler_set_coeff()
899 regmap_write(map, SUN8I_SCALER_VSU_CHCOEFF1(base, i), in sun8i_vi_scaler_set_coeff()
906 regmap_write(map, SUN8I_SCALER_VSU_YVCOEFF(base, i), in sun8i_vi_scaler_set_coeff()
908 regmap_write(map, SUN8I_SCALER_VSU_CVCOEFF(base, i), in sun8i_vi_scaler_set_coeff()
925 regmap_write(layer->regs, in sun8i_vi_scaler_enable()
970 regmap_write(layer->regs, in sun8i_vi_scaler_setup()
974 regmap_write(layer->regs, in sun8i_vi_scaler_setup()
976 regmap_write(layer->regs, in sun8i_vi_scaler_setup()
[all …]
H A Dsun4i_frontend.c90 regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_HORZCOEF0_REG(i), in sun4i_frontend_scaler_init()
92 regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_HORZCOEF0_REG(i), in sun4i_frontend_scaler_init()
94 regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_HORZCOEF1_REG(i), in sun4i_frontend_scaler_init()
96 regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_HORZCOEF1_REG(i), in sun4i_frontend_scaler_init()
98 regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_VERTCOEF_REG(i), in sun4i_frontend_scaler_init()
100 regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_VERTCOEF_REG(i), in sun4i_frontend_scaler_init()
180 regmap_write(frontend->regs, SUN4I_FRONTEND_TB_OFF0_REG, in sun4i_frontend_update_buffer()
187 regmap_write(frontend->regs, SUN4I_FRONTEND_TB_OFF1_REG, in sun4i_frontend_update_buffer()
195 regmap_write(frontend->regs, SUN4I_FRONTEND_TB_OFF2_REG, in sun4i_frontend_update_buffer()
210 regmap_write(frontend->regs, SUN4I_FRONTEND_LINESTRD0_REG, in sun4i_frontend_update_buffer()
[all …]
/linux/drivers/power/reset/
H A Darm-versatile-reboot.c79 regmap_write(syscon_regmap, INTEGRATOR_HDR_LOCK_OFFSET, in versatile_reboot()
87 regmap_write(syscon_regmap, VERSATILE_SYS_LOCK_OFFSET, in versatile_reboot()
93 regmap_write(syscon_regmap, VERSATILE_SYS_LOCK_OFFSET, in versatile_reboot()
97 regmap_write(syscon_regmap, VERSATILE_SYS_LOCK_OFFSET, in versatile_reboot()
99 regmap_write(syscon_regmap, in versatile_reboot()
103 regmap_write(syscon_regmap, VERSATILE_SYS_LOCK_OFFSET, in versatile_reboot()
105 regmap_write(syscon_regmap, in versatile_reboot()
110 regmap_write(syscon_regmap, VERSATILE_SYS_LOCK_OFFSET, in versatile_reboot()
112 regmap_write(syscon_regmap, VERSATILE_SYS_RESETCTL_OFFSET, in versatile_reboot()
114 regmap_write(syscon_regmap, VERSATILE_SYS_RESETCTL_OFFSET, in versatile_reboot()
[all …]
/linux/drivers/phy/allwinner/
H A Dphy-sun6i-mipi-dphy.c229 regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG, in sun6i_a31_mipi_dphy_tx_power_on()
236 regmap_write(dphy->regs, SUN6I_DPHY_ANA1_REG, in sun6i_a31_mipi_dphy_tx_power_on()
240 regmap_write(dphy->regs, SUN6I_DPHY_ANA4_REG, in sun6i_a31_mipi_dphy_tx_power_on()
251 regmap_write(dphy->regs, SUN6I_DPHY_ANA2_REG, in sun6i_a31_mipi_dphy_tx_power_on()
255 regmap_write(dphy->regs, SUN6I_DPHY_ANA3_REG, in sun6i_a31_mipi_dphy_tx_power_on()
267 regmap_write(dphy->regs, SUN6I_DPHY_ANA4_REG, in sun50i_a100_mipi_dphy_tx_power_on()
287 regmap_write(dphy->regs, SUN6I_DPHY_ANA3_REG, in sun50i_a100_mipi_dphy_tx_power_on()
292 regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG, in sun50i_a100_mipi_dphy_tx_power_on()
296 regmap_write(dphy->regs, SUN50I_COMBO_PHY_REG0, in sun50i_a100_mipi_dphy_tx_power_on()
303 regmap_write(dphy->regs, SUN50I_DPHY_PLL_REG0, in sun50i_a100_mipi_dphy_tx_power_on()
[all …]
/linux/drivers/gpu/drm/meson/
H A Dmeson_vclk.c246 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x5800023d); in meson_venci_cvbs_clock_config()
247 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00404e00); in meson_venci_cvbs_clock_config()
248 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x0d5c5091); in meson_venci_cvbs_clock_config()
249 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x801da72c); in meson_venci_cvbs_clock_config()
250 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980); in meson_venci_cvbs_clock_config()
251 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x00000e55); in meson_venci_cvbs_clock_config()
252 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x4800023d); in meson_venci_cvbs_clock_config()
259 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x4000027b); in meson_venci_cvbs_clock_config()
260 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb300); in meson_venci_cvbs_clock_config()
261 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0xa6212844); in meson_venci_cvbs_clock_config()
[all …]
/linux/sound/soc/uniphier/
H A Daio-core.c91 regmap_write(r, SG_AOUTEN, (enable) ? ~0 : 0); in aio_iecout_set_enable()
205 regmap_write(r, A2RBNMAPCTR0(sub->swm->rb.hw), in aio_init()
207 regmap_write(r, A2CHNMAPCTR0(sub->swm->ch.hw), in aio_init()
215 regmap_write(r, A2IIFNMAPCTR0(sub->swm->iif.hw), in aio_init()
217 regmap_write(r, A2IPORTNMAPCTR0(sub->swm->iport.hw), in aio_init()
220 regmap_write(r, A2OIFNMAPCTR0(sub->swm->oif.hw), in aio_init()
222 regmap_write(r, A2OPORTNMAPCTR0(sub->swm->oport.hw), in aio_init()
227 regmap_write(r, A2OIFNMAPCTR0(sub->swm->oif.hw), in aio_init()
229 regmap_write(r, A2OPORTNMAPCTR0(sub->swm->oport.hw), in aio_init()
231 regmap_write(r, A2CHNMAPCTR0(sub->swm->och.hw), in aio_init()
[all …]
/linux/drivers/phy/lantiq/
H A Dphy-lantiq-vrx200-pcie.c103 regmap_write(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL1, 0x120e); in ltq_vrx200_pcie_phy_common_setup()
106 regmap_write(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL2, 0x39d7); in ltq_vrx200_pcie_phy_common_setup()
107 regmap_write(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL3, 0x0900); in ltq_vrx200_pcie_phy_common_setup()
110 regmap_write(priv->phy_regmap, PCIE_PHY_RX1_EI, 0x0004); in ltq_vrx200_pcie_phy_common_setup()
111 regmap_write(priv->phy_regmap, PCIE_PHY_RX1_A_CTRL, 0x6803); in ltq_vrx200_pcie_phy_common_setup()
118 regmap_write(priv->phy_regmap, PCIE_PHY_TX1_A_CTRL2, 0x0706); in ltq_vrx200_pcie_phy_common_setup()
121 regmap_write(priv->phy_regmap, PCIE_PHY_TX1_CTRL3, 0x1fff); in ltq_vrx200_pcie_phy_common_setup()
124 regmap_write(priv->phy_regmap, PCIE_PHY_TX1_A_CTRL1, 0x0810); in ltq_vrx200_pcie_phy_common_setup()
131 regmap_write(priv->phy_regmap, PCIE_PHY_TX1_CTRL2, 0x2e00); in ltq_vrx200_pcie_phy_common_setup()
134 regmap_write(priv->phy_regmap, PCIE_PHY_TX2_CTRL2, 0x3096); in ltq_vrx200_pcie_phy_common_setup()
[all …]
/linux/drivers/phy/amlogic/
H A Dphy-meson-axg-mipi-dphy.c229 regmap_write(priv->regmap, MIPI_DSI_PHY_CTRL, 0x1); in phy_meson_axg_mipi_dphy_power_on()
230 regmap_write(priv->regmap, MIPI_DSI_PHY_CTRL, in phy_meson_axg_mipi_dphy_power_on()
247 regmap_write(priv->regmap, MIPI_DSI_CLK_TIM, in phy_meson_axg_mipi_dphy_power_on()
253 regmap_write(priv->regmap, MIPI_DSI_CLK_TIM1, in phy_meson_axg_mipi_dphy_power_on()
256 regmap_write(priv->regmap, MIPI_DSI_HS_TIM, in phy_meson_axg_mipi_dphy_power_on()
262 regmap_write(priv->regmap, MIPI_DSI_LP_TIM, in phy_meson_axg_mipi_dphy_power_on()
268 regmap_write(priv->regmap, MIPI_DSI_ANA_UP_TIM, 0x0100); in phy_meson_axg_mipi_dphy_power_on()
269 regmap_write(priv->regmap, MIPI_DSI_INIT_TIM, in phy_meson_axg_mipi_dphy_power_on()
271 regmap_write(priv->regmap, MIPI_DSI_WAKEUP_TIM, in phy_meson_axg_mipi_dphy_power_on()
273 regmap_write(priv->regmap, MIPI_DSI_LPOK_TIM, 0x7C); in phy_meson_axg_mipi_dphy_power_on()
[all …]

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