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Searched refs:regUVD_MPC_CHROMA_SRCH_BASE_IDX (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_6_0_offset.h1033 #define regUVD_MPC_CHROMA_SRCH_BASE_IDX 1 macro
H A Dvcn_4_0_5_offset.h432 #define regUVD_MPC_CHROMA_SRCH_BASE_IDX 1 macro
H A Dvcn_4_0_0_offset.h449 #define regUVD_MPC_CHROMA_SRCH_BASE_IDX 1 macro
H A Dvcn_4_0_3_offset.h451 #define regUVD_MPC_CHROMA_SRCH_BASE_IDX 1 macro