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Searched refs:regSPI_GDBG_WAVE_CNTL3_BASE_IDX (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gc/ !
H A Dgc_9_4_2_offset.h6013 #define regSPI_GDBG_WAVE_CNTL3_BASE_IDX 0 macro
H A Dgc_9_4_3_offset.h3187 #define regSPI_GDBG_WAVE_CNTL3_BASE_IDX 0 macro
H A Dgc_12_0_0_offset.h9288 #define regSPI_GDBG_WAVE_CNTL3_BASE_IDX 1 macro
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H A Dgc_11_0_3_offset.h6683 #define regSPI_GDBG_WAVE_CNTL3_BASE_IDX 1 macro
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H A Dgc_11_0_0_offset.h6355 #define regSPI_GDBG_WAVE_CNTL3_BASE_IDX 1 macro
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