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Searched refs:regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_5_0_offset.h14185 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G … macro
H A Ddcn_3_6_0_offset.h6372 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G … macro
H A Ddcn_3_2_1_offset.h5920 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G … macro
H A Ddcn_3_5_1_offset.h14164 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G … macro
H A Ddcn_4_1_0_offset.h6460 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G … macro