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Searched refs:regMC_VM_CACHEABLE_DRAM_CNTL_BASE_IDX (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_1_8_0_offset.h3115 #define regMC_VM_CACHEABLE_DRAM_CNTL_BASE_IDX 0 macro
H A Dmmhub_1_7_offset.h5101 #define regMC_VM_CACHEABLE_DRAM_CNTL_BASE_IDX 0 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_2_offset.h7367 #define regMC_VM_CACHEABLE_DRAM_CNTL_BASE_IDX 0 macro
H A Dgc_9_4_3_offset.h2049 #define regMC_VM_CACHEABLE_DRAM_CNTL_BASE_IDX 0 macro