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Searched refs:regCP_HQD_CNTL_STACK_SIZE_BASE_IDX (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_2_offset.h792 #define regCP_HQD_CNTL_STACK_SIZE_BASE_IDX … macro
H A Dgc_9_4_3_offset.h3381 #define regCP_HQD_CNTL_STACK_SIZE_BASE_IDX … macro
H A Dgc_11_5_0_offset.h3672 #define regCP_HQD_CNTL_STACK_SIZE_BASE_IDX … macro
H A Dgc_12_0_0_offset.h3939 #define regCP_HQD_CNTL_STACK_SIZE_BASE_IDX … macro
H A Dgc_11_0_3_offset.h4923 #define regCP_HQD_CNTL_STACK_SIZE_BASE_IDX … macro
H A Dgc_11_0_0_offset.h4699 #define regCP_HQD_CNTL_STACK_SIZE_BASE_IDX … macro