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Searched refs:refcyc_h_blank_end (Results 1 – 20 of 20) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml2/
H A Ddml_display_rq_dlg_calc.c290 disp_dlg_regs->refcyc_h_blank_end = (dml_uint_t)((dml_float_t) hblank_end * ref_freq_to_pix_freq); in dml_rq_dlg_get_dlg_reg()
307 disp_dlg_regs->refcyc_h_blank_end = (dml_uint_t)(((dml_float_t) hblank_end + (dml_float_t) pipe_idx_in_combine * (dml_float_t) hactive / (dml_float_t) odm_combine_factor) * ref_freq_to_pix_freq); in dml_rq_dlg_get_dlg_reg()
313 dml_print("DML_DLG: %s: refcyc_h_blank_end = %d\n", __func__, disp_dlg_regs->refcyc_h_blank_end); in dml_rq_dlg_get_dlg_reg()
315 ASSERT(disp_dlg_regs->refcyc_h_blank_end < (dml_uint_t)dml_pow(2, 13)); in dml_rq_dlg_get_dlg_reg()
H A Ddisplay_mode_util.c253 dml_print("DML: refcyc_h_blank_end = 0x%x\n", dlg_regs->refcyc_h_blank_end); in dml_print_dlg_regs_st()
H A Ddml2_translation_helper.c1457 out->dlg_regs.refcyc_h_blank_end = disp_dlg_regs->refcyc_h_blank_end; in dml2_update_pipe_ctx_dchub_regs()
H A Ddisplay_mode_core_structs.h1932 dml_uint_t refcyc_h_blank_end; member
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn21/
H A Ddcn21_hubp.c358 REFCYC_H_BLANK_END, &dlg_attr.refcyc_h_blank_end, in hubp21_validate_dml_output()
370 if (dlg_attr.refcyc_h_blank_end != dml_dlg_attr->refcyc_h_blank_end) in hubp21_validate_dml_output()
372 dml_dlg_attr->refcyc_h_blank_end, dlg_attr.refcyc_h_blank_end); in hubp21_validate_dml_output()
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn20/
H A Ddcn20_hubp.c90 REFCYC_H_BLANK_END, dlg_attr->refcyc_h_blank_end, in hubp2_program_deadline()
1156 REFCYC_H_BLANK_END, &dlg_attr->refcyc_h_blank_end, in hubp2_read_state_common()
1467 REFCYC_H_BLANK_END, &dlg_attr.refcyc_h_blank_end, in hubp2_validate_dml_output()
1479 if (dlg_attr.refcyc_h_blank_end != dml_dlg_attr->refcyc_h_blank_end) in hubp2_validate_dml_output()
1481 dml_dlg_attr->refcyc_h_blank_end, dlg_attr.refcyc_h_blank_end); in hubp2_validate_dml_output()
/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/
H A Ddml_top_dchub_registers.h12 uint32_t refcyc_h_blank_end; member
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddisplay_rq_dlg_calc_32.c334 dlg_regs->refcyc_h_blank_end = (unsigned int) ((double) hblank_end * ref_freq_to_pix_freq); in dml32_rq_dlg_get_dlg_reg()
341 dlg_regs->refcyc_h_blank_end = (unsigned int) (((double) hblank_end in dml32_rq_dlg_get_dlg_reg()
345 ASSERT(dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13)); in dml32_rq_dlg_get_dlg_reg()
/linux/drivers/gpu/drm/amd/display/dc/dml/
H A Ddisplay_rq_dlg_helpers.c185 "DML_RQ_DLG_CALC: refcyc_h_blank_end = 0x%0x\n", in print__dlg_regs_st()
186 dlg_regs->refcyc_h_blank_end); in print__dlg_regs_st()
H A Ddisplay_mode_structs.h621 unsigned int refcyc_h_blank_end; member
H A Ddml1_display_rq_dlg_calc.c1156 disp_dlg_regs->refcyc_h_blank_end = (unsigned int) ((double) hblank_end in dml1_rq_dlg_get_dlg_params()
1158 ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int) dml_pow(2, 13)); in dml1_rq_dlg_get_dlg_params()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddisplay_rq_dlg_calc_30.c1210 disp_dlg_regs->refcyc_h_blank_end = (unsigned int)((double) hblank_end * ref_freq_to_pix_freq); in dml_rq_dlg_get_dlg_params()
1214 disp_dlg_regs->refcyc_h_blank_end = (unsigned int)(((double) hblank_end + odm_pipe_index * (double) dst->hactive / odm_combine_factor) * ref_freq_to_pix_freq); in dml_rq_dlg_get_dlg_params()
1216 ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13)); in dml_rq_dlg_get_dlg_params()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddisplay_rq_dlg_calc_31.c1084 disp_dlg_regs->refcyc_h_blank_end = (unsigned int) ((double) hblank_end * ref_freq_to_pix_freq); in dml_rq_dlg_get_dlg_params()
1088 disp_dlg_regs->refcyc_h_blank_end = (unsigned int) (((double) hblank_end + odm_pipe_index * (double) dst->hactive / odm_combine_factor) * ref_freq_to_pix_freq); in dml_rq_dlg_get_dlg_params()
1089 } ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13)); in dml_rq_dlg_get_dlg_params()
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn401/
H A Ddcn401_hubp.c223 REFCYC_H_BLANK_END, dlg_attr->refcyc_h_blank_end, in hubp401_program_deadline()
824 REFCYC_H_BLANK_END, &dlg_attr->refcyc_h_blank_end, in hubp401_read_state()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/
H A Ddisplay_rq_dlg_calc_314.c1171 disp_dlg_regs->refcyc_h_blank_end = (unsigned int) ((double) hblank_end * ref_freq_to_pix_freq); in dml_rq_dlg_get_dlg_params()
1176 disp_dlg_regs->refcyc_h_blank_end = (unsigned int) (((double) hblank_end + odm_pipe_index * (double) dst->hactive / odm_combine_factor) * ref_freq_to_pix_freq); in dml_rq_dlg_get_dlg_params()
1177 } ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13)); in dml_rq_dlg_get_dlg_params()
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn10/
H A Ddcn10_hubp.c615 REFCYC_H_BLANK_END, dlg_attr->refcyc_h_blank_end, in hubp1_program_deadline()
925 REFCYC_H_BLANK_END, &dlg_attr->refcyc_h_blank_end, in hubp1_read_state_common()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddisplay_rq_dlg_calc_20.c925 disp_dlg_regs->refcyc_h_blank_end = (unsigned int) ((double) hblank_end in dml20_rq_dlg_get_dlg_params()
927 ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int) dml_pow(2, 13)); in dml20_rq_dlg_get_dlg_params()
/linux/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_hw_sequencer_debug.c261 pool->hubps[i]->inst, dlg_regs->refcyc_h_blank_end, dlg_regs->dlg_vblank_end, dlg_regs->min_dst_y_next_start, in dcn10_get_dlg_states()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
H A Ddcn10_hwseq.c397 pool->hubps[i]->inst, dlg_regs->refcyc_h_blank_end, dlg_regs->dlg_vblank_end, dlg_regs->min_dst_y_next_start, in dcn10_log_hubp_states()
/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/
H A Ddml2_core_dcn4_calcs.c12404 disp_dlg_regs->refcyc_h_blank_end = (unsigned int)((double)l->hblank_end * l->ref_freq_to_pix_freq); in rq_dlg_get_dlg_reg()
12426 disp_dlg_regs->refcyc_h_blank_end = (unsigned int)(((double)l->hblank_end + (double)l->pipe_idx_in_combine * (double)l->hactive / (double)l->odm_combine_factor) * l->ref_freq_to_pix_freq); in rq_dlg_get_dlg_reg()
12432 DML_LOG_VERBOSE("DML_DLG: %s: refcyc_h_blank_end = %d\n", __func__, disp_dlg_regs->refcyc_h_blank_end); in rq_dlg_get_dlg_reg()
12434 DML_ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int)math_pow(2, 13)); in rq_dlg_get_dlg_reg()