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/linux/arch/arm/boot/dts/st/
H A Dstm32h743.dtsi45 #include <dt-bindings/mfd/stm32h7-rcc.h>
77 clocks = <&rcc TIM5_CK>;
85 clocks = <&rcc LPTIM1_CK>;
113 resets = <&rcc STM32H7_APB1L_RESET(SPI2)>;
114 clocks = <&rcc SPI2_CK>;
125 resets = <&rcc STM32H7_APB1L_RESET(SPI3)>;
126 clocks = <&rcc SPI3_CK>;
135 clocks = <&rcc USART2_CK>;
143 clocks = <&rcc USART3_CK>;
151 clocks = <&rcc UART4_CK>;
[all …]
H A Dstm32f746.dtsi45 #include <dt-bindings/mfd/stm32f7-rcc.h>
84 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
106 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
128 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
150 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
172 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
188 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
204 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
224 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
238 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
[all …]
H A Dstm32f429.dtsi50 #include <dt-bindings/mfd/stm32f4-rcc.h>
101 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
123 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
145 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
167 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
189 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
205 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
221 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
241 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
255 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
[all …]
H A Dstm32mp131.dtsi148 clocks = <&rcc TIM2_K>;
183 clocks = <&rcc TIM3_K>;
219 clocks = <&rcc TIM4_K>;
253 clocks = <&rcc TIM5_K>;
289 clocks = <&rcc TIM6_K>;
314 clocks = <&rcc TIM7_K>;
338 clocks = <&rcc LPTIM1_K>;
381 clocks = <&rcc SPI2_K>;
382 resets = <&rcc SPI2_R>;
406 clocks = <&rcc SPI3_K>;
[all …]
H A Dstm32mp151.dtsi135 clocks = <&rcc IPCC>;
140 rcc: rcc@50000000 { label
141 compatible = "st,stm32mp1-rcc", "syscon";
260 clocks = <&rcc SYSCFG>;
267 clocks = <&rcc TMPSENS>;
276 clocks = <&rcc HDP>;
284 clocks = <&rcc MDMA>;
285 resets = <&rcc MDMA_R>;
296 clocks = <&rcc SDMMC1_K>;
298 resets = <&rcc SDMMC1_R>;
[all …]
H A Dstm32mp133.dtsi18 clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
31 clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
44 clocks = <&rcc ADC1>, <&rcc ADC1_K>;
86 clocks = <&rcc ETH2MAC>,
87 <&rcc ETH2TX>,
88 <&rcc ETH2RX>,
89 <&rcc ETH2STP>,
90 <&rcc ETH2PTP_K>,
91 <&rcc ETH2CK_K>;
H A Dstm32mp157.dtsi15 clocks = <&rcc GPU>, <&rcc GPU_K>;
17 resets = <&rcc GPU_R>;
23 clocks = <&rcc DSI>, <&clk_hse>, <&rcc DSI_PX>;
26 resets = <&rcc DSI_R>;
H A Dstm32mp153.dtsi41 clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
43 resets = <&rcc FDCAN_R>;
56 clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
58 resets = <&rcc FDCAN_R>;
H A Dstm32f769.dtsi15 resets = <&rcc STM32F7_APB1_RESET(CAN3)>;
16 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
24 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
30 clocks = <&rcc 1 CLK_F769_DSI>, <&clk_hse>;
32 resets = <&rcc STM32F7_APB2_RESET(DSI)>;
H A Dstm32mp157c-ev1-scmi.dts39 clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
57 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
61 clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
80 &rcc {
81 compatible = "st,stm32mp1-rcc-secure", "syscon";
H A Dstm32mp157a-dk1-scmi.dts33 clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
51 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
70 &rcc {
71 compatible = "st,stm32mp1-rcc-secure", "syscon";
H A Dstm32mp157c-ed1-scmi.dts38 clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
56 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
75 &rcc {
76 compatible = "st,stm32mp1-rcc-secure", "syscon";
H A Dstm32mp157c-dk2-scmi.dts39 clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
57 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
76 &rcc {
77 compatible = "st,stm32mp1-rcc-secure", "syscon";
H A Dstm32f7-pinctrl.dtsi8 #include <dt-bindings/mfd/stm32f7-rcc.h>
25 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
35 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
45 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
55 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
65 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
75 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
85 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
95 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
105 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
[all …]
H A Dstm32mp157f-dk2-scmi.dtsi52 clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
72 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
98 &rcc {
99 compatible = "st,stm32mp1-rcc-secure", "syscon";
H A Dstm32f4-pinctrl.dtsi44 #include <dt-bindings/mfd/stm32f4-rcc.h>
61 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
71 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
81 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
91 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>;
101 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>;
111 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>;
121 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>;
131 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>;
141 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>;
[all …]
H A Dstm32mp135.dtsi15 resets = <&rcc DCMIPP_R>;
16 clocks = <&rcc DCMIPP_K>;
28 clocks = <&rcc LTDC_PX>;
H A Dstm32mp151c-mecio1r0.dts44 assigned-clocks = <&rcc ETHCK_K>, <&rcc PLL3_Q>;
45 assigned-clock-parents = <&rcc PLL3_Q>;
H A Dstm32mp151c-plyaqm.dts235 clocks = <&rcc SPI1>, <&rcc SPI1_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
250 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
265 &rcc {
266 compatible = "st,stm32mp1-rcc-secure", "syscon";
/linux/arch/arm64/boot/dts/st/
H A Dstm32mp231.dtsi6 #include <dt-bindings/clock/st,stm32mp25-rcc.h>
9 #include <dt-bindings/reset/st,stm32mp25-rcc.h>
232 clocks = <&rcc CK_BUS_SPI2>, <&rcc CK_KER_SPI2>;
234 resets = <&rcc SPI2_R>;
248 clocks = <&rcc CK_KER_SPI2>;
249 resets = <&rcc SPI2_R>;
263 clocks = <&rcc CK_BUS_SPI3>, <&rcc CK_KER_SPI3>;
265 resets = <&rcc SPI3_R>;
279 clocks = <&rcc CK_KER_SPI3>;
280 resets = <&rcc SPI3_R>;
[all …]
H A Dstm32mp251.dtsi6 #include <dt-bindings/clock/st,stm32mp25-rcc.h>
8 #include <dt-bindings/reset/st,stm32mp25-rcc.h>
253 clocks = <&rcc CK_BUS_OSPIIOM>,
257 resets = <&rcc OSPIIOM_R>,
314 clocks = <&rcc CK_KER_TIM2>;
345 clocks = <&rcc CK_KER_TIM3>;
376 clocks = <&rcc CK_KER_TIM4>;
407 clocks = <&rcc CK_KER_TIM5>;
438 clocks = <&rcc CK_KER_TIM6>;
463 clocks = <&rcc CK_KER_TIM7>;
[all …]
H A Dstm32mp255.dtsi10 clocks = <&clk_flexgen_27_fixed>, <&rcc CK_BUS_LTDC>, <&syscfg>, <&lvds>;
19 clocks = <&rcc CK_BUS_LVDS>, <&rcc CK_KER_LVDSPHY>;
21 resets = <&rcc LVDS_R>;
31 clocks = <&rcc CK_BUS_VDEC>;
40 clocks = <&rcc CK_BUS_VENC>;
H A Dstm32mp233.dtsi58 clocks = <&rcc CK_ETH2_MAC>,
59 <&rcc CK_ETH2_TX>,
60 <&rcc CK_ETH2_RX>,
61 <&rcc CK_KER_ETH2PTP>,
62 <&rcc CK_ETH2_STP>,
63 <&rcc CK_KER_ETH2>;
H A Dstm32mp253.dtsi58 clocks = <&rcc CK_ETH2_MAC>,
59 <&rcc CK_ETH2_TX>,
60 <&rcc CK_ETH2_RX>,
61 <&rcc CK_KER_ETH2PTP>,
62 <&rcc CK_ETH2_STP>,
63 <&rcc CK_KER_ETH2>;
/linux/drivers/clk/qcom/
H A Dclk-rpm.c254 struct rpm_cc *rcc = r->rpm_cc; in clk_rpm_xo_prepare() local
258 mutex_lock(&rcc->xo_lock); in clk_rpm_xo_prepare()
260 value = rcc->xo_buffer_value | (QCOM_RPM_XO_MODE_ON << r->xo_offset); in clk_rpm_xo_prepare()
264 rcc->xo_buffer_value = value; in clk_rpm_xo_prepare()
267 mutex_unlock(&rcc->xo_lock); in clk_rpm_xo_prepare()
275 struct rpm_cc *rcc = r->rpm_cc; in clk_rpm_xo_unprepare() local
279 mutex_lock(&rcc->xo_lock); in clk_rpm_xo_unprepare()
281 value = rcc->xo_buffer_value & ~(QCOM_RPM_XO_MODE_ON << r->xo_offset); in clk_rpm_xo_unprepare()
285 rcc->xo_buffer_value = value; in clk_rpm_xo_unprepare()
288 mutex_unlock(&rcc->xo_lock); in clk_rpm_xo_unprepare()
[all …]

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