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Searched refs:pwr_reg (Results 1 – 14 of 14) sorted by relevance

/linux/sound/soc/codecs/
H A Dwm8961.c197 u16 pwr_reg = snd_soc_component_read(component, WM8961_PWR_MGMT_2); in wm8961_hp_event() local
212 pwr_reg |= WM8961_LOUT1_PGA | WM8961_ROUT1_PGA; in wm8961_hp_event()
213 snd_soc_component_write(component, WM8961_PWR_MGMT_2, pwr_reg); in wm8961_hp_event()
271 pwr_reg &= ~(WM8961_LOUT1_PGA | WM8961_ROUT1_PGA); in wm8961_hp_event()
272 snd_soc_component_write(component, WM8961_PWR_MGMT_2, pwr_reg); in wm8961_hp_event()
287 u16 pwr_reg = snd_soc_component_read(component, WM8961_PWR_MGMT_2); in wm8961_spk_event() local
292 pwr_reg |= WM8961_SPKL_PGA | WM8961_SPKR_PGA; in wm8961_spk_event()
293 snd_soc_component_write(component, WM8961_PWR_MGMT_2, pwr_reg); in wm8961_spk_event()
306 pwr_reg &= ~(WM8961_SPKL_PGA | WM8961_SPKR_PGA); in wm8961_spk_event()
307 snd_soc_component_write(component, WM8961_PWR_MGMT_2, pwr_reg); in wm8961_spk_event()
H A Dwm8940.c481 u16 pwr_reg = snd_soc_component_read(component, WM8940_POWER1) & 0x1F0; in wm8940_set_bias_level() local
487 pwr_reg |= (1 << 2) | (1 << 3); in wm8940_set_bias_level()
494 ret = snd_soc_component_write(component, WM8940_POWER1, pwr_reg | 0x1); in wm8940_set_bias_level()
498 pwr_reg |= (1 << 2) | (1 << 3); in wm8940_set_bias_level()
499 ret = snd_soc_component_write(component, WM8940_POWER1, pwr_reg | 0x1); in wm8940_set_bias_level()
511 pwr_reg |= (1 << 2) | (1 << 3); in wm8940_set_bias_level()
513 ret = snd_soc_component_write(component, WM8940_POWER1, pwr_reg | 0x2); in wm8940_set_bias_level()
516 ret = snd_soc_component_write(component, WM8940_POWER1, pwr_reg); in wm8940_set_bias_level()
H A Dwm8971.c565 u16 pwr_reg = snd_soc_component_read(component, WM8971_PWR1) & 0xfe3e; in wm8971_set_bias_level() local
570 snd_soc_component_write(component, WM8971_PWR1, pwr_reg | 0x00c1); in wm8971_set_bias_level()
580 snd_soc_component_write(component, WM8971_PWR1, pwr_reg | 0x01c0); in wm8971_set_bias_level()
585 snd_soc_component_write(component, WM8971_PWR1, pwr_reg | 0x0140); in wm8971_set_bias_level()
H A Dwm8750.c625 u16 pwr_reg = snd_soc_component_read(component, WM8750_PWR1) & 0xfe3e; in wm8750_set_bias_level() local
630 snd_soc_component_write(component, WM8750_PWR1, pwr_reg | 0x00c0); in wm8750_set_bias_level()
639 snd_soc_component_write(component, WM8750_PWR1, pwr_reg | 0x01c1); in wm8750_set_bias_level()
646 snd_soc_component_write(component, WM8750_PWR1, pwr_reg | 0x0141); in wm8750_set_bias_level()
H A Dwm8988.c727 u16 pwr_reg = snd_soc_component_read(component, WM8988_PWR1) & ~0x1c1; in wm8988_set_bias_level() local
735 snd_soc_component_write(component, WM8988_PWR1, pwr_reg | 0x00c0); in wm8988_set_bias_level()
743 snd_soc_component_write(component, WM8988_PWR1, pwr_reg | 0x1c1); in wm8988_set_bias_level()
750 snd_soc_component_write(component, WM8988_PWR1, pwr_reg | 0x0141); in wm8988_set_bias_level()
H A Dwm8958-dsp2.c327 int pwr_reg = snd_soc_component_read(component, WM8994_POWER_MANAGEMENT_5); in wm8958_dsp_apply() local
332 pwr_reg &= (WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA); in wm8958_dsp_apply()
336 pwr_reg &= (WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA); in wm8958_dsp_apply()
340 pwr_reg &= (WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA); in wm8958_dsp_apply()
352 if (!pwr_reg) in wm8958_dsp_apply()
358 path, wm8994->dsp_active, start, pwr_reg, reg); in wm8958_dsp_apply()
H A Dwm8753.c1335 u16 pwr_reg = snd_soc_component_read(component, WM8753_PWR1) & 0xfe3e; in wm8753_set_bias_level() local
1340 snd_soc_component_write(component, WM8753_PWR1, pwr_reg | 0x00c0); in wm8753_set_bias_level()
1349 snd_soc_component_write(component, WM8753_PWR1, pwr_reg | 0x01c1); in wm8753_set_bias_level()
1354 snd_soc_component_write(component, WM8753_PWR1, pwr_reg | 0x0141); in wm8753_set_bias_level()
H A Dwm8904.c702 int pwr_reg; in out_pga_event() local
712 pwr_reg = WM8904_POWER_MANAGEMENT_2; in out_pga_event()
721 pwr_reg = WM8904_POWER_MANAGEMENT_3; in out_pga_event()
737 snd_soc_component_update_bits(component, pwr_reg, in out_pga_event()
838 snd_soc_component_update_bits(component, pwr_reg, in out_pga_event()
/linux/drivers/mmc/host/
H A Dmmci_stm32_sdmmc.c394 pwr |= host->pwr_reg & (MCI_STM32_VSWITCHEN | in mmci_sdmmc_set_pwrreg()
662 mmci_write_pwrreg(host, host->pwr_reg | MCI_STM32_VSWITCHEN); in sdmmc_pre_sig_volt_vswitch()
674 host->pwr_reg & MCI_STM32_VSWITCHEN) { in sdmmc_post_sig_volt_switch()
675 mmci_write_pwrreg(host, host->pwr_reg | MCI_STM32_VSWITCH); in sdmmc_post_sig_volt_switch()
687 mmci_write_pwrreg(host, host->pwr_reg & in sdmmc_post_sig_volt_switch()
731 host->pwr_reg = readl_relaxed(host->base + MMCIPOWER); in sdmmc_variant_init()
H A Dmmci.h428 u32 pwr_reg; member
H A Dmmci.c416 if (host->pwr_reg != pwr) { in mmci_write_pwrreg()
417 host->pwr_reg = pwr; in mmci_write_pwrreg()
1868 writel(host->pwr_reg, host->base + MMCIPOWER); in mmci_irq_thread()
2545 writel(host->pwr_reg, host->base + MMCIPOWER); in mmci_restore()
/linux/drivers/clk/
H A Dclk-rp1.c324 u32 pwr_reg; member
396 u32 pwr = clockman_read(clockman, data->pwr_reg); in rp1_pll_core_is_on()
413 clockman_write(clockman, data->pwr_reg, PLL_PWR_MASK); in rp1_pll_core_on()
421 clockman_write(clockman, data->pwr_reg, fbdiv_frac ? 0 : PLL_PWR_DSMPD); in rp1_pll_core_on()
442 clockman_write(clockman, data->pwr_reg, 0); in rp1_pll_core_off()
495 clockman_write(clockman, data->pwr_reg, fbdiv_frac ? 0 : PLL_PWR_DSMPD); in rp1_pll_core_set_rate()
1317 .pwr_reg = PLL_SYS_PWR,
1332 .pwr_reg = PLL_AUDIO_PWR,
1347 .pwr_reg = PLL_VIDEO_PWR,
/linux/drivers/pinctrl/renesas/
H A Dpinctrl-rzg2l.c917 int pwr_reg; in rzg2l_get_power_source() local
923 pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps); in rzg2l_get_power_source()
924 if (pwr_reg < 0) in rzg2l_get_power_source()
925 return pwr_reg; in rzg2l_get_power_source()
927 val = readb(pctrl->base + pwr_reg); in rzg2l_get_power_source()
945 int pwr_reg; in rzg2l_set_power_source() local
969 pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps); in rzg2l_set_power_source()
970 if (pwr_reg < 0) in rzg2l_set_power_source()
971 return pwr_reg; in rzg2l_set_power_source()
973 writeb(val, pctrl->base + pwr_reg); in rzg2l_set_power_source()
/linux/drivers/clk/mediatek/
H A Dclk-pll.c336 pll->pwr_addr = base + data->pwr_reg; in mtk_clk_register_pll_ops()