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Searched refs:pll_28nm (Results 1 – 2 of 2) sorted by relevance

/linux/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy_28nm.c80 static bool pll_28nm_poll_for_ready(struct dsi_pll_28nm *pll_28nm, in pll_28nm_poll_for_ready() argument
87 val = readl(pll_28nm->phy->pll_base + REG_DSI_28nm_PHY_PLL_STATUS); in pll_28nm_poll_for_ready()
100 static void pll_28nm_software_reset(struct dsi_pll_28nm *pll_28nm) in pll_28nm_software_reset() argument
102 void __iomem *base = pll_28nm->phy->pll_base; in pll_28nm_software_reset()
120 struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw); in dsi_pll_28nm_clk_set_rate() local
121 struct device *dev = &pll_28nm->phy->pdev->dev; in dsi_pll_28nm_clk_set_rate()
122 void __iomem *base = pll_28nm->phy->pll_base; in dsi_pll_28nm_clk_set_rate()
213 if (pll_28nm->phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP) in dsi_pll_28nm_clk_set_rate()
236 struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw); in dsi_pll_28nm_clk_is_enabled() local
238 return pll_28nm_poll_for_ready(pll_28nm, POLL_MAX_READS, in dsi_pll_28nm_clk_is_enabled()
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H A Ddsi_phy_28nm_8960.c71 static bool pll_28nm_poll_for_ready(struct dsi_pll_28nm *pll_28nm, in pll_28nm_poll_for_ready() argument
78 val = readl(pll_28nm->phy->pll_base + REG_DSI_28nm_8960_PHY_PLL_RDY); in pll_28nm_poll_for_ready()
97 struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw); in dsi_pll_28nm_clk_set_rate() local
98 void __iomem *base = pll_28nm->phy->pll_base; in dsi_pll_28nm_clk_set_rate()
132 struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw); in dsi_pll_28nm_clk_is_enabled() local
134 return pll_28nm_poll_for_ready(pll_28nm, POLL_MAX_READS, in dsi_pll_28nm_clk_is_enabled()
141 struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw); in dsi_pll_28nm_clk_recalc_rate() local
142 void __iomem *base = pll_28nm->phy->pll_base; in dsi_pll_28nm_clk_recalc_rate()
174 struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw); in dsi_pll_28nm_vco_prepare() local
175 struct device *dev = &pll_28nm->phy->pdev->dev; in dsi_pll_28nm_vco_prepare()
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