1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
4 */
5
6 #ifndef _SUN8I_MIXER_H_
7 #define _SUN8I_MIXER_H_
8
9 #include <linux/clk.h>
10 #include <linux/regmap.h>
11 #include <linux/reset.h>
12 #include <drm/drm_plane.h>
13
14 #include "sunxi_engine.h"
15
16 #define SUN8I_MIXER_SIZE(w, h) (((h) - 1) << 16 | ((w) - 1))
17 #define SUN8I_MIXER_COORD(x, y) ((y) << 16 | (x))
18
19 #define SUN8I_MIXER_GLOBAL_CTL 0x0
20 #define SUN8I_MIXER_GLOBAL_STATUS 0x4
21 #define SUN8I_MIXER_GLOBAL_DBUFF 0x8
22 #define SUN8I_MIXER_GLOBAL_SIZE 0xc
23
24 #define SUN50I_MIXER_GLOBAL_SIZE 0x8
25 #define SUN50I_MIXER_GLOBAL_CLK 0xc
26
27 #define SUN8I_MIXER_GLOBAL_CTL_RT_EN BIT(0)
28
29 #define SUN8I_MIXER_GLOBAL_DBUFF_ENABLE BIT(0)
30
31 #define DE2_MIXER_UNIT_SIZE 0x6000
32 #define DE3_MIXER_UNIT_SIZE 0x3000
33
34 #define DE2_BLD_BASE 0x1000
35 #define DE2_CH_BASE 0x2000
36 #define DE2_CH_SIZE 0x1000
37
38 #define DE3_BLD_BASE 0x0800
39 #define DE3_CH_BASE 0x1000
40 #define DE3_CH_SIZE 0x0800
41
42 #define DE33_CH_BASE 0x1000
43 #define DE33_CH_SIZE 0x20000
44
45 #define SUN8I_MIXER_BLEND_PIPE_CTL(base) ((base) + 0)
46 #define SUN8I_MIXER_BLEND_ATTR_FCOLOR(base, x) ((base) + 0x4 + 0x10 * (x))
47 #define SUN8I_MIXER_BLEND_ATTR_INSIZE(base, x) ((base) + 0x8 + 0x10 * (x))
48 #define SUN8I_MIXER_BLEND_ATTR_COORD(base, x) ((base) + 0xc + 0x10 * (x))
49 #define SUN8I_MIXER_BLEND_ROUTE(base) ((base) + 0x80)
50 #define SUN8I_MIXER_BLEND_PREMULTIPLY(base) ((base) + 0x84)
51 #define SUN8I_MIXER_BLEND_BKCOLOR(base) ((base) + 0x88)
52 #define SUN8I_MIXER_BLEND_OUTSIZE(base) ((base) + 0x8c)
53 #define SUN8I_MIXER_BLEND_MODE(base, x) ((base) + 0x90 + 0x04 * (x))
54 #define SUN8I_MIXER_BLEND_CK_CTL(base) ((base) + 0xb0)
55 #define SUN8I_MIXER_BLEND_CK_CFG(base) ((base) + 0xb4)
56 #define SUN8I_MIXER_BLEND_CK_MAX(base, x) ((base) + 0xc0 + 0x04 * (x))
57 #define SUN8I_MIXER_BLEND_CK_MIN(base, x) ((base) + 0xe0 + 0x04 * (x))
58 #define SUN8I_MIXER_BLEND_OUTCTL(base) ((base) + 0xfc)
59 #define SUN50I_MIXER_BLEND_CSC_CTL(base) ((base) + 0x100)
60 #define SUN50I_MIXER_BLEND_CSC_COEFF(base, layer, x) \
61 ((base) + 0x110 + (layer) * 0x30 + (x) * 4)
62
63 #define SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK GENMASK(12, 8)
64 #define SUN8I_MIXER_BLEND_PIPE_CTL_EN(pipe) BIT(8 + pipe)
65 #define SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(pipe) BIT(pipe)
66
67 /* colors are always in AARRGGBB format */
68 #define SUN8I_MIXER_BLEND_COLOR_BLACK 0xff000000
69 /* The following numbers are some still unknown magic numbers */
70 #define SUN8I_MIXER_BLEND_MODE_DEF 0x03010301
71
72 #define SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(n) (0xf << ((n) << 2))
73 #define SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(n) ((n) << 2)
74
75 #define SUN8I_MIXER_BLEND_OUTCTL_INTERLACED BIT(1)
76
77 #define SUN50I_MIXER_BLEND_CSC_CTL_EN(ch) BIT(ch)
78 #define SUN50I_MIXER_BLEND_CSC_CONST_VAL(d, c) (((d) << 16) | ((c) & 0xffff))
79
80 #define SUN8I_MIXER_FBFMT_ARGB8888 0
81 #define SUN8I_MIXER_FBFMT_ABGR8888 1
82 #define SUN8I_MIXER_FBFMT_RGBA8888 2
83 #define SUN8I_MIXER_FBFMT_BGRA8888 3
84 #define SUN8I_MIXER_FBFMT_XRGB8888 4
85 #define SUN8I_MIXER_FBFMT_XBGR8888 5
86 #define SUN8I_MIXER_FBFMT_RGBX8888 6
87 #define SUN8I_MIXER_FBFMT_BGRX8888 7
88 #define SUN8I_MIXER_FBFMT_RGB888 8
89 #define SUN8I_MIXER_FBFMT_BGR888 9
90 #define SUN8I_MIXER_FBFMT_RGB565 10
91 #define SUN8I_MIXER_FBFMT_BGR565 11
92 #define SUN8I_MIXER_FBFMT_ARGB4444 12
93 #define SUN8I_MIXER_FBFMT_ABGR4444 13
94 #define SUN8I_MIXER_FBFMT_RGBA4444 14
95 #define SUN8I_MIXER_FBFMT_BGRA4444 15
96 #define SUN8I_MIXER_FBFMT_ARGB1555 16
97 #define SUN8I_MIXER_FBFMT_ABGR1555 17
98 #define SUN8I_MIXER_FBFMT_RGBA5551 18
99 #define SUN8I_MIXER_FBFMT_BGRA5551 19
100 #define SUN8I_MIXER_FBFMT_ARGB2101010 20
101 #define SUN8I_MIXER_FBFMT_ABGR2101010 21
102 #define SUN8I_MIXER_FBFMT_RGBA1010102 22
103 #define SUN8I_MIXER_FBFMT_BGRA1010102 23
104
105 #define SUN8I_MIXER_FBFMT_YUYV 0
106 #define SUN8I_MIXER_FBFMT_UYVY 1
107 #define SUN8I_MIXER_FBFMT_YVYU 2
108 #define SUN8I_MIXER_FBFMT_VYUY 3
109 #define SUN8I_MIXER_FBFMT_NV16 4
110 #define SUN8I_MIXER_FBFMT_NV61 5
111 #define SUN8I_MIXER_FBFMT_YUV422 6
112 /* format 7 doesn't exist */
113 #define SUN8I_MIXER_FBFMT_NV12 8
114 #define SUN8I_MIXER_FBFMT_NV21 9
115 #define SUN8I_MIXER_FBFMT_YUV420 10
116 /* format 11 doesn't exist */
117 /* format 12 is semi-planar YUV411 UVUV */
118 /* format 13 is semi-planar YUV411 VUVU */
119 #define SUN8I_MIXER_FBFMT_YUV411 14
120 /* format 15 doesn't exist */
121 #define SUN8I_MIXER_FBFMT_P010_YUV 16
122 /* format 17 is P010 YVU */
123 #define SUN8I_MIXER_FBFMT_P210_YUV 18
124 /* format 19 is P210 YVU */
125 /* format 20 is packed YVU444 10-bit */
126 /* format 21 is packed YUV444 10-bit */
127
128 /*
129 * Sub-engines listed bellow are unused for now. The EN registers are here only
130 * to be used to disable these sub-engines.
131 */
132 #define SUN8I_MIXER_FCE_EN 0xa0000
133 #define SUN8I_MIXER_BWS_EN 0xa2000
134 #define SUN8I_MIXER_LTI_EN 0xa4000
135 #define SUN8I_MIXER_PEAK_EN 0xa6000
136 #define SUN8I_MIXER_ASE_EN 0xa8000
137 #define SUN8I_MIXER_FCC_EN 0xaa000
138 #define SUN8I_MIXER_DCSC_EN 0xb0000
139
140 #define SUN50I_MIXER_FCE_EN 0x70000
141 #define SUN50I_MIXER_PEAK_EN 0x70800
142 #define SUN50I_MIXER_LCTI_EN 0x71000
143 #define SUN50I_MIXER_BLS_EN 0x71800
144 #define SUN50I_MIXER_FCC_EN 0x72000
145 #define SUN50I_MIXER_DNS_EN 0x80000
146 #define SUN50I_MIXER_DRC_EN 0xa0000
147 #define SUN50I_MIXER_FMT_EN 0xa8000
148 #define SUN50I_MIXER_CDC0_EN 0xd0000
149 #define SUN50I_MIXER_CDC1_EN 0xd8000
150
151 enum {
152 /* First mixer or second mixer with VEP support. */
153 CCSC_MIXER0_LAYOUT,
154 /* Second mixer without VEP support. */
155 CCSC_MIXER1_LAYOUT,
156 /* First mixer with the MMIO layout found in the D1 SoC. */
157 CCSC_D1_MIXER0_LAYOUT,
158 };
159
160 enum sun8i_mixer_type {
161 SUN8I_MIXER_DE2,
162 SUN8I_MIXER_DE3,
163 SUN8I_MIXER_DE33,
164 };
165
166 /**
167 * struct sun8i_layer_cfg - layer configuration
168 * @vi_scaler_num: Number of VI scalers. Used on DE2 and DE3.
169 * @scaler_mask: bitmask which tells which channel supports scaling
170 * First, scaler supports for VI channels is defined and after that, scaler
171 * support for UI channels. For example, if mixer has 2 VI channels without
172 * scaler and 2 UI channels with scaler, bitmask would be 0xC.
173 * @ccsc: select set of CCSC base addresses from the enumeration above.
174 * @de_type: sun8i_mixer_type enum representing the display engine generation.
175 * @scaline_yuv: size of a scanline for VI scaler for YUV formats.
176 * @de2_fcc_alpha: use FCC for missing DE2 VI alpha capability
177 * Most DE2 cores has FCC. If number of VI planes is one, enable this.
178 */
179 struct sun8i_layer_cfg {
180 unsigned int vi_scaler_num;
181 int scaler_mask;
182 int ccsc;
183 unsigned int de_type;
184 unsigned int scanline_yuv;
185 unsigned int de2_fcc_alpha : 1;
186 };
187
188 /**
189 * struct sun8i_mixer_cfg - mixer HW configuration
190 * @lay_cfg: layer configuration
191 * @vi_num: number of VI channels
192 * @ui_num: number of UI channels
193 * @de_type: sun8i_mixer_type enum representing the display engine generation.
194 * @mod_rate: module clock rate that needs to be set in order to have
195 * a functional block.
196 * @map: channel map for DE variants processing YUV separately (DE33)
197 */
198
199 struct sun8i_mixer_cfg {
200 struct sun8i_layer_cfg lay_cfg;
201 int vi_num;
202 int ui_num;
203 unsigned int de_type;
204 unsigned long mod_rate;
205 unsigned int map[6];
206 };
207
208 struct sun8i_mixer {
209 struct sunxi_engine engine;
210
211 const struct sun8i_mixer_cfg *cfg;
212
213 struct reset_control *reset;
214
215 struct clk *bus_clk;
216 struct clk *mod_clk;
217
218 struct regmap *top_regs;
219 struct regmap *disp_regs;
220 };
221
222 enum {
223 SUN8I_LAYER_TYPE_UI,
224 SUN8I_LAYER_TYPE_VI,
225 };
226
227 struct sun8i_layer {
228 struct drm_plane plane;
229 int type;
230 int index;
231 int channel;
232 int overlay;
233 struct regmap *regs;
234 const struct sun8i_layer_cfg *cfg;
235 };
236
237 static inline struct sun8i_layer *
plane_to_sun8i_layer(struct drm_plane * plane)238 plane_to_sun8i_layer(struct drm_plane *plane)
239 {
240 return container_of(plane, struct sun8i_layer, plane);
241 }
242
243 static inline struct sun8i_mixer *
engine_to_sun8i_mixer(struct sunxi_engine * engine)244 engine_to_sun8i_mixer(struct sunxi_engine *engine)
245 {
246 return container_of(engine, struct sun8i_mixer, engine);
247 }
248
249 static inline u32
sun8i_blender_base(struct sun8i_mixer * mixer)250 sun8i_blender_base(struct sun8i_mixer *mixer)
251 {
252 return mixer->cfg->de_type == SUN8I_MIXER_DE3 ? DE3_BLD_BASE : DE2_BLD_BASE;
253 }
254
255 static inline struct regmap *
sun8i_blender_regmap(struct sun8i_mixer * mixer)256 sun8i_blender_regmap(struct sun8i_mixer *mixer)
257 {
258 return mixer->cfg->de_type == SUN8I_MIXER_DE33 ?
259 mixer->disp_regs : mixer->engine.regs;
260 }
261
262 static inline u32
sun8i_channel_base(struct sun8i_layer * layer)263 sun8i_channel_base(struct sun8i_layer *layer)
264 {
265 if (layer->cfg->de_type == SUN8I_MIXER_DE33)
266 return DE33_CH_BASE + layer->channel * DE33_CH_SIZE;
267 else if (layer->cfg->de_type == SUN8I_MIXER_DE3)
268 return DE3_CH_BASE + layer->channel * DE3_CH_SIZE;
269 else
270 return DE2_CH_BASE + layer->channel * DE2_CH_SIZE;
271 }
272
273 int sun8i_mixer_drm_format_to_hw(u32 format, u32 *hw_format);
274 #endif /* _SUN8I_MIXER_H_ */
275