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Searched refs:pix_clk_div (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/media/i2c/
H A Dccs-pll.c113 br->bk->pix_clk_div); in print_pll()
263 * values of pix_clk_div. in ccs_pll_find_vt_sys_div()
378 pll_bk->pix_clk_div = best_pix_div; in __ccs_pll_calculate_vt_tree()
383 pll_bk->sys_clk_freq_hz / pll_bk->pix_clk_div; in __ccs_pll_calculate_vt_tree()
478 op_pll_bk->sys_clk_div * op_pll_bk->pix_clk_div in ccs_pll_calculate_vt()
583 pll->vt_bk.pix_clk_div = best_pix_div; in ccs_pll_calculate_vt()
588 pll->vt_bk.sys_clk_freq_hz / pll->vt_bk.pix_clk_div; in ccs_pll_calculate_vt()
705 op_pll_bk->pix_clk_div = in ccs_pll_calculate_op()
711 op_pll_bk->pix_clk_div = in ccs_pll_calculate_op()
718 / op_pll_bk->pix_clk_div; in ccs_pll_calculate_op()
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H A Dccs-pll.h80 * @pix_clk_div: Pixel clock divider
86 u16 pix_clk_div; member
/linux/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy_10nm.c65 u8 pix_clk_div; member
485 cached->pix_clk_div = (cmn_clk_cfg0 & 0xf0) >> 4; in dsi_10nm_pll_save_state()
490 DBG("DSI PLL%d outdiv %x bit_clk_div %x pix_clk_div %x pll_mux %x", in dsi_10nm_pll_save_state()
492 cached->pix_clk_div, cached->pll_mux); in dsi_10nm_pll_save_state()
508 writel(cached->bit_clk_div | (cached->pix_clk_div << 4), in dsi_10nm_pll_restore_state()
H A Ddsi_phy_7nm.c75 u8 pix_clk_div; member
602 cached->pix_clk_div = FIELD_GET(DSI_7nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK, cmn_clk_cfg0); in dsi_7nm_pll_save_state()
607 DBG("DSI PLL%d outdiv %x bit_clk_div %x pix_clk_div %x pll_mux %x", in dsi_7nm_pll_save_state()
609 cached->pix_clk_div, cached->pll_mux); in dsi_7nm_pll_save_state()
626 DSI_7nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4(cached->pix_clk_div)); in dsi_7nm_pll_restore_state()
/linux/drivers/media/i2c/ccs/
H A Dccs-core.c379 rval = ccs_write(sensor, VT_PIX_CLK_DIV, pll->vt_bk.pix_clk_div); in ccs_pll_configure()
412 rval = ccs_write(sensor, OP_PIX_CLK_DIV, pll->op_bk.pix_clk_div); in ccs_pll_configure()