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Searched refs:pipe_plane (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/
H A Ddml2_core_utils.h21 …ne_mapping(const struct core_display_cfg_support_info *cfg_support_info, unsigned int *pipe_plane);
H A Ddml2_core_utils.c401 …ane_mapping(const struct core_display_cfg_support_info *cfg_support_info, unsigned int *pipe_plane) in dml2_core_utils_pipe_plane_mapping() argument
406 pipe_plane[k] = __DML2_CALCS_PIPE_NO_PLANE__; in dml2_core_utils_pipe_plane_mapping()
411 pipe_plane[pipe_idx] = plane_idx; in dml2_core_utils_pipe_plane_mapping()
H A Ddml2_core_dcn4_calcs.c217 …ane_mapping(const struct core_display_cfg_support_info *cfg_support_info, unsigned int *pipe_plane) in dml_calc_pipe_plane_mapping() argument
222 pipe_plane[k] = __DML2_CALCS_PIPE_NO_PLANE__; in dml_calc_pipe_plane_mapping()
227 pipe_plane[pipe_idx] = plane_idx; in dml_calc_pipe_plane_mapping()
247 unsigned int plane_idx = mode_lib->mp.pipe_plane[pipe_idx]; in dml_get_is_phantom_pipe()
257 plane_idx = mode_lib->mp.pipe_plane[pipe_idx]; \
10419 dml_calc_pipe_plane_mapping(cfg_support_info, mode_lib->mp.pipe_plane); in dml_core_mode_programming()
10506 DML_LOG_VERBOSE("DML::%s: pipe=%d is in plane=%d\n", __func__, k, mode_lib->mp.pipe_plane[k]); in dml_core_mode_programming()
12200 unsigned int plane_idx = mode_lib->mp.pipe_plane[pipe_idx]; in dml_get_plane_idx()
12490 l->min_ttu_vblank = mode_lib->mp.MinTTUVBlank[mode_lib->mp.pipe_plane[pipe_idx]]; in rq_dlg_get_dlg_reg()
12491 …_next_start = (unsigned int)(mode_lib->mp.MIN_DST_Y_NEXT_START[mode_lib->mp.pipe_plane[pipe_idx]]); in rq_dlg_get_dlg_reg()
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/linux/drivers/gpu/drm/amd/display/dc/dml2_0/
H A Ddisplay_mode_util.c759 dml_uint_t plane_idx = mode_lib->mp.pipe_plane[pipe_idx]; in dml_get_plane_idx()
771 if (plane_idx == mode_lib->mp.pipe_plane[i]) { in dml_get_pipe_idx()
782 void dml_calc_pipe_plane_mapping(const struct dml_hw_resource_st *hw, dml_uint_t *pipe_plane) in dml_calc_pipe_plane_mapping() argument
787 pipe_plane[k] = __DML_PIPE_NO_PLANE__; in dml_calc_pipe_plane_mapping()
792 pipe_plane[pipe_idx] = plane_idx; in dml_calc_pipe_plane_mapping()
H A Ddisplay_mode_util.h72 …oid dml_calc_pipe_plane_mapping(const struct dml_hw_resource_st *hw, dml_uint_t *pipe_plane);
H A Ddml2_mall_phantom.c258 …ckChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] <= 0)… in assign_subvp_pipe()
624 if (vba->ActiveDRAMClockChangeLatencyMargin[vba->pipe_plane[pipe_idx]] > 0 && in dml2_svp_validate_static_schedulability()
H A Ddisplay_mode_core_structs.h1136 …dml_uint_t pipe_plane[__DML_NUM_PLANES__]; // <brief used mainly by dv to map the pipe inst to pla… member
H A Ddisplay_mode_core.c8316 dml_calc_pipe_plane_mapping(&mode_lib->ms.cache_display_cfg.hw, mode_lib->mp.pipe_plane); in dml_core_mode_programming()
10211 dml_uint_t plane_idx = mode_lib->mp.pipe_plane[pipe_idx]; in dml_get_is_phantom_pipe()
10220 plane_idx = mode_lib->mp.pipe_plane[surface_idx]; \
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/
H A Ddcn20_resource.c1934 int pipe_plane = v->pipe_plane[pipe_idx]; in dcn20_validate_apply_pipe_split_flags() local
1941 if (split4mpc || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 4) in dcn20_validate_apply_pipe_split_flags()
1943 else if (force_split || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 2) in dcn20_validate_apply_pipe_split_flags()
1957 v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_2to1; in dcn20_validate_apply_pipe_split_flags()
1961 v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_4to1; in dcn20_validate_apply_pipe_split_flags()
1968 v->ODMCombineEnabled[pipe_plane] = in dcn20_validate_apply_pipe_split_flags()
1969 v->ODMCombineEnablePerState[vlevel][pipe_plane]; in dcn20_validate_apply_pipe_split_flags()
1971 if (v->ODMCombineEnabled[pipe_plane] == dm_odm_combine_mode_disabled) { in dcn20_validate_apply_pipe_split_flags()
/linux/drivers/gpu/drm/amd/display/dc/dml/
H A Ddisplay_mode_vba.c134 which_plane = mode_lib->vba.pipe_plane[which_pipe]; \
264 if (plane_idx == mode_lib->vba.pipe_plane[i]) { in get_pipe_idx()
282 plane_idx = mode_lib->vba.pipe_plane[pipe_idx]; in get_det_buffer_size_kbytes()
298 plane_idx = mode_lib->vba.pipe_plane[pipe_idx]; in get_is_phantom_pipe()
545 mode_lib->vba.pipe_plane[j] = mode_lib->vba.NumberOfActivePlanes; in fetch_pipe_params()
789 mode_lib->vba.pipe_plane[k] = in fetch_pipe_params()
H A Ddisplay_mode_vba.h589 unsigned int pipe_plane[DC__NUM_DPP__MAX]; member
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c520 num_dpp = vba->NoOfDPP[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]]; in dcn32_set_phantom_stream_timing()
521 phantom_vactive += num_dpp > 1 ? vba->meta_row_height[vba->pipe_plane[pipe_idx]] : 0; in dcn32_set_phantom_stream_timing()
636 …ckChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] <= 0 … in dcn32_assign_subvp_pipe()
637 …ckChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] > 0 && in dcn32_assign_subvp_pipe()
1065 …if (vba->ActiveDRAMClockChangeLatencyMarginPerState[vlevel][vba->maxMpcComb][vba->pipe_plane[pipe_… in subvp_validate_static_schedulability()
1252 odm = vba->ODMCombineEnabled[vba->pipe_plane[dml_pipe_idx]] != in update_pipe_slice_table_with_split_flags()
1734 …lockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] > 0) in dcn32_calculate_dlg_params()
2043 odm = vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled; in dcn32_apply_merge_split_flags_helper()
2226 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled in dcn32_internal_validate_bw()
3542 …ckChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] <= 0)… in dcn32_assign_fpo_vactive_candidate()
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/linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/
H A Ddcn30_resource.c1741 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled in dcn30_internal_validate_bw()
1810 odm = vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled; in dcn30_internal_validate_bw()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn21/
H A Ddcn21_resource.c857 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled in dcn21_fast_validate_bw()