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Searched refs:pipe_dlg_param (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml2_0/
H A Ddml2_utils.c253 pipe_ctx->pipe_dlg_param.vstartup_start = dml_get_vstartup_calculated(mode_lib, pipe_idx); in populate_pipe_ctx_dlg_params_from_dml()
254 pipe_ctx->pipe_dlg_param.vupdate_offset = dml_get_vupdate_offset(mode_lib, pipe_idx); in populate_pipe_ctx_dlg_params_from_dml()
255 pipe_ctx->pipe_dlg_param.vupdate_width = dml_get_vupdate_width(mode_lib, pipe_idx); in populate_pipe_ctx_dlg_params_from_dml()
256 pipe_ctx->pipe_dlg_param.vready_offset = dml_get_vready_offset(mode_lib, pipe_idx); in populate_pipe_ctx_dlg_params_from_dml()
258 pipe_ctx->pipe_dlg_param.otg_inst = pipe_ctx->stream_res.tg->inst; in populate_pipe_ctx_dlg_params_from_dml()
260 pipe_ctx->pipe_dlg_param.hactive = hactive; in populate_pipe_ctx_dlg_params_from_dml()
261 pipe_ctx->pipe_dlg_param.vactive = vactive; in populate_pipe_ctx_dlg_params_from_dml()
262 pipe_ctx->pipe_dlg_param.htotal = pipe_ctx->stream->timing.h_total; in populate_pipe_ctx_dlg_params_from_dml()
263 pipe_ctx->pipe_dlg_param.vtotal = pipe_ctx->stream->timing.v_total; in populate_pipe_ctx_dlg_params_from_dml()
264 pipe_ctx->pipe_dlg_param.hblank_end = hblank_end; in populate_pipe_ctx_dlg_params_from_dml()
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/linux/drivers/gpu/drm/amd/display/dc/dml/calcs/
H A Ddcn_calcs.c445 input->dest.vstartup_start = pipe->pipe_dlg_param.vstartup_start; in pipe_ctx_to_e2e_pipe_params()
446 input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset; in pipe_ctx_to_e2e_pipe_params()
447 input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset; in pipe_ctx_to_e2e_pipe_params()
448 input->dest.vupdate_width = pipe->pipe_dlg_param.vupdate_width; in pipe_ctx_to_e2e_pipe_params()
1209 pipe->pipe_dlg_param.vupdate_width = v->v_update_width_pix[input_idx]; in dcn_validate_bandwidth()
1210 pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset_pix[input_idx]; in dcn_validate_bandwidth()
1211 pipe->pipe_dlg_param.vready_offset = v->v_ready_offset_pix[input_idx]; in dcn_validate_bandwidth()
1212 pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx]; in dcn_validate_bandwidth()
1214 pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total; in dcn_validate_bandwidth()
1215 pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total; in dcn_validate_bandwidth()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
H A Ddcn20_hwseq.c910 pipe_ctx->pipe_dlg_param.vready_offset, in dcn20_enable_stream_timing()
911 pipe_ctx->pipe_dlg_param.vstartup_start, in dcn20_enable_stream_timing()
912 pipe_ctx->pipe_dlg_param.vupdate_offset, in dcn20_enable_stream_timing()
913 pipe_ctx->pipe_dlg_param.vupdate_width, in dcn20_enable_stream_timing()
914 pipe_ctx->pipe_dlg_param.pstate_keepout, in dcn20_enable_stream_timing()
1558 if (old_pipe->pipe_dlg_param.vready_offset != new_pipe->pipe_dlg_param.vready_offset in dcn20_detect_pipe_changes()
1559 || old_pipe->pipe_dlg_param.vstartup_start != new_pipe->pipe_dlg_param.vstartup_start in dcn20_detect_pipe_changes()
1560 || old_pipe->pipe_dlg_param.vupdate_offset != new_pipe->pipe_dlg_param.vupdate_offset in dcn20_detect_pipe_changes()
1561 || old_pipe->pipe_dlg_param.vupdate_width != new_pipe->pipe_dlg_param.vupdate_width) in dcn20_detect_pipe_changes()
1703 &pipe_ctx->pipe_dlg_param); in dcn20_update_dchubp_dpp()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
H A Ddcn10_hwseq.c139 vblank_start = pipe_ctx->pipe_dlg_param.vblank_start; in dcn10_wait_for_pipe_update_if_needed()
1156 int vready_offset = pipe->pipe_dlg_param.vready_offset; in calculate_vready_offset_for_group()
1160 if (other_pipe->pipe_dlg_param.vready_offset > vready_offset) in calculate_vready_offset_for_group()
1161 vready_offset = other_pipe->pipe_dlg_param.vready_offset; in calculate_vready_offset_for_group()
1164 if (other_pipe->pipe_dlg_param.vready_offset > vready_offset) in calculate_vready_offset_for_group()
1165 vready_offset = other_pipe->pipe_dlg_param.vready_offset; in calculate_vready_offset_for_group()
1168 if (other_pipe->pipe_dlg_param.vready_offset > vready_offset) in calculate_vready_offset_for_group()
1169 vready_offset = other_pipe->pipe_dlg_param.vready_offset; in calculate_vready_offset_for_group()
1172 if (other_pipe->pipe_dlg_param.vready_offset > vready_offset) in calculate_vready_offset_for_group()
1173 vready_offset = other_pipe->pipe_dlg_param.vready_offset; in calculate_vready_offset_for_group()
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/linux/drivers/gpu/drm/amd/display/dc/inc/
H A Dcore_types.h485 struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param; member
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c357 pipe->pipe_dlg_param = pipes[pipe_idx].pipe.dest; in dcn32_helper_populate_phantom_dlg_params()
1730 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest; in dcn32_calculate_dlg_params()
1762 &context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start); in dcn32_calculate_dlg_params()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn10/
H A Ddcn10_resource.c1302 return pipe_ctx->pipe_dlg_param.vstartup_start; in dcn10_get_vstartup_for_pipe()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.c1202 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest; in dcn20_calculate_dlg_params()
1207 &context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start); in dcn20_calculate_dlg_params()
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_dmub_srv.c694 pipe_data->pipe_config.vblank_data.vstartup_start = vblank_pipe->pipe_dlg_param.vstartup_start; in populate_subvp_cmd_vblank_pipe_info()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.c3619 &pipe_ctx->ttu_regs, &pipe_ctx->rq_regs, &pipe_ctx->pipe_dlg_param); in dcn401_update_dchubp_dpp_sequence()