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Searched refs:pipe_ctx (Results 1 – 25 of 121) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/hwss/dce60/
H A Ddce60_hwseq.c55 struct pipe_ctx *pipe_ctx = NULL; in dce60_should_enable_fbc() local
71 if (res_ctx->pipe_ctx[i].stream) { in dce60_should_enable_fbc()
73 pipe_ctx = &res_ctx->pipe_ctx[i]; in dce60_should_enable_fbc()
75 if (!pipe_ctx) in dce60_should_enable_fbc()
79 if (pipe_ctx->pipe_idx != underlay_idx) { in dce60_should_enable_fbc()
89 if (!pipe_ctx->stream->link) in dce60_should_enable_fbc()
93 if (pipe_ctx->stream->link->connector_signal != SIGNAL_TYPE_EDP) in dce60_should_enable_fbc()
97 if (pipe_ctx->stream->link->psr_settings.psr_feature_enabled) in dce60_should_enable_fbc()
101 if (!pipe_ctx->plane_state) in dce60_should_enable_fbc()
105 if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL) in dce60_should_enable_fbc()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
H A Ddcn20_hwseq.h34 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
36 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
43 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);
44 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);
45 bool dcn20_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
47 bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
50 struct pipe_ctx *pipe_ctx,
54 void dcn20_enable_stream(struct pipe_ctx *pipe_ctx);
55 void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,
57 void dcn20_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);
[all …]
H A Ddcn20_hwseq.c220 struct pipe_ctx *pipe_ctx, in dcn20_setup_gsl_group_as_lock() argument
232 if (pipe_ctx->stream_res.gsl_group > 0) in dcn20_setup_gsl_group_as_lock()
237 pipe_ctx->stream_res.gsl_group = group_idx; in dcn20_setup_gsl_group_as_lock()
259 group_idx = pipe_ctx->stream_res.gsl_group; in dcn20_setup_gsl_group_as_lock()
263 pipe_ctx->stream_res.gsl_group = 0; in dcn20_setup_gsl_group_as_lock()
287 if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL) { in dcn20_setup_gsl_group_as_lock()
288 pipe_ctx->stream_res.tg->funcs->set_gsl( in dcn20_setup_gsl_group_as_lock()
289 pipe_ctx->stream_res.tg, in dcn20_setup_gsl_group_as_lock()
291 if (pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) in dcn20_setup_gsl_group_as_lock()
292 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select( in dcn20_setup_gsl_group_as_lock()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/
H A Dhw_sequencer_private.h56 struct pipe_ctx;
77 void (*disable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
78 void (*enable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
83 struct pipe_ctx *pipe_ctx);
86 struct pipe_ctx *pipe_ctx,
88 void (*update_mpcc)(struct dc *dc, struct pipe_ctx *pipe_ctx);
89 void (*update_mpcc_sequence)(struct dc *dc, struct pipe_ctx *pipe_ctx,
92 struct pipe_ctx *pipe_ctx,
95 struct pipe_ctx *pipe_ctx,
105 struct pipe_ctx *pipe_ctx,
[all …]
H A Dhw_sequencer.h37 struct pipe_ctx;
64 struct pipe_ctx *pipe_ctx; member
75 struct pipe_ctx *pipe_ctx; member
81 struct pipe_ctx *pipe_ctx; member
86 struct pipe_ctx *pipe_ctx; member
91 struct pipe_ctx *pipe_ctx; member
95 struct pipe_ctx *pipe_ctx; member
105 struct pipe_ctx *pipe_ctx; member
109 struct pipe_ctx *pipe_ctx; member
114 struct pipe_ctx *pipe_ctx; member
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/linux/drivers/gpu/drm/amd/display/dc/link/
H A Dlink_dpms.c152 struct pipe_ctx *pipes[MAX_PIPES]; in link_set_all_streams_dpms_off_for_link()
197 const struct pipe_ctx *pipe) in is_master_pipe_for_link()
210 struct pipe_ctx *pipes[MAX_PIPES]) in link_get_master_pipes_with_dpms_on()
213 struct pipe_ctx *pipe = NULL; in link_get_master_pipes_with_dpms_on()
217 pipe = &state->res_ctx.pipe_ctx[i]; in link_get_master_pipes_with_dpms_on()
226 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx, in get_ext_hdmi_settings() argument
233 pipe_ctx->stream->ctx->dc_bios->integrated_info; in get_ext_hdmi_settings()
323 static bool write_i2c(struct pipe_ctx *pipe_ctx, in write_i2c() argument
334 cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz; in write_i2c()
342 if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx, in write_i2c()
[all …]
H A Dlink_dpms.h32 struct pipe_ctx *pipe_ctx);
33 void link_set_dpms_off(struct pipe_ctx *pipe_ctx);
42 struct pipe_ctx *pipes[MAX_PIPES]);
43 enum dc_status link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t req_pbn);
44 enum dc_status link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t req_pbn);
45 bool link_set_dsc_pps_packet(struct pipe_ctx *pipe_ctx,
50 void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable);
51 bool link_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable);
52 bool link_update_dsc_config(struct pipe_ctx *pipe_ctx);
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.c91 void dcn401_program_gamut_remap(struct pipe_ctx *pipe_ctx) in dcn401_program_gamut_remap() argument
95 unsigned int mpcc_id = pipe_ctx->plane_res.mpcc_inst; in dcn401_program_gamut_remap()
96 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn401_program_gamut_remap()
99 if (pipe_ctx->plane_state) in dcn401_program_gamut_remap()
100 ASSERT(pipe_ctx->plane_state->mcm_location == MPCC_MOVABLE_CM_LOCATION_BEFORE); in dcn401_program_gamut_remap()
107 if (pipe_ctx->plane_state && in dcn401_program_gamut_remap()
108 pipe_ctx->plane_state->gamut_remap_matrix.enable_remap == true) { in dcn401_program_gamut_remap()
112 pipe_ctx->plane_state->gamut_remap_matrix.matrix[i]; in dcn401_program_gamut_remap()
128 if (pipe_ctx->top_pipe == NULL) { in dcn401_program_gamut_remap()
129 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { in dcn401_program_gamut_remap()
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H A Ddcn401_hwseq.h35 void dcn401_program_gamut_remap(struct pipe_ctx *pipe_ctx);
39 bool dcn401_set_mcm_luts(struct pipe_ctx *pipe_ctx,
42 struct pipe_ctx *pipe_ctx,
45 struct pipe_ctx *pipe_ctx);
46 void dcn401_calculate_dccg_tmds_div_value(struct pipe_ctx *pipe_ctx,
49 struct pipe_ctx *pipe_ctx,
52 void dcn401_enable_stream(struct pipe_ctx *pipe_ctx);
54 struct pipe_ctx *pipe_ctx,
63 void dcn401_set_cursor_position(struct pipe_ctx *pipe_ctx);
68 const struct pipe_ctx *top_pipe_to_program);
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/
H A Ddce110_hwseq.c284 dce110_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, in dce110_set_input_transfer_func() argument
287 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; in dce110_set_input_transfer_func()
607 dce110_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, in dce110_set_output_transfer_func() argument
610 struct transform *xfm = pipe_ctx->plane_res.xfm; in dce110_set_output_transfer_func()
631 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx) in dce110_update_info_frame() argument
636 ASSERT(pipe_ctx->stream); in dce110_update_info_frame()
638 if (pipe_ctx->stream_res.stream_enc == NULL) in dce110_update_info_frame()
641 is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal); in dce110_update_info_frame()
642 is_dp = dc_is_dp_signal(pipe_ctx->stream->signal); in dce110_update_info_frame()
648 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( in dce110_update_info_frame()
[all …]
H A Ddce110_hwseq.h43 struct pipe_ctx *pipe_ctx,
47 void dce110_enable_stream(struct pipe_ctx *pipe_ctx);
49 void dce110_disable_stream(struct pipe_ctx *pipe_ctx);
51 void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
54 void dce110_blank_stream(struct pipe_ctx *pipe_ctx);
56 void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx);
57 void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx);
59 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx);
61 void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);
90 bool dce110_set_backlight_level(struct pipe_ctx *pipe_ctx,
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/linux/drivers/gpu/drm/amd/display/dc/link/hwss/
H A Dlink_hwss_dio.c39 void set_dio_throttled_vcp_size(struct pipe_ctx *pipe_ctx, in set_dio_throttled_vcp_size() argument
42 struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc; in set_dio_throttled_vcp_size()
49 void setup_dio_stream_encoder(struct pipe_ctx *pipe_ctx) in setup_dio_stream_encoder() argument
51 struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc; in setup_dio_stream_encoder()
52 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; in setup_dio_stream_encoder()
54 if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment) in setup_dio_stream_encoder()
55 link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link); in setup_dio_stream_encoder()
61 if (!dc_is_rgb_signal(pipe_ctx->stream->signal)) in setup_dio_stream_encoder()
63 pipe_ctx->stream_res.stream_enc->id, true); in setup_dio_stream_encoder()
64 if (dc_is_dp_signal(pipe_ctx->stream->signal)) in setup_dio_stream_encoder()
[all …]
H A Dlink_hwss_hpo_dp.c33 void set_hpo_dp_throttled_vcp_size(struct pipe_ctx *pipe_ctx, in set_hpo_dp_throttled_vcp_size() argument
37 pipe_ctx->stream_res.hpo_dp_stream_enc; in set_hpo_dp_throttled_vcp_size()
39 pipe_ctx->link_res.hpo_dp_link_enc; in set_hpo_dp_throttled_vcp_size()
46 void set_hpo_dp_hblank_min_symbol_width(struct pipe_ctx *pipe_ctx, in set_hpo_dp_hblank_min_symbol_width() argument
51 pipe_ctx->stream_res.hpo_dp_stream_enc; in set_hpo_dp_hblank_min_symbol_width()
52 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; in set_hpo_dp_hblank_min_symbol_width()
56 pipe_ctx->stream->link, link_settings); in set_hpo_dp_hblank_min_symbol_width()
74 void setup_hpo_dp_stream_encoder(struct pipe_ctx *pipe_ctx) in setup_hpo_dp_stream_encoder() argument
76 struct hpo_dp_stream_encoder *stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc; in setup_hpo_dp_stream_encoder()
77 struct hpo_dp_link_encoder *link_enc = pipe_ctx->link_res.hpo_dp_link_enc; in setup_hpo_dp_stream_encoder()
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H A Dlink_hwss_hpo_dp.h31 void set_hpo_dp_throttled_vcp_size(struct pipe_ctx *pipe_ctx,
33 void set_hpo_dp_hblank_min_symbol_width(struct pipe_ctx *pipe_ctx,
36 void set_hpo_dp_hblank_min_symbol_width(struct pipe_ctx *pipe_ctx,
39 void setup_hpo_dp_stream_encoder(struct pipe_ctx *pipe_ctx);
40 void reset_hpo_dp_stream_encoder(struct pipe_ctx *pipe_ctx);
41 void setup_hpo_dp_stream_attribute(struct pipe_ctx *pipe_ctx);
53 void setup_hpo_dp_audio_output(struct pipe_ctx *pipe_ctx,
55 void enable_hpo_dp_audio_packet(struct pipe_ctx *pipe_ctx);
56 void disable_hpo_dp_audio_packet(struct pipe_ctx *pipe_ctx);
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
H A Ddcn10_hwseq.c102 void dcn10_wait_for_pipe_update_if_needed(struct dc *dc, struct pipe_ctx *pipe_ctx, bool is_surface… in dcn10_wait_for_pipe_update_if_needed() argument
105 struct dc_stream_state *stream = pipe_ctx->stream; in dcn10_wait_for_pipe_update_if_needed()
111 if (!pipe_ctx->stream || in dcn10_wait_for_pipe_update_if_needed()
112 !pipe_ctx->stream_res.tg || in dcn10_wait_for_pipe_update_if_needed()
113 !pipe_ctx->stream_res.stream_enc) in dcn10_wait_for_pipe_update_if_needed()
116 if (pipe_ctx->prev_odm_pipe && in dcn10_wait_for_pipe_update_if_needed()
117 pipe_ctx->stream) in dcn10_wait_for_pipe_update_if_needed()
120 if (!pipe_ctx->wait_is_required) in dcn10_wait_for_pipe_update_if_needed()
123 struct timing_generator *tg = pipe_ctx->stream_res.tg; in dcn10_wait_for_pipe_update_if_needed()
128 dc->hwss.calc_vupdate_position(dc, pipe_ctx, &vupdate_start, in dcn10_wait_for_pipe_update_if_needed()
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/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_resource.c701 const struct pipe_ctx *pipe_with_clk_src, in is_sharable_clk_src()
702 const struct pipe_ctx *pipe) in is_sharable_clk_src()
733 struct pipe_ctx *pipe_ctx) in resource_find_used_clk_src_for_sharing() argument
738 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx)) in resource_find_used_clk_src_for_sharing()
739 return res_ctx->pipe_ctx[i].clock_source; in resource_find_used_clk_src_for_sharing()
852 struct pipe_ctx *pipe_ctx, in calculate_plane_rec_in_timing_active() argument
916 const struct dc_stream_state *stream = pipe_ctx->stream; in calculate_plane_rec_in_timing_active()
942 struct pipe_ctx *pipe_ctx, in calculate_mpc_slice_in_timing_active() argument
945 const struct dc_stream_state *stream = pipe_ctx->stream; in calculate_mpc_slice_in_timing_active()
946 int mpc_slice_count = resource_get_mpc_slice_count(pipe_ctx); in calculate_mpc_slice_in_timing_active()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/inc/
H A Dresource.h116 struct pipe_ctx *pipe_ctx);
118 bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx);
124 void resource_build_info_frame(struct pipe_ctx *pipe_ctx);
151 struct pipe_ctx *pipe_ctx);
164 bool resource_can_pipe_disable_cursor(struct pipe_ctx *pipe_ctx);
287 bool resource_is_pipe_type(const struct pipe_ctx *pipe_ctx, enum pipe_type type);
315 struct pipe_ctx *otg_master_pipe,
379 struct pipe_ctx *resource_get_otg_master_for_stream(
389 int resource_get_opp_heads_for_otg_master(const struct pipe_ctx *otg_master,
391 struct pipe_ctx *opp_heads[MAX_PIPES]);
[all …]
H A Dlink_hwss.h38 struct pipe_ctx;
49 void (*set_hblank_min_symbol_width)(struct pipe_ctx *pipe_ctx,
52 void (*set_throttled_vcp_size)(struct pipe_ctx *pipe_ctx,
77 void (*setup_stream_encoder)(struct pipe_ctx *pipe_ctx);
78 void (*reset_stream_encoder)(struct pipe_ctx *pipe_ctx);
79 void (*setup_stream_attribute)(struct pipe_ctx *pipe_ctx);
83 void (*setup_audio_output)(struct pipe_ctx *pipe_ctx,
85 void (*enable_audio_packet)(struct pipe_ctx *pipe_ctx);
86 void (*disable_audio_packet)(struct pipe_ctx *pipe_ctx);
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/
H A Ddcn201_hwseq.c60 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr) in patch_address_for_sbs_tb_stereo() argument
62 struct dc_plane_state *plane_state = pipe_ctx->plane_state; in patch_address_for_sbs_tb_stereo()
63 bool sec_split = pipe_ctx->top_pipe && in patch_address_for_sbs_tb_stereo()
64 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state; in patch_address_for_sbs_tb_stereo()
67 (pipe_ctx->stream->timing.timing_3d_format == in patch_address_for_sbs_tb_stereo()
69 pipe_ctx->stream->timing.timing_3d_format == in patch_address_for_sbs_tb_stereo()
76 if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE && in patch_address_for_sbs_tb_stereo()
136 void dcn201_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx) in dcn201_update_plane_addr() argument
140 struct dc_plane_state *plane_state = pipe_ctx->plane_state; in dcn201_update_plane_addr()
148 addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr); in dcn201_update_plane_addr()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/basics/
H A Ddc_common.c53 bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx) in is_lower_pipe_tree_visible() argument
55 if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible) in is_lower_pipe_tree_visible()
57 if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe)) in is_lower_pipe_tree_visible()
62 bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx) in is_upper_pipe_tree_visible() argument
64 if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible) in is_upper_pipe_tree_visible()
66 if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe)) in is_upper_pipe_tree_visible()
71 bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx) in is_pipe_tree_visible() argument
73 if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible) in is_pipe_tree_visible()
75 if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe)) in is_pipe_tree_visible()
77 if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe)) in is_pipe_tree_visible()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
H A Ddcn35_hwseq.c327 static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) in update_dsc_on_stream() argument
329 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; in update_dsc_on_stream()
330 struct dc_stream_state *stream = pipe_ctx->stream; in update_dsc_on_stream()
331 struct pipe_ctx *odm_pipe; in update_dsc_on_stream()
337 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) in update_dsc_on_stream()
347 DC_LOG_DSC("DSC is NULL for tg instance %d:", pipe_ctx->stream_res.tg->inst); in update_dsc_on_stream()
354 DC_LOG_DSC("DSC has been disabled for tg instance %d:", pipe_ctx->stream_res.tg->inst); in update_dsc_on_stream()
363 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; in update_dsc_on_stream()
370 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); in update_dsc_on_stream()
371 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { in update_dsc_on_stream()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
H A Ddcn30_hwseq.h59 bool dcn30_set_blend_lut(struct pipe_ctx *pipe_ctx,
63 struct pipe_ctx *pipe_ctx,
66 void dcn30_program_gamut_remap(struct pipe_ctx *pipe_ctx);
69 struct pipe_ctx *pipe_ctx,
71 void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);
72 void dcn30_update_info_frame(struct pipe_ctx *pipe_ctx);
73 void dcn30_program_dmdata_engine(struct pipe_ctx *pipe_ctx);
86 struct pipe_ctx *pipe_ctx,
94 struct pipe_ctx *pipe_ctx,
100 void dcn30_wait_for_all_pending_updates(const struct pipe_ctx *pipe_ctx);
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
H A Ddcn32_hwseq.c239 struct pipe_ctx *pipe = &ctx->res_ctx.pipe_ctx[i]; in dcn32_calculate_cab_allocation()
361 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dcn32_commit_subvp_config() local
363 if (pipe_ctx->stream && dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_MAIN) { in dcn32_commit_subvp_config()
382 struct pipe_ctx *top_pipe_to_program, in dcn32_subvp_pipe_control_lock()
388 struct pipe_ctx *pipe; in dcn32_subvp_pipe_control_lock()
392 pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_subvp_pipe_control_lock()
413 pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_subvp_pipe_control_lock()
447 struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream) in dcn32_set_mpc_shaper_3dlut() argument
449 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn32_set_mpc_shaper_3dlut()
450 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn32_set_mpc_shaper_3dlut()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn21/
H A Ddcn21_hwseq.c128 void dcn21_PLAT_58856_wa(struct dc_state *context, struct pipe_ctx *pipe_ctx) in dcn21_PLAT_58856_wa() argument
130 if (!pipe_ctx->stream->dpms_off) in dcn21_PLAT_58856_wa()
133 pipe_ctx->stream->dpms_off = false; in dcn21_PLAT_58856_wa()
134 pipe_ctx->stream->ctx->dc->link_srv->set_dpms_on(context, pipe_ctx); in dcn21_PLAT_58856_wa()
135 pipe_ctx->stream->ctx->dc->link_srv->set_dpms_off(pipe_ctx); in dcn21_PLAT_58856_wa()
136 pipe_ctx->stream->dpms_off = true; in dcn21_PLAT_58856_wa()
178 void dcn21_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx) in dcn21_set_abm_immediate_disable() argument
180 struct abm *abm = pipe_ctx->stream_res.abm; in dcn21_set_abm_immediate_disable()
181 uint32_t otg_inst = pipe_ctx->stream_res.tg->inst; in dcn21_set_abm_immediate_disable()
182 struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl; in dcn21_set_abm_immediate_disable()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn31/
H A Ddcn31_hwseq.c376 void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx) in dcn31_update_info_frame() argument
381 ASSERT(pipe_ctx->stream); in dcn31_update_info_frame()
383 if (pipe_ctx->stream_res.stream_enc == NULL) in dcn31_update_info_frame()
386 is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal); in dcn31_update_info_frame()
387 is_dp = dc_is_dp_signal(pipe_ctx->stream->signal); in dcn31_update_info_frame()
393 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( in dcn31_update_info_frame()
394 pipe_ctx->stream_res.stream_enc, in dcn31_update_info_frame()
395 &pipe_ctx->stream_res.encoder_info_frame); in dcn31_update_info_frame()
396 else if (pipe_ctx->stream->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { in dcn31_update_info_frame()
397 if (pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->update_dp_info_packets_sdp_line_num) in dcn31_update_info_frame()
[all …]

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