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Searched refs:pipe_config (Results 1 – 25 of 43) sorted by relevance

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/linux/drivers/gpu/drm/i915/display/
H A Dg4x_dp.c62 struct intel_crtc_state *pipe_config) in g4x_dp_set_clock() argument
84 if (pipe_config->port_clock == divisor[i].dot) { in g4x_dp_set_clock()
85 pipe_config->dpll = divisor[i]; in g4x_dp_set_clock()
86 pipe_config->clock_set = true; in g4x_dp_set_clock()
94 const struct intel_crtc_state *pipe_config) in intel_dp_prepare() argument
99 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in intel_dp_prepare()
100 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; in intel_dp_prepare()
103 pipe_config->port_clock, in intel_dp_prepare()
104 pipe_config->lane_count); in intel_dp_prepare()
129 intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count); in intel_dp_prepare()
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H A Dintel_dp_mst.c599 struct intel_crtc_state *pipe_config, in mst_stream_compute_config() argument
604 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in mst_stream_compute_config()
609 &pipe_config->hw.adjusted_mode; in mst_stream_compute_config()
615 if (pipe_config->fec_enable && in mst_stream_compute_config()
616 !intel_dp_supports_fec(intel_dp, connector, pipe_config)) in mst_stream_compute_config()
626 pipe_config->joiner_pipes = GENMASK(crtc->pipe + num_joined_pipes - 1, crtc->pipe); in mst_stream_compute_config()
628 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; in mst_stream_compute_config()
629 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; in mst_stream_compute_config()
630 pipe_config->has_pch_encoder = false; in mst_stream_compute_config()
636 pipe_config, false, &limits); in mst_stream_compute_config()
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H A Dintel_dp.c1622 const struct intel_crtc_state *pipe_config) in intel_dp_source_supports_fec() argument
1631 !intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST)) in intel_dp_source_supports_fec()
1639 const struct intel_crtc_state *pipe_config) in intel_dp_supports_fec() argument
1641 return intel_dp_source_supports_fec(intel_dp, pipe_config) && in intel_dp_supports_fec()
1759 struct intel_crtc_state *pipe_config, in intel_dp_compute_link_config_wide() argument
1763 int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state); in intel_dp_compute_link_config_wide()
1770 intel_dp_output_format_link_bpp_x16(pipe_config->output_format, bpp); in intel_dp_compute_link_config_wide()
1782 &pipe_config->hw.adjusted_mode; in intel_dp_compute_link_config_wide()
1793 pipe_config->lane_count = lane_count; in intel_dp_compute_link_config_wide()
1794 pipe_config->pipe_bpp = bpp; in intel_dp_compute_link_config_wide()
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H A Dintel_dvo.c162 struct intel_crtc_state *pipe_config) in intel_dvo_get_config() argument
168 pipe_config->output_types |= BIT(INTEL_OUTPUT_DVO); in intel_dvo_get_config()
180 pipe_config->hw.adjusted_mode.flags |= flags; in intel_dvo_get_config()
182 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; in intel_dvo_get_config()
202 const struct intel_crtc_state *pipe_config, in intel_enable_dvo() argument
210 &pipe_config->hw.mode, in intel_enable_dvo()
211 &pipe_config->hw.adjusted_mode); in intel_enable_dvo()
255 struct intel_crtc_state *pipe_config, in intel_dvo_compute_config() argument
260 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; in intel_dvo_compute_config()
281 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; in intel_dvo_compute_config()
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H A Dintel_display.c2853 struct intel_crtc_state *pipe_config) in intel_get_transcoder_timings() argument
2856 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; in intel_get_transcoder_timings()
2857 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; in intel_get_transcoder_timings()
2890 if (intel_pipe_is_interlaced(pipe_config)) { in intel_get_transcoder_timings()
2897 pipe_config->set_context_latency = in intel_get_transcoder_timings()
2902 pipe_config->set_context_latency; in intel_get_transcoder_timings()
2911 pipe_config->set_context_latency = in intel_get_transcoder_timings()
2916 pipe_config->min_hblank = intel_de_read(display, in intel_get_transcoder_timings()
2938 struct intel_crtc_state *pipe_config) in intel_get_pipe_src_size() argument
2945 drm_rect_init(&pipe_config->pipe_src, 0, 0, in intel_get_pipe_src_size()
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H A Dicl_dsi.c296 const struct intel_crtc_state *pipe_config) in configure_dual_link_mode() argument
305 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in configure_dual_link_mode()
321 &pipe_config->hw.adjusted_mode; in configure_dual_link_mode()
701 const struct intel_crtc_state *pipe_config) in gen11_dsi_configure_transcoder() argument
705 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in gen11_dsi_configure_transcoder()
721 if (afe_clk(encoder, pipe_config) >= 1500 * 1000) { in gen11_dsi_configure_transcoder()
747 if (pipe_config->dsc.compression_enable) { in gen11_dsi_configure_transcoder()
815 configure_dual_link_mode(encoder, pipe_config); in gen11_dsi_configure_transcoder()
1220 const struct intel_crtc_state *pipe_config, in gen11_dsi_pre_enable() argument
1224 gen11_dsi_map_pll(encoder, pipe_config); in gen11_dsi_pre_enable()
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H A Dvlv_dsi.c271 struct intel_crtc_state *pipe_config, in intel_dsi_compute_config() argument
277 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; in intel_dsi_compute_config()
281 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; in intel_dsi_compute_config()
282 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; in intel_dsi_compute_config()
288 ret = intel_pfit_compute_config(pipe_config, conn_state); in intel_dsi_compute_config()
299 pipe_config->pipe_bpp = 24; in intel_dsi_compute_config()
301 pipe_config->pipe_bpp = 18; in intel_dsi_compute_config()
305 pipe_config->mode_flags |= in intel_dsi_compute_config()
310 pipe_config->cpu_transcoder = TRANSCODER_DSI_C; in intel_dsi_compute_config()
312 pipe_config->cpu_transcoder = TRANSCODER_DSI_A; in intel_dsi_compute_config()
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H A Dintel_fdi.c186 struct intel_crtc_state *pipe_config, in ilk_check_fdi_lanes() argument
189 struct drm_atomic_state *state = pipe_config->uapi.state; in ilk_check_fdi_lanes()
197 pipe_name(pipe), pipe_config->fdi_lanes); in ilk_check_fdi_lanes()
198 if (pipe_config->fdi_lanes > 4) { in ilk_check_fdi_lanes()
201 pipe_name(pipe), pipe_config->fdi_lanes); in ilk_check_fdi_lanes()
206 if (pipe_config->fdi_lanes > 2) { in ilk_check_fdi_lanes()
209 pipe_config->fdi_lanes); in ilk_check_fdi_lanes()
224 if (pipe_config->fdi_lanes <= 2) in ilk_check_fdi_lanes()
236 pipe_name(pipe), pipe_config->fdi_lanes); in ilk_check_fdi_lanes()
241 if (pipe_config->fdi_lanes > 2) { in ilk_check_fdi_lanes()
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H A Dintel_vdsc.c240 static int intel_dsc_slice_dimensions_valid(struct intel_crtc_state *pipe_config, in intel_dsc_slice_dimensions_valid() argument
243 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_RGB || in intel_dsc_slice_dimensions_valid()
244 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) { in intel_dsc_slice_dimensions_valid()
249 } else if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { in intel_dsc_slice_dimensions_valid()
272 int intel_dsc_compute_params(struct intel_crtc_state *pipe_config) in intel_dsc_compute_params() argument
274 struct intel_display *display = to_intel_display(pipe_config); in intel_dsc_compute_params()
275 struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config; in intel_dsc_compute_params()
276 u16 compressed_bpp = fxp_q4_to_int(pipe_config->dsc.compressed_bpp_x16); in intel_dsc_compute_params()
280 vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay; in intel_dsc_compute_params()
282 pipe_config->dsc.slice_count); in intel_dsc_compute_params()
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H A Dintel_tv.c929 const struct intel_crtc_state *pipe_config, in intel_enable_tv() argument
935 intel_crtc_wait_for_next_vblank(to_intel_crtc(pipe_config->uapi.crtc)); in intel_enable_tv()
1092 struct intel_crtc_state *pipe_config) in intel_tv_get_config() argument
1096 &pipe_config->hw.adjusted_mode; in intel_tv_get_config()
1104 pipe_config->output_types |= BIT(INTEL_OUTPUT_TVOUT); in intel_tv_get_config()
1126 tv_mode.clock = pipe_config->port_clock; in intel_tv_get_config()
1153 intel_tv_mode_to_mode(&mode, &tv_mode, pipe_config->port_clock); in intel_tv_get_config()
1169 pipe_config->mode_flags |= in intel_tv_get_config()
1191 struct intel_crtc_state *pipe_config, in intel_tv_compute_config() argument
1196 to_intel_atomic_state(pipe_config->uapi.state); in intel_tv_compute_config()
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H A Dintel_sdvo.c1282 static int i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config) in i9xx_adjust_sdvo_tv_clock() argument
1284 struct intel_display *display = to_intel_display(pipe_config); in i9xx_adjust_sdvo_tv_clock()
1285 unsigned int dotclock = pipe_config->hw.adjusted_mode.crtc_clock; in i9xx_adjust_sdvo_tv_clock()
1286 struct dpll *clock = &pipe_config->dpll; in i9xx_adjust_sdvo_tv_clock()
1310 pipe_config->clock_set = true; in i9xx_adjust_sdvo_tv_clock()
1358 struct intel_crtc_state *pipe_config, in intel_sdvo_compute_config() argument
1365 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; in intel_sdvo_compute_config()
1366 struct drm_display_mode *mode = &pipe_config->hw.mode; in intel_sdvo_compute_config()
1369 pipe_config->has_pch_encoder = true; in intel_sdvo_compute_config()
1370 if (!intel_link_bw_compute_pipe_bpp(pipe_config)) in intel_sdvo_compute_config()
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H A Dintel_lspcon.h22 const struct intel_crtc_state *pipe_config);
38 const struct intel_crtc_state *pipe_config);
H A Dintel_fdi.h22 const struct intel_crtc_state *pipe_config);
24 struct intel_crtc_state *pipe_config);
H A Dintel_lspcon.c643 const struct intel_crtc_state *pipe_config) in lspcon_infoframes_enabled() argument
662 HSW_TVIDEO_DIP_CTL(display, pipe_config->cpu_transcoder)); in lspcon_infoframes_enabled()
718 const struct intel_crtc_state *pipe_config) in intel_lspcon_infoframes_enabled() argument
722 return dig_port->infoframes_enabled(encoder, pipe_config); in intel_lspcon_infoframes_enabled()
H A Dintel_dp_test.h17 struct intel_crtc_state *pipe_config,
H A Dintel_vdsc.h23 int intel_dsc_compute_params(struct intel_crtc_state *pipe_config);
H A Dintel_hdcp.h33 const struct intel_crtc_state *pipe_config,
H A Dintel_hdmi.h30 struct intel_crtc_state *pipe_config,
H A Dintel_psr.c1900 struct intel_crtc_state *pipe_config) in intel_psr_get_config() argument
1904 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; in intel_psr_get_config()
1920 pipe_config->has_psr = pipe_config->has_panel_replay = true; in intel_psr_get_config()
1926 pipe_config->has_psr = true; in intel_psr_get_config()
1929 pipe_config->has_sel_update = intel_dp->psr.sel_update_enabled; in intel_psr_get_config()
1930 pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); in intel_psr_get_config()
1939 pipe_config->enable_psr2_sel_fetch = true; in intel_psr_get_config()
1942 pipe_config->enable_psr2_su_region_et = intel_dp->psr.su_region_et_enabled; in intel_psr_get_config()
1947 pipe_config->dc3co_exitline = REG_FIELD_GET(EXITLINE_MASK, val); in intel_psr_get_config()
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_dmub_srv.c609 pipe_data->pipe_config.vblank_data.drr_info.drr_in_use = true; in populate_subvp_cmd_drr_info()
610 pipe_data->pipe_config.vblank_data.drr_info.use_ramping = false; // for now don't use ramping in populate_subvp_cmd_drr_info()
611 …pipe_data->pipe_config.vblank_data.drr_info.drr_window_size_ms = 4; // hardcode 4ms DRR window for… in populate_subvp_cmd_drr_info()
642 pipe_data->pipe_config.vblank_data.drr_info.min_vtotal_supported = min_vtotal_supported; in populate_subvp_cmd_drr_info()
643 pipe_data->pipe_config.vblank_data.drr_info.max_vtotal_supported = max_vtotal_supported; in populate_subvp_cmd_drr_info()
644 …pipe_data->pipe_config.vblank_data.drr_info.drr_vblank_start_margin = dc->caps.subvp_drr_vblank_st… in populate_subvp_cmd_drr_info()
688 pipe_data->pipe_config.vblank_data.pix_clk_100hz = vblank_pipe->stream->timing.pix_clk_100hz; in populate_subvp_cmd_vblank_pipe_info()
689 pipe_data->pipe_config.vblank_data.vblank_start = vblank_pipe->stream->timing.v_total - in populate_subvp_cmd_vblank_pipe_info()
691 pipe_data->pipe_config.vblank_data.vtotal = vblank_pipe->stream->timing.v_total; in populate_subvp_cmd_vblank_pipe_info()
692 pipe_data->pipe_config.vblank_data.htotal = vblank_pipe->stream->timing.h_total; in populate_subvp_cmd_vblank_pipe_info()
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/linux/drivers/usb/renesas_usbhs/
H A Dpipe.c477 struct renesas_usbhs_driver_pipe_config *pipe_config = in usbhsp_setup_pipebuff() local
489 buff_size = pipe_config->bufsize; in usbhsp_setup_pipebuff()
490 bufnmb = pipe_config->bufnum; in usbhsp_setup_pipebuff()
507 struct renesas_usbhs_driver_pipe_config *pipe_config = in usbhs_pipe_config_update() local
509 u16 dblb = pipe_config->double_buf ? DBLB : 0; in usbhs_pipe_config_update()
/linux/drivers/staging/media/atomisp/pci/
H A Dsh_css_sp.c201 pipe->pipe_config = 0x0; /* No parameters */ in sh_css_sp_start_binary_copy()
272 pipe->pipe_config = in sh_css_sp_start_raw_copy()
275 pipe->pipe_config = pipe_conf_override; in sh_css_sp_start_raw_copy()
340 pipe->pipe_config = 0x0; /* No parameters */ in sh_css_sp_start_isys_copy()
1242 sh_css_sp_group.pipe[thread_id].pipe_config = in sh_css_sp_init_pipeline()
1251 sh_css_sp_group.pipe[thread_id].pipe_config = 0; in sh_css_sp_init_pipeline()
1299 sh_css_sp_group.pipe[thread_id].pipe_config |= (uint32_t) in sh_css_sp_init_pipeline()
H A Dia_css_pipe_public.h218 void ia_css_pipe_config_defaults(struct ia_css_pipe_config *pipe_config);
/linux/drivers/staging/media/atomisp/pci/runtime/binary/interface/
H A Dia_css_binary.h188 struct ia_css_pipe_config *pipe_config);
/linux/drivers/net/wireless/ath/ath10k/
H A Dpci.h183 struct ce_pipe_config *pipe_config; member

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