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Searched refs:pipe_bpp (Results 1 – 18 of 18) sorted by relevance

/linux/drivers/gpu/drm/i915/display/
H A Dintel_link_bw.c132 link_bpp_x16 = fxp_q4_from_int(crtc_state->pipe_bpp); in __intel_link_bw_reduce_bpp()
183 int pipe_bpp = min(crtc_state->pipe_bpp, in intel_link_bw_compute_pipe_bpp() local
186 pipe_bpp = rounddown(pipe_bpp, 2 * 3); in intel_link_bw_compute_pipe_bpp()
188 if (pipe_bpp < 6 * 3) in intel_link_bw_compute_pipe_bpp()
191 crtc_state->pipe_bpp = pipe_bpp; in intel_link_bw_compute_pipe_bpp()
H A Dintel_dp.c1188 int intel_dp_output_format_link_bpp_x16(enum intel_output_format output_format, int pipe_bpp) in intel_dp_output_format_link_bpp_x16() argument
1196 pipe_bpp /= 2; in intel_dp_output_format_link_bpp_x16()
1198 return fxp_q4_from_int(pipe_bpp); in intel_dp_output_format_link_bpp_x16()
1464 int pipe_bpp; in intel_dp_mode_valid() local
1470 pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX); in intel_dp_mode_valid()
1493 output_format, pipe_bpp, in intel_dp_mode_valid()
1699 bpc = crtc_state->pipe_bpp / 3; in intel_dp_max_bpp()
1794 pipe_config->pipe_bpp = bpp; in intel_dp_compute_link_config_wide()
2191 int pipe_bpp, int max_bpp_x16) in align_max_compressed_bpp_x16() argument
2194 int link_bpp_x16 = intel_dp_output_format_link_bpp_x16(output_format, pipe_bpp); in align_max_compressed_bpp_x16()
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H A Dintel_lvds.c302 if (crtc_state->dither && crtc_state->pipe_bpp == 18) in intel_pre_enable_lvds()
447 if (lvds_bpp != crtc_state->pipe_bpp && !crtc_state->bw_constrained) { in intel_lvds_compute_config()
450 crtc_state->pipe_bpp, lvds_bpp); in intel_lvds_compute_config()
451 crtc_state->pipe_bpp = lvds_bpp; in intel_lvds_compute_config()
H A Dintel_display.c2973 if (crtc_state->dither && crtc_state->pipe_bpp != 30) in i9xx_set_pipeconf()
2977 switch (crtc_state->pipe_bpp) { in i9xx_set_pipeconf()
2980 MISSING_CASE(crtc_state->pipe_bpp); in i9xx_set_pipeconf()
3073 pipe_config->pipe_bpp = 18; in i9xx_get_pipe_config()
3076 pipe_config->pipe_bpp = 24; in i9xx_get_pipe_config()
3079 pipe_config->pipe_bpp = 30; in i9xx_get_pipe_config()
3165 switch (crtc_state->pipe_bpp) { in ilk_set_pipeconf()
3168 MISSING_CASE(crtc_state->pipe_bpp); in ilk_set_pipeconf()
3253 switch (crtc_state->pipe_bpp) { in bdw_set_pipe_misc()
3269 MISSING_CASE(crtc_state->pipe_bpp); in bdw_set_pipe_misc()
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H A Dhsw_ips.c199 if (crtc_state->pipe_bpp > 24) in hsw_crtc_state_ips_capable()
H A Dintel_dp_mst.c431 crtc_state->pipe_bpp = fxp_q4_to_int(bpp_x16); in intel_dp_mtp_tu_compute_config()
467 crtc_state->pipe_bpp = limits->pipe.max_bpp; in mst_stream_dsc_compute_link_config()
1492 int pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX); in mst_connector_mode_valid_ctx() local
1501 INTEL_OUTPUT_FORMAT_RGB, pipe_bpp, in mst_connector_mode_valid_ctx()
H A Dicl_dsi.c1579 pipe_config->pipe_bpp = bdw_get_pipe_misc_bpp(crtc); in gen11_dsi_get_config()
1624 if (crtc_state->pipe_bpp < 8 * 3) in gen11_dsi_dsc_compute_config()
1691 pipe_config->pipe_bpp = 24; in gen11_dsi_compute_config()
1693 pipe_config->pipe_bpp = 18; in gen11_dsi_compute_config()
H A Dintel_crt.c458 if (crtc_state->bw_constrained && crtc_state->pipe_bpp < 24) { in hsw_crt_compute_config()
464 crtc_state->pipe_bpp = 24; in hsw_crt_compute_config()
H A Dintel_fdi.c314 pipe_config->pipe_bpp); in ilk_fdi_compute_config()
318 intel_link_compute_m_n(fxp_q4_from_int(pipe_config->pipe_bpp), in ilk_fdi_compute_config()
H A Dvlv_dsi.c299 pipe_config->pipe_bpp = 24; in intel_dsi_compute_config()
301 pipe_config->pipe_bpp = 18; in intel_dsi_compute_config()
1043 pipe_config->pipe_bpp = bdw_get_pipe_misc_bpp(crtc); in bxt_dsi_get_pipe_config()
H A Dintel_pfit.c537 if (DISPLAY_VER(display) < 4 && crtc_state->pipe_bpp == 18) in gmch_panel_fitting()
H A Dintel_vdsc.c316 vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3; in intel_dsc_compute_params()
H A Dintel_psr.c1584 max_bpp = crtc_state->pipe_bpp; in intel_psr2_config_valid()
1599 if (crtc_state->pipe_bpp > max_bpp) { in intel_psr2_config_valid()
1602 crtc_state->pipe_bpp, max_bpp); in intel_psr2_config_valid()
H A Dintel_display_types.h1165 int pipe_bpp; /* in 1 bpp units */ member
H A Dg4x_dp.c406 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); in intel_dp_get_config()
H A Dintel_tv.c1217 pipe_config->pipe_bpp = 8*3; in intel_tv_compute_config()
H A Dintel_bios.c3567 crtc_state->pipe_bpp = bpc * 3; in fill_dsc()
3569 crtc_state->dsc.compressed_bpp_x16 = fxp_q4_from_int(min(crtc_state->pipe_bpp, in fill_dsc()
H A Dintel_sdvo.c1376 pipe_config->pipe_bpp = 8*3; in intel_sdvo_compute_config()