| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 127 .phyclk_mhz = 600.0,
136 .phyclk_mhz = 810.0,
145 .phyclk_mhz = 810.0,
154 .phyclk_mhz = 810.0,
163 .phyclk_mhz = 810.0,
371 .phyclk_mhz = 600.0,
380 .phyclk_mhz = 810.0,
389 .phyclk_mhz = 810.0,
398 .phyclk_mhz = 810.0,
407 .phyclk_mhz = 810.0,
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn351/ |
| H A D | dcn351_fpu.c | 107 .phyclk_mhz = 600.0,
120 .phyclk_mhz = 810.0,
133 .phyclk_mhz = 810.0,
146 .phyclk_mhz = 810.0,
159 .phyclk_mhz = 810.0,
172 .phyclk_mhz = 810.0,
185 .phyclk_mhz = 810.0,
198 .phyclk_mhz = 810.0,
343 clock_limits[i].phyclk_mhz = in dcn351_update_bw_bounding_box_fpu()
344 dcn3_51_soc.clock_limits[closest_clk_lvl].phyclk_mhz; in dcn351_update_bw_bounding_box_fpu()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| H A D | dcn314_fpu.c | 108 .phyclk_mhz = 600.0,
117 .phyclk_mhz = 810.0,
126 .phyclk_mhz = 810.0,
135 .phyclk_mhz = 810.0,
144 .phyclk_mhz = 810.0,
254 clock_limits[i].phyclk_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].phyclk_mhz; in dcn314_update_bw_bounding_box_fpu()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| H A D | dcn301_fpu.c | 123 .phyclk_mhz = 600.0,
135 .phyclk_mhz = 600.0,
147 .phyclk_mhz = 810.0,
159 .phyclk_mhz = 810.0,
171 .phyclk_mhz = 810.0,
378 s[i].phyclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_mhz; in dcn301_fpu_update_bw_bounding_box()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn321/ |
| H A D | dcn321_fpu.c | 113 .phyclk_mhz = 810.0,
375 if (bw_params->clk_table.entries[i].phyclk_mhz > max_clk_data.phyclk_mhz) in build_synthetic_soc_states()
376 max_clk_data.phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; in build_synthetic_soc_states()
421 if (max_clk_data.phyclk_mhz == 0) in build_synthetic_soc_states()
422 max_clk_data.phyclk_mhz = dcn3_21_soc.clock_limits[0].phyclk_mhz; in build_synthetic_soc_states()
429 entry.phyclk_mhz = max_clk_data.phyclk_mhz; in build_synthetic_soc_states()
728 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) in dcn321_update_bw_bounding_box_fpu()
729 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; in dcn321_update_bw_bounding_box_fpu()
738 max_phyclk_mhz = dcn3_21_soc.clock_limits[0].phyclk_mhz; in dcn321_update_bw_bounding_box_fpu()
825 dcn3_21_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz; in dcn321_update_bw_bounding_box_fpu()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | dcn20_fpu.c | 229 .phyclk_mhz = 540.0,
240 .phyclk_mhz = 600.0,
251 .phyclk_mhz = 810.0,
262 .phyclk_mhz = 810.0,
273 .phyclk_mhz = 810.0,
285 .phyclk_mhz = 810.0,
340 .phyclk_mhz = 540.0,
351 .phyclk_mhz = 600.0,
362 .phyclk_mhz = 810.0,
373 .phyclk_mhz = 810.0,
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn302/ |
| H A D | dcn302_fpu.c | 119 .phyclk_mhz = 300.0,
230 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) in dcn302_fpu_update_bw_bounding_box()
231 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; in dcn302_fpu_update_bw_bounding_box()
240 max_phyclk_mhz = dcn3_02_soc.clock_limits[0].phyclk_mhz; in dcn302_fpu_update_bw_bounding_box()
327 dcn3_02_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz; in dcn302_fpu_update_bw_bounding_box()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn303/ |
| H A D | dcn303_fpu.c | 118 .phyclk_mhz = 300.0,
226 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) in dcn303_fpu_update_bw_bounding_box()
227 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; in dcn303_fpu_update_bw_bounding_box()
236 max_phyclk_mhz = dcn3_03_soc.clock_limits[0].phyclk_mhz; in dcn303_fpu_update_bw_bounding_box()
333 dcn3_03_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz; in dcn303_fpu_update_bw_bounding_box()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn35/ |
| H A D | dcn35_fpu.c | 124 .phyclk_mhz = 600.0,
133 .phyclk_mhz = 810.0,
142 .phyclk_mhz = 810.0,
151 .phyclk_mhz = 810.0,
160 .phyclk_mhz = 810.0,
309 clock_limits[i].phyclk_mhz = in dcn35_update_bw_bounding_box_fpu()
310 dcn3_5_soc.clock_limits[closest_clk_lvl].phyclk_mhz; in dcn35_update_bw_bounding_box_fpu()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/ |
| H A D | dml2_policy.c | 149 if (p->in_states->state_array[i].phyclk_mhz > max_phyclk_mhz) in dml2_policy_build_synthetic_soc_states()
150 max_phyclk_mhz = (int)p->in_states->state_array[i].phyclk_mhz; in dml2_policy_build_synthetic_soc_states()
170 s->entry.phyclk_mhz = max_phyclk_mhz; in dml2_policy_build_synthetic_soc_states()
173 s->entry.phyclk_mhz = max_phyclk_mhz; in dml2_policy_build_synthetic_soc_states()
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| H A D | dml2_translation_helper.c | 362 p->in_states->state_array[0].phyclk_mhz = 810; in dml2_init_soc_states()
398 p->in_states->state_array[0].phyclk_mhz = 810; in dml2_init_soc_states()
435 p->in_states->state_array[0].phyclk_mhz = 810; in dml2_init_soc_states()
581 if (p->in_states->state_array[i].phyclk_mhz > max_phyclk_mhz) in dml2_init_soc_states()
582 max_phyclk_mhz = (int)p->in_states->state_array[i].phyclk_mhz; in dml2_init_soc_states()
594 p->out_states->state_array[i].phyclk_mhz = max_phyclk_mhz; in dml2_init_soc_states()
597 p->out_states->state_array[i].phyclk_mhz = max_phyclk_mhz; in dml2_init_soc_states()
732 out->state_array[i].phyclk_mhz = dc->dml.soc.clock_limits[i].phyclk_mhz; in dml2_translate_soc_states()
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| H A D | display_mode_util.c | 625 dml_print("DML: state_bbox: phyclk_mhz = %f\n", state->phyclk_mhz); in dml_print_soc_state_bounding_box()
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| H A D | display_mode_core_structs.h | 280 dml_float_t phyclk_mhz; member
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| H A D | display_mode_core.c | 7165 mode_lib->ms.state.phyclk_mhz, in dml_core_mode_support()
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_socbb.h | 34 uint32_t phyclk_mhz; member
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn201/ |
| H A D | dcn201_resource.c | 148 .phyclk_mhz = 810.0,
159 .phyclk_mhz = 810.0,
170 .phyclk_mhz = 810.0,
181 .phyclk_mhz = 810.0,
193 .phyclk_mhz = 810.0,
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| H A D | dcn35_clk_mgr.c | 1087 bw_params->clk_table.entries[i].phyclk_mhz = bw_params->clk_table.entries[j].phyclk_mhz; in dcn35_clk_mgr_helper_populate_bw_params()
1135 bw_params->clk_table.entries[i].phyclk_mhz = def_max.phyclk_mhz; in dcn35_clk_mgr_helper_populate_bw_params()
1165 if (!bw_params->clk_table.entries[i].phyclk_mhz) in dcn35_clk_mgr_helper_populate_bw_params()
1166 bw_params->clk_table.entries[i].phyclk_mhz = def_max.phyclk_mhz; in dcn35_clk_mgr_helper_populate_bw_params()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | dcn32_fpu.c | 134 .phyclk_mhz = 810.0,
2687 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) in dcn32_patch_dpm_table()
2688 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; in dcn32_patch_dpm_table()
2833 if (bw_params->clk_table.entries[i].phyclk_mhz > max_clk_data.phyclk_mhz) in build_synthetic_soc_states()
2834 max_clk_data.phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; in build_synthetic_soc_states()
2879 if (max_clk_data.phyclk_mhz == 0) in build_synthetic_soc_states()
2880 max_clk_data.phyclk_mhz = dcn3_2_soc.clock_limits[0].phyclk_mhz; in build_synthetic_soc_states()
2887 entry.phyclk_mhz = max_clk_data.phyclk_mhz; in build_synthetic_soc_states()
3176 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) in dcn32_update_bw_bounding_box_fpu()
3177 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; in dcn32_update_bw_bounding_box_fpu()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| H A D | dcn30_clk_mgr.c | 161 &clk_mgr_base->bw_params->clk_table.entries[0].phyclk_mhz, in dcn3_init_clocks()
469 unsigned int i, max_phyclk_req = clk_mgr_base->bw_params->clk_table.entries[0].phyclk_mhz * 1000; in dcn30_notify_link_rate_change()
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| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | clk_mgr.h | 124 unsigned int phyclk_mhz; member
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| H A D | dcn30_fpu.c | 131 .phyclk_mhz = 300.0,
541 dcn30_bb_max_clk->max_phyclk_mhz = dcn3_0_soc.clock_limits[0].phyclk_mhz; in dcn30_fpu_update_max_clk()
590 dcn3_0_soc.clock_limits[i].phyclk_mhz = dcn30_bb_max_clk->max_phyclk_mhz; in dcn30_fpu_update_bw_bounding_box()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| H A D | display_mode_structs.h | 167 double phyclk_mhz; member
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| H A D | display_mode_vba.c | 398 mode_lib->vba.PHYCLKPerState[i] = soc->clock_limits[i].phyclk_mhz; in fetch_socbb_params()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| H A D | dcn30_resource.c | 2165 if (bw_params->clk_table.entries[i].phyclk_mhz > dcn30_bb_max_clk.max_phyclk_mhz) in dcn30_update_bw_bounding_box()
2166 dcn30_bb_max_clk.max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; in dcn30_update_bw_bounding_box()
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